[ { num => 5, text => [ { col => undef, table => undef, text => "1.1" }, { col => undef, table => undef, text => "About this Manual" }, { col => undef, table => undef, text => "1.2" }, { col => undef, table => undef, text => "Nomenclature and Conventions" }, { col => undef, table => undef, text => "1.2.1" }, { col => undef, table => undef, text => "Numeric Representations" }, { col => undef, table => undef, text => "1.2.2" }, { col => undef, table => undef, text => "Register Description" }, { col => "heading", table => 0, text => "DST_HEIGHT_WIDTH_8 - W - 32 bits - [MMReg:0x158C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DST_WIDTH" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Destination Width Note: This is an initiator register. Y is incremented ", }, { col => 3, table => 0, text => "at end of blit. Write 15: 0 to E2_DST_X, Write 31: 16 to ", }, { col => 3, table => 0, text => "E2_DST_WIDTH, then signal blit_start. E2_DST_Y = E2_DEST_Y ", }, { col => 3, table => 0, text => "(+/-) E2_DST_HEIGHT as function of direction after blit is complete", }, { col => 0, table => 0, text => "DST_HEIGHT" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Destination Height Write 15: 0 to E2_DST_Y, Write 31: 16 to ", }, { col => undef, table => undef, text => "E2_DST_HEIGHT" }, { col => undef, table => undef, text => "[ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to 256 (ZERO extent)", }, ], }, { num => 6, text => [ { col => undef, table => undef, text => "Table 1-1 Register description table notation", }, { col => 0, table => 0, text => "Register Information" }, { col => 1, table => 0, text => "Example" }, { col => 0, table => 0, text => "Register name" }, { col => 1, table => 0, text => "DST_HEIGHT_WIDTH_8" }, { col => 0, table => 0, text => "Read / Write capability" }, { col => 0, table => 0, text => " R = Readable" }, { col => 0, table => 0, text => " W = Writable" }, { col => 0, table => 0, text => " RW = Readable and Writable" }, { col => 1, table => 0, text => "W" }, { col => 0, table => 0, text => "Register size" }, { col => 1, table => 0, text => "32 bits" }, { col => 0, table => 0, text => "Register address(es)*" }, { col => 1, table => 0, text => "MMReg:0x158C" }, { col => 0, table => 0, text => "Field name" }, { col => 1, table => 0, text => "DST_WIDTH" }, { col => 0, table => 0, text => "Field position/size" }, { col => 1, table => 0, text => "23:16" }, { col => 0, table => 0, text => "Field default value" }, { col => 1, table => 0, text => "0x0" }, { col => 0, table => 0, text => "Field description " }, { col => 1, table => 0, text => "Destination....complete" }, { col => 0, table => 0, text => "Field mirror information" }, { col => 1, table => 0, text => "(mirror bits 0:7 of DST_WIDTH:DST_WIDTH)", }, { col => 0, table => 0, text => "Brief register description" }, { col => 1, table => 0, text => "[ W] (Reserved) 15: 0 DST_WIDTH 23: 16 Destination width: range 0 to ", }, { col => 1, table => 0, text => "256 (ZERO extent)" }, { col => 0, table => 0, text => "* Note:" }, { col => 0, table => 0, text => "There may be more than one address; the convention used is as follows:", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName:offset]" }, { col => 0, table => 0, text => " - single mapping, to one aperture/decode and one offset", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName1, aperName2, \\205, aperNameN:offset]", }, { col => 0, table => 0, text => " - multiple mappings to different apertures/decodes but same offset", }, { col => 0, table => 0, text => " " }, { col => 0, table => 0, text => "[aperName:startOffset-endOffset]" }, { col => 0, table => 0, text => " - mapped to an offset range in the same aperture/decode", }, ], }, { num => 8, text => [ { col => undef, table => undef, text => "2.1" }, { col => undef, table => undef, text => "Memory Controller Registers" }, { col => "heading", table => 0, text => "MC_SEQ_CNTL - RW - 32 bits - [GpuF0MMReg:0x2600]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MEM_ADDR_MAP_COLS" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=2**8 columns " }, { col => 3, table => 0, text => " 1=2**9 columns " }, { col => 3, table => 0, text => " 2=2**10 columns " }, { col => 3, table => 0, text => " 3=reserved " }, { col => 0, table => 0, text => "MEM_ADDR_MAP_BANK" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=4 banks " }, { col => 3, table => 0, text => " 1=8 banks " }, { col => 0, table => 0, text => "SAFE_MODE" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable safe mode " }, { col => 3, table => 0, text => " 1=Ensure closing all pages before doing refresh ", }, { col => 3, table => 0, text => " 2=Ensure closing page before access a different page in ", }, { col => 3, table => 0, text => "the same bank " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "CHANNEL_DISABLE" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field allows the user to " }, { col => 3, table => 0, text => "disable the mclk branch for the specific unused channel. ", }, { col => 3, table => 0, text => "NOT FOR 600 " }, { col => 0, table => 0, text => "PIPE_DELAY_OUT" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "This field specifies pipeline " }, { col => 3, table => 0, text => "delay between mc & io. This field is NOT CONFIGURABLE ", }, { col => 3, table => 0, text => "for a specific ASIC " }, { col => 3, table => 0, text => "for 600: 0 " }, { col => 3, table => 0, text => "for " }, { col => 3, table => 0, text => "610: 0 " }, { col => 3, table => 0, text => "for 630: 1 " }, { col => 3, table => 0, text => " 0=No pipeline delay between MC/IO for outgoing signals ", }, { col => 3, table => 0, text => " 1=pipeline delay " }, { col => 0, table => 0, text => "PIPE_DELAY_IN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "This field specifies pipeline " }, { col => 3, table => 0, text => "delay between mc & io. This field is NOT CONFIGURABLE ", }, { col => 3, table => 0, text => "for a specific ASIC " }, { col => 3, table => 0, text => "for 600: 0 " }, { col => 3, table => 0, text => "for " }, { col => 3, table => 0, text => "610: 0 " }, { col => 3, table => 0, text => "for 630: 1 " }, { col => 3, table => 0, text => " 0=No pipeline delay between MC/IO for incoming signals ", }, { col => 3, table => 0, text => " 1=pipeline delay " }, { col => 0, table => 0, text => "MSKOFF_DAT_TL" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, tie the corresponding dq to 0 ONLY 1 bit could be ", }, { col => 3, table => 0, text => "set to 1 among MSKOFF_DAT_TL, MSKOFF_DAT_TH, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_AC " }, { col => 3, table => 0, text => " 1=Tie low for the DQ whose corresponding DQM is on ", }, { col => 0, table => 0, text => "MSKOFF_DAT_TH" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, tie the corresponding dq to 1 ONLY 1 bit could be ", }, { col => 3, table => 0, text => "set to 1 among MSKOFF_DAT_TL, MSKOFF_DAT_TH, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_AC " }, { col => 3, table => 0, text => " 1=Tie high for the DQ whose corresponding DQM is on ", }, { col => 0, table => 0, text => "MSKOFF_DAT_AC" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "for the byte which has data " }, { col => 3, table => 0, text => "mask on, keep the previous dq value to avoid toggleing ", }, { col => 3, table => 0, text => "ONLY 1 bit could be set to 1 among MSKOFF_DAT_TL, ", }, { col => 3, table => 0, text => "MSKOFF_DAT_TH, MSKOFF_DAT_AC " }, { col => undef, table => undef, text => " 1=no toggling for the DQ whose corresponding DQM is on ", }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "This register specifies specific seq configuration ", }, { col => "heading", table => 1, text => "MC_SEQ_DRAM - RW - 32 bits - [GpuF0MMReg:0x2608]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ADR_2CK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of cycle(s) to send an address. One cycle ", }, { col => 3, table => 1, text => "for non-DDR4. Two cycles for DDR4.", }, { col => 3, table => 1, text => " 0=One-cycle address " }, { col => 3, table => 1, text => " 1=Two-cycle address " }, ], }, { num => 9, text => [ { col => 0, table => 0, text => "ADR_MUX" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Address bus is shared between two channels or not. ", }, { col => 3, table => 0, text => "Not shared for DDR4. Shared for non-DDR4.", }, { col => 3, table => 0, text => " 0=Address bus is not shared " }, { col => 3, table => 0, text => " 1=Address bus is shared " }, { col => 0, table => 0, text => "ADR_DF1" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for address bus (during NOP).", }, { col => 3, table => 0, text => " 0=Address default low " }, { col => 3, table => 0, text => " 1=Address default high " }, { col => 0, table => 0, text => "AP8" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Location of auto-precharge bit.", }, { col => 3, table => 0, text => " 0=AP bit starts at MSB+1 " }, { col => 3, table => 0, text => " 1=AP bit is bit 8 " }, { col => 0, table => 0, text => "DAT_DF1" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for data bus.", }, { col => 3, table => 0, text => " 0=DAT default low " }, { col => 3, table => 0, text => " 1=DAT default high " }, { col => 0, table => 0, text => "DQS_DF1" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for write strobes.", }, { col => 3, table => 0, text => " 0=DQS default low " }, { col => 3, table => 0, text => " 1=DQS default high " }, { col => 0, table => 0, text => "DQM_DF1" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Default value for write mask.", }, { col => 3, table => 0, text => " 0=DQM default low " }, { col => 3, table => 0, text => " 1=DQM default high " }, { col => 0, table => 0, text => "DQM_ACT" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Polarity of data mask. Active low for DDR4. Active ", }, { col => 3, table => 0, text => "high for non- DDR4." }, { col => 3, table => 0, text => " 0=DQM active low " }, { col => 3, table => 0, text => " 1=DQM active high " }, { col => 0, table => 0, text => "STB_CNT" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0xf" }, { col => 3, table => 0, text => " DRAM standby counter. Number of idle cycles ", }, { col => 3, table => 0, text => "before dynamic CKE is enabled. This prevents the ", }, { col => 3, table => 0, text => "CKE from turning off too easily." }, { col => 0, table => 0, text => "CKE_DYN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Dynamic CKE." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CKE_ACT" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Polarity of clock enable. Active low for DDR4. Active ", }, { col => 3, table => 0, text => "high for non- DDR4." }, { col => 3, table => 0, text => " 0=Active low " }, { col => 3, table => 0, text => " 1=Active high " }, { col => 0, table => 0, text => "BO4" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " DRAM burst size." }, { col => 3, table => 0, text => " 0=DRAM is burst of 8 " }, { col => 3, table => 0, text => " 1=DRAM is burst of 4 " }, { col => 0, table => 0, text => "DLL_CLR" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Resets DLL lock timer. DRAM power up is ", }, { col => 3, table => 0, text => "completed once the DLL lock time is reached. If the ", }, { col => 3, table => 0, text => "DLL lock timer is reset, the DRAM power up flag is ", }, { col => 3, table => 0, text => "deasserted." }, { col => 3, table => 0, text => " 0=Not reset DLL timer " }, { col => 3, table => 0, text => " 1=Reset DLL timer " }, { col => 0, table => 0, text => "DLL_CNT" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0xf" }, { col => 3, table => 0, text => " DRAM DLL lock time in multiples of 256 mclk cycles.", }, { col => 0, table => 0, text => "DAT_INV" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Enables/disables DDR write data inversion mode.", }, { col => 3, table => 0, text => " 0=Disable write data inversion " }, { col => 3, table => 0, text => " 1=Enable write data inversion " }, { col => 0, table => 0, text => "INV_ACM" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Selects DDR write data inversion mode.", }, { col => 3, table => 0, text => " 0=DC mode " }, { col => 3, table => 0, text => " 1=AC mode " }, { col => 0, table => 0, text => "ODT_ENB" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable ODT " }, { col => 3, table => 0, text => " 1=Enable ODT " }, { col => 0, table => 0, text => "ODT_ACT" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=ODT active low " }, { col => 3, table => 0, text => " 1=ODT active high " }, { col => 0, table => 0, text => "RST_CTL" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Controls DRAM reset pin. Channel B only.", }, { col => 3, table => 0, text => " 0=Drive reset low " }, { col => 3, table => 0, text => " 1=Drive reset high " }, { col => 0, table => 0, text => "TRI_MIO_DYN" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => " 1=Tristate cmd/data/addr during dynamic cke ", }, { col => undef, table => undef, text => " This register specifies the character of the DRAM interface.", }, ], }, { num => 10, text => [ { col => "heading", table => 0, text => "MC_SEQ_RAS_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x260C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TRCDW" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 0, text => "TRCDWA" }, { col => 1, table => 0, text => "9:5" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => " Number of cycles from active to write with ", }, { col => 3, table => 0, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 0, text => "Otherwise the same as TRCDW." }, { col => 0, table => 0, text => "TRCDR" }, { col => 1, table => 0, text => "14:10" }, { col => 2, table => 0, text => "0xd" }, { col => 3, table => 0, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 0, text => "TRCDRA" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0xd" }, { col => 3, table => 0, text => " Number of cycles from active to read with ", }, { col => 3, table => 0, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 0, text => "Otherwise the same as TRCDR." }, { col => 0, table => 0, text => "TRRD" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x5" }, { col => 3, table => 0, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 0, text => "b - 1." }, { col => 0, table => 0, text => "TRC" }, { col => 1, table => 0, text => "30:24" }, { col => 2, table => 0, text => "0x27" }, { col => 3, table => 0, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for performance mode.", }, { col => "heading", table => 1, text => "MC_SEQ_CAS_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x2610]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TNOPW" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 1, text => "debugging purpose only." }, { col => 0, table => 1, text => "TNOPR" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 1, text => "debugging purpose only." }, { col => 0, table => 1, text => "TR2W" }, { col => 1, table => 1, text => "8:4" }, { col => 2, table => 1, text => "0x9" }, { col => 3, table => 1, text => " Read to write turn around time - 1.", }, { col => 0, table => 1, text => "TR2R" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 1, text => "TW2R" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0x9" }, { col => 3, table => 1, text => " Write to read turn around time - 1.", }, { col => 0, table => 1, text => "TCL" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for performance mode.", }, { col => "heading", table => 2, text => "MC_SEQ_MISC_TIMING_P - RW - 32 bits - [GpuF0MMReg:0x2614]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TRP_WRA" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x15" }, { col => 3, table => 2, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 2, text => "TCKE_HI" }, { col => 1, table => 2, text => "7:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " " }, { col => 3, table => 2, text => "2 MSB of " }, { col => 3, table => 2, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 2, text => "TRP_RDA" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x11" }, { col => 3, table => 2, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 2, text => "TRP" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0xb" }, { col => 3, table => 2, text => " Precharge command period - 1.", }, { col => 0, table => 2, text => "TRFC" }, { col => 1, table => 2, text => "26:20" }, { col => 2, table => 2, text => "0x2f" }, { col => 3, table => 2, text => " Auto-refresh command period - 1.", }, { col => 0, table => 2, text => "TCKE" }, { col => 1, table => 2, text => "31:28" }, { col => 2, table => 2, text => "0x4" }, { col => undef, table => undef, text => " 4 LSB CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for performance mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING2_P - RW - 32 bits - [GpuF0MMReg:0x2618]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "PA2RDATA" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " " }, { col => 3, table => 3, text => "Read " }, { col => 3, table => 3, text => "Preamble for DDR4. " }, { col => 0, table => 3, text => "PA2WDATA" }, { col => 1, table => 3, text => "6:4" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " Write " }, { col => 3, table => 3, text => "Preamble for DDR4. " }, { col => 0, table => 3, text => "FAW" }, { col => 1, table => 3, text => "12:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " Four Active " }, { col => 3, table => 3, text => "Window/2 - 5 in MCLK " }, ], }, { num => 11, text => [ { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for performance mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x261C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for balanced mode", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x2620]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for balanced mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_B - RW - 32 bits - [GpuF0MMReg:0x2624]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TRP" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0xb" }, { col => 3, table => 3, text => " Precharge command period - 1.", }, { col => 0, table => 3, text => "TRFC" }, { col => 1, table => 3, text => "26:20" }, { col => 2, table => 3, text => "0x2f" }, { col => 3, table => 3, text => " Auto-refresh command period - 1.", }, { col => 0, table => 3, text => "TCKE" }, { col => 1, table => 3, text => "31:28" }, { col => 2, table => 3, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for balanced mode.", }, { col => undef, table => undef, text => "MC_SEQ_MISC_TIMING2_B - RW - 32 bits - [GpuF0MMReg:0x2628]", }, ], }, { num => 12, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PA2RDATA" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Read " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "PA2WDATA" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "FAW" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for balanced mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x262C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for battery mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x2630]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for battery mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_S - RW - 32 bits - [GpuF0MMReg:0x2634]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " " }, { col => 3, table => 3, text => "2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TRP" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0xb" }, { col => 3, table => 3, text => " Precharge command period - 1.", }, { col => 0, table => 3, text => "TRFC" }, { col => 1, table => 3, text => "26:20" }, { col => 2, table => 3, text => "0x2f" }, { col => 3, table => 3, text => " Auto-refresh command period - 1.", }, { col => 0, table => 3, text => "TCKE" }, { col => 1, table => 3, text => "31:28" }, { col => 2, table => 3, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for battery mode.", }, ], }, { num => 13, text => [ { col => "heading", table => 0, text => "MC_SEQ_MISC_TIMING2_S - RW - 32 bits - [GpuF0MMReg:0x2638]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PA2RDATA" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Read " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "PA2WDATA" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write " }, { col => 3, table => 0, text => "Preamble for DDR4. " }, { col => 0, table => 0, text => "FAW" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "TCKE_PULSE" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for battery mode.", }, { col => "heading", table => 1, text => "MC_SEQ_RAS_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x263C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TRCDW" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write - 1.", }, { col => 0, table => 1, text => "TRCDWA" }, { col => 1, table => 1, text => "9:5" }, { col => 2, table => 1, text => "0xa" }, { col => 3, table => 1, text => " Number of cycles from active to write with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDW." }, { col => 0, table => 1, text => "TRCDR" }, { col => 1, table => 1, text => "14:10" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read - 1.", }, { col => 0, table => 1, text => "TRCDRA" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0xd" }, { col => 3, table => 1, text => " Number of cycles from active to read with ", }, { col => 3, table => 1, text => "auto-precharge - 1. A special case for DDR1. ", }, { col => 3, table => 1, text => "Otherwise the same as TRCDR." }, { col => 0, table => 1, text => "TRRD" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => " Number of cycles from active bank a to active bank ", }, { col => 3, table => 1, text => "b - 1." }, { col => 0, table => 1, text => "TRC" }, { col => 1, table => 1, text => "30:24" }, { col => 2, table => 1, text => "0x27" }, { col => 3, table => 1, text => " Number of cycles from active to active/auto refresh ", }, { col => undef, table => undef, text => "- 1." }, { col => undef, table => undef, text => " RAS related parameters in hclk cycles for context switch mode for context switch mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CAS_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x2640]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TNOPW" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive write bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TNOPR" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Extra cycle(s) between successive read bursts. For ", }, { col => 3, table => 2, text => "debugging purpose only." }, { col => 0, table => 2, text => "TR2W" }, { col => 1, table => 2, text => "8:4" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Read to write turn around time - 1.", }, { col => 0, table => 2, text => "TR2R" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => " Read to read time - 1 (different rank).", }, { col => 0, table => 2, text => "TW2R" }, { col => 1, table => 2, text => "20:16" }, { col => 2, table => 2, text => "0x9" }, { col => 3, table => 2, text => " Write to read turn around time - 1.", }, { col => 0, table => 2, text => "TCL" }, { col => 1, table => 2, text => "28:24" }, { col => 2, table => 2, text => "0x6" }, { col => undef, table => undef, text => " CAS to data return latency - 2 (0 to 20).", }, { col => undef, table => undef, text => " CAS related paramters in hclk cycles for context switch mode.", }, { col => "heading", table => 3, text => "MC_SEQ_MISC_TIMING_C - RW - 32 bits - [GpuF0MMReg:0x2644]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TRP_WRA" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x15" }, { col => 3, table => 3, text => " From write with auto-prechrage to active - 1.", }, { col => 0, table => 3, text => "TCKE_HI" }, { col => 1, table => 3, text => "7:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 2 MSB of " }, { col => 3, table => 3, text => "tCKE parameters, used to control exit power down time. ", }, { col => 0, table => 3, text => "TRP_RDA" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x11" }, { col => 3, table => 3, text => " From read with auto-prechrage to active - 1.", }, ], }, { num => 14, text => [ { col => 0, table => 0, text => "TRP" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0xb" }, { col => 3, table => 0, text => " Precharge command period - 1.", }, { col => 0, table => 0, text => "TRFC" }, { col => 1, table => 0, text => "26:20" }, { col => 2, table => 0, text => "0x2f" }, { col => 3, table => 0, text => " Auto-refresh command period - 1.", }, { col => 0, table => 0, text => "TCKE" }, { col => 1, table => 0, text => "31:28" }, { col => 2, table => 0, text => "0x4" }, { col => undef, table => undef, text => " CKE power down exit timer.", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for context switch mode.", }, { col => "heading", table => 1, text => "MC_SEQ_MISC_TIMING2_C - RW - 32 bits - [GpuF0MMReg:0x2648]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PA2RDATA" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Read " }, { col => 3, table => 1, text => "Preamble for DDR4. " }, { col => 0, table => 1, text => "PA2WDATA" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Write " }, { col => 3, table => 1, text => "Preamble for DDR4. " }, { col => 0, table => 1, text => "FAW" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "TCKE_PULSE" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " minimum " }, { col => undef, table => undef, text => "power down period/power up period ", }, { col => undef, table => undef, text => " Misc. DRAM parameters in hclk cycles for context switch mode.", }, { col => "heading", table => 2, text => "MC_SEQ_CMD - RW - 32 bits - [GpuF0MMReg:0x26C4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ADR" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " This field is mapped directly to the address bus.", }, { col => 0, table => 2, text => "MOP" }, { col => 1, table => 2, text => "18:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " DRAM command." }, { col => 3, table => 2, text => " 0=NOP " }, { col => 3, table => 2, text => " 1=Load mode register " }, { col => 3, table => 2, text => " 2=Precharge " }, { col => 3, table => 2, text => " 3=Auto-refresh " }, { col => 3, table => 2, text => " 4=Self-refresh " }, { col => 0, table => 2, text => "END" }, { col => 1, table => 2, text => 20 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " If set, the DLL lock timer starts counting. Once it ", }, { col => 3, table => 2, text => "reaches a pre- defined value, the DLL is stabilized ", }, { col => 3, table => 2, text => "and DRAM power up sequence is completed. See ", }, { col => 3, table => 2, text => "also DLL_CNT inside MC_SEQ_DRAM." }, { col => 3, table => 2, text => " 0=Not last operation " }, { col => 3, table => 2, text => " 1=Last operation, wait for DLL to stabilize ", }, { col => 0, table => 2, text => "CSB" }, { col => 1, table => 2, text => "22:21" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Allows rank 0 and rank 1 to be selected ", }, { col => 3, table => 2, text => "independently." }, { col => 3, table => 2, text => " 0=Select both ranks " }, { col => 3, table => 2, text => " 1=Select rank 1 " }, { col => 3, table => 2, text => " 2=Select rank 0 " }, { col => 3, table => 2, text => " 3=Select none " }, { col => 0, table => 2, text => "CHAN0" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Select channel 0 " }, { col => 3, table => 2, text => " 1=Not select channel 0 " }, { col => 0, table => 2, text => "CHAN1" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Select channel 1 " }, { col => undef, table => undef, text => " 1=Not select channel 1 " }, { col => undef, table => undef, text => " Command register for DRAM initialization.", }, { col => "heading", table => 3, text => "MC_PMG_CMD - RW - 32 bits - [GpuF0MMReg:0x26CC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ADR" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " The value of the mode register for resetting DRAM ", }, { col => 3, table => 3, text => "DLL." }, ], }, { num => 15, text => [ { col => 0, table => 0, text => "MOP" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Operation" }, { col => 3, table => 0, text => " 0=NOP " }, { col => 3, table => 0, text => " 1=Reset DLL " }, { col => 3, table => 0, text => " 2=Precharge All " }, { col => 3, table => 0, text => " 3=Auto-refresh " }, { col => 3, table => 0, text => " 4=Self-refresh " }, { col => 0, table => 0, text => "END" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field is not used." }, { col => 3, table => 0, text => " 0=Not last operation " }, { col => 3, table => 0, text => " 1=Last operation, wait for DLL to stabilize ", }, { col => 0, table => 0, text => "CSB" }, { col => 1, table => 0, text => "22:21" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " This field is not used." }, { col => 3, table => 0, text => " 0=Select both ranks " }, { col => 3, table => 0, text => " 1=Select rank 1 " }, { col => 3, table => 0, text => " 2=Select rank 0 " }, { col => undef, table => undef, text => " 3=Select none " }, { col => undef, table => undef, text => " Power manager command register. This register specifies the value used for resetting the DRAM DLL.", }, { col => "heading", table => 1, text => "MC_PMG_CFG - RW - 32 bits - [GpuF0MMReg:0x26D0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SYC_CLK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls mclk/yclk synchronization after on-chip ", }, { col => 3, table => 1, text => "DLL is reset." }, { col => 3, table => 1, text => " 0=Don't synchronize YCLK/MCLK after DLL is reset ", }, { col => 3, table => 1, text => " 1=Synchronize YCLK/MCLK after DLL is reset ", }, { col => 0, table => 1, text => "RST_DLL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls DRAM DLL reset after waking up from ", }, { col => 3, table => 1, text => "self-refresh." }, { col => 3, table => 1, text => " 0=Don't reset DRAM DLL after self-refresh ", }, { col => 3, table => 1, text => " 1=Reset DRAM DLL after self-refresh " }, { col => 0, table => 1, text => "TRI_MIO" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Controls memory IO tristate during power down.", }, { col => 3, table => 1, text => " 0=Don't tri-state DRAM CMD and CLK signals dring ", }, { col => 3, table => 1, text => "self-refresh " }, { col => 3, table => 1, text => " 1=tri-state DRAM CMD and CLK signals druing ", }, { col => 3, table => 1, text => "self-refresh " }, { col => 0, table => 1, text => "XSR_TMR" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Multiple of 16 mclk cycles to wait before resetting ", }, { col => 3, table => 1, text => "DRAM DLL." }, { col => 0, table => 1, text => "AUTO_SLF" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Enable " }, { col => 3, table => 1, text => "automatic selfrefresh mode " }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "AUTO_SLF_IDLE_CNT" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of " }, { col => 3, table => 1, text => "idle cycles memory stays before put the memory into self ", }, { col => 3, table => 1, text => "refresh mode " }, { col => 3, table => 1, text => " 1=256*2 " }, { col => 3, table => 1, text => " 2=256*3 " }, { col => 3, table => 1, text => " 3=256*4 " }, { col => 3, table => 1, text => " 4=256*5 " }, { col => 3, table => 1, text => " 5=256*6 " }, { col => 3, table => 1, text => " 6=256*7 " }, { col => 3, table => 1, text => " 7=256*8 " }, { col => 3, table => 1, text => " 8=256*9 " }, { col => 3, table => 1, text => " 9=256*10 " }, { col => 3, table => 1, text => " 10=256*11 " }, { col => 3, table => 1, text => " 11=256*12 " }, { col => 3, table => 1, text => " 12=256*13 " }, { col => 3, table => 1, text => " 13=256*14 " }, { col => 3, table => 1, text => " 14=256*15 " }, { col => 0, table => 1, text => "SLF_IDLE_CNT" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Number of " }, { col => 3, table => 1, text => "SEQ idle cycles after SEQ receiving self-refresh command ", }, { col => 3, table => 1, text => "to the time SEQ issue the self-refresh command - 16 ", }, ], }, { num => 16, text => [ { col => 0, table => 0, text => "WRITE_DURING_DLOCK" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=no write during dll lock time " }, { col => 3, table => 0, text => " 1=allow write transaction during dll lock time ", }, { col => 0, table => 0, text => "EARLY_ACK_DYN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ack out-of-slf when DLL is locked " }, { col => 3, table => 0, text => " 1=ack out-of-slf when tXSNR expires " }, { col => 0, table => 0, text => "EARLY_ACK_ACPI" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ack out-of-slf when DLL is locked " }, { col => 3, table => 0, text => " 1=ack out-of-slf when tXSNR expires " }, { col => 0, table => 0, text => "UNUSED_SEQ_SHUTDOWN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=keep mclk branch running for unused SEQ pair ", }, { col => undef, table => undef, text => " 1=shut off unused SEQ pair " }, { col => undef, table => undef, text => " Power manager configuration register.", }, { col => "heading", table => 1, text => "MC_IMP_CNTL - RW - 32 bits - [GpuF0MMReg:0x26D4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MEM_IO_UPDATE_RATE" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0x16" }, { col => 3, table => 1, text => "Update the impedance value to the PMTEST every ", }, { col => 3, table => 1, text => "2^MEM_IO_UPDATE_DELAY cycles" }, { col => 0, table => 1, text => "MEM_IO_PMCOMP_STRD2" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "MEM_IO_SAMPLE_DELAY" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x6" }, { col => 3, table => 1, text => "Calibration Unit will sample every " }, { col => 3, table => 1, text => "2^MEM_IO_SAMPLE_DELAY cycles" }, { col => 0, table => 1, text => "MEM_IO_SAMPLE_CNT" }, { col => 1, table => 1, text => "15:13" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "Number of samples to be taken before update value to IO", }, { col => 0, table => 1, text => "MEM_IO_INC_THRESHOLD" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0xe" }, { col => 3, table => 1, text => "Number of '1' get detected during 15 cycles before increase ", }, { col => 3, table => 1, text => "impedance value" }, { col => 0, table => 1, text => "MEM_IO_DEC_THRESHOLD" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x6" }, { col => 3, table => 1, text => "Number of '0' get detected during 15 cycles before ", }, { col => 3, table => 1, text => "decrease impedance value" }, { col => 0, table => 1, text => "CAL_WHEN_IDLE" }, { col => 1, table => 1, text => 29 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "CAL_WHEN_REFRESH" }, { col => 1, table => 1, text => 30 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "MEM_IMP_EN" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Impedance Calibration Control" }, { col => "heading", table => 2, text => "MC_IMP_DEBUG - RW - 32 bits - [GpuF0MMReg:0x2878]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MEM_IMP_DEBUG_N" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MEM_IMP_DEBUG_P" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MEM_IO_IMP_DEBUG_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "MEM_STATUS_SEL" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Vertical " }, { col => 3, table => 2, text => " 1=Horizontal " }, { col => "heading", table => 3, text => "MC_IMP_STATUS - RW - 32 bits - [GpuF0MMReg:0x2874]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "IMP_N_MEM_DQ_SN_I0 (R)" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_MEM_DQ_SP_I0 (R)" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_N_MEM_DQ_SN_I1 (R)" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_MEM_DQ_SP_I1 (R)" }, { col => 1, table => 3, text => "15:12" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_N_VALUE_R_BACK (R)" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_P_VALUE_R_BACK (R)" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "IMP_CAL_COUNT (R)" }, { col => 1, table => 3, text => "27:24" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 17, text => [ { col => 0, table => 0, text => "TEST_OUT_R_BACK (R)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DUMMY_OUT_R_BACK (R)" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL - RW - 32 bits - [GpuF0MMReg:0x2700]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VREFI_VCO_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTR" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTN" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "IMP_VREF_INTP" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D0_P - RW - 32 bits - [GpuF0MMReg:0x264C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " Delay to turn on receive enable.", }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, { col => undef, table => undef, text => "RCV_EXT" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " Extends receive enable signal to cover clock drift.", }, { col => undef, table => undef, text => " 0=DQS receive enable not extended ", }, { col => undef, table => undef, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => undef, table => undef, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => undef, table => undef, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => undef, table => undef, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => undef, table => undef, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => undef, table => undef, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => undef, table => undef, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => undef, table => undef, text => " 8=DQS receive enable always on ", }, { col => undef, table => undef, text => "RST_SEL" }, { col => undef, table => undef, text => "9:8" }, { col => undef, table => undef, text => "0x2" }, { col => undef, table => undef, text => " NPL FIFO pointer reset mode.", }, { col => undef, table => undef, text => " 0=Reset pointers off " }, { col => undef, table => undef, text => " 1=Reset pointers on " }, { col => undef, table => undef, text => " 2=Reset pointers before read ", }, { col => undef, table => undef, text => " 3=Reset pointers during refresh ", }, ], }, { num => 18, text => [ { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Disables NPL FIFO pointer reset after a read ", }, { col => 3, table => 0, text => "command for a certain period of time. This prevents ", }, { col => 3, table => 0, text => "the pointers (read and write) from resetting before ", }, { col => 3, table => 0, text => "the FIFO is read." }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Creates an extra strobe in the preamble of a burst. ", }, { col => 3, table => 0, text => "This is needed if DQS is default high and its falling ", }, { col => 3, table => 0, text => "edge is used as a trigger." }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Creates an extra strobe in the postamble of a burst. ", }, { col => 3, table => 0, text => "This is needed if DQS is default high and its rising ", }, { col => 3, table => 0, text => "edge is used as a trigger." }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Delay to read data out of a NPL FIFO. This is used ", }, { col => 3, table => 0, text => "to cover the NPL FIFO's write to read latency.", }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => undef, table => undef, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => " Channel 0's read command parameters in hclk.", }, { col => "heading", table => 1, text => "MC_SEQ_RD_CTL_D1_P - RW - 32 bits - [GpuF0MMReg:0x2650]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, ], }, { num => 19, text => [ { col => 0, table => 0, text => "RCV_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 0, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 0, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 0, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 0, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 0, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 0, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 0, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => undef, table => undef, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => " Channel 1's read command parameters in hclk. See MC_SEQ_RD_CTL_I0.", }, ], }, { num => 20, text => [ { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D0_P - RW - 32 bits - [GpuF0MMReg:0x2654]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to data output latency.", }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to DQS latency.", }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Controls write preamble." }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => " Write command to output enable latency.", }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " Extends output enable after data burst.", }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Write command to on-die-termination enable ", }, { col => 3, table => 0, text => "latency." }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Extends on-die-termination enable after data burst.", }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => undef, table => undef, text => " Channel 0's write command parameters in hclk.", }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_P - RW - 32 bits - [GpuF0MMReg:0x2658]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => undef, table => undef, text => " Channel 1's write command parameters in hclk. See MC_SEQ_WR_CTL_I1.", }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D0_B - RW - 32 bits - [GpuF0MMReg:0x2694]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 21, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_B - RW - 32 bits - [GpuF0MMReg:0x2698]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 22, text => [ { col => 0, table => 0, text => "RCV_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 0, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 0, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 0, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 0, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 0, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 0, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 0, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, ], }, { num => 23, text => [ { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D0_B - RW - 32 bits - [GpuF0MMReg:0x269C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_B - RW - 32 bits - [GpuF0MMReg:0x26A0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => 3, table => 1, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 2, text => "MC_SEQ_RD_CTL_D0_S - RW - 32 bits - [GpuF0MMReg:0x26A4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RCV_DLY" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 2, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 2, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 2, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 2, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 2, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 2, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 2, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 2, text => "RCV_EXT" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=DQS receive enable not extended " }, { col => 3, table => 2, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 2, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 2, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 2, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 2, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 2, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 2, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 2, text => " 8=DQS receive enable always on " }, ], }, { num => 24, text => [ { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_S - RW - 32 bits - [GpuF0MMReg:0x26A8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 25, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D0_S - RW - 32 bits - [GpuF0MMReg:0x26AC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, ], }, { num => 26, text => [ { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_WR_CTL_D1_S - RW - 32 bits - [GpuF0MMReg:0x26B0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAT_DLY" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_DLY" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "DQS_XTR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No write preamble " }, { col => 3, table => 1, text => " 1=Write preamble " }, { col => 0, table => 1, text => "OEN_DLY" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "OEN_EXT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=output enable not extended " }, { col => 3, table => 1, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 1, text => "OEN_SEL" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x3" }, { col => 0, table => 1, text => "ODT_DLY" }, { col => 1, table => 1, text => "27:24" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "ODT_EXT" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=ODT not extended " }, { col => 3, table => 1, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 2, text => "MC_SEQ_RD_CTL_D0_C - RW - 32 bits - [GpuF0MMReg:0x26B4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RCV_DLY" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn on receive enable at CL-2 " }, { col => 3, table => 2, text => " 1=Turn on receive enable at CL-1 " }, { col => 3, table => 2, text => " 2=Turn on receive enable at CL " }, { col => 3, table => 2, text => " 3=Turn on receive enable at CL+1 " }, { col => 3, table => 2, text => " 4=Turn on receive enable at CL+2 " }, { col => 3, table => 2, text => " 5=Turn on receive enable at CL+3 " }, { col => 3, table => 2, text => " 6=Turn on receive enable at CL+4 " }, { col => 3, table => 2, text => " 7=Turn on receive enable at CL+5 " }, { col => 0, table => 2, text => "RCV_EXT" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=DQS receive enable not extended " }, { col => 3, table => 2, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 2, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 2, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 2, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 2, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 2, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 2, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 2, text => " 8=DQS receive enable always on " }, { col => 0, table => 2, text => "RST_SEL" }, { col => 1, table => 2, text => "9:8" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => " 0=Reset pointers off " }, { col => 3, table => 2, text => " 1=Reset pointers on " }, { col => 3, table => 2, text => " 2=Reset pointers before read " }, { col => 3, table => 2, text => " 3=Reset pointers during refresh " }, ], }, { num => 27, text => [ { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_RD_CTL_D1_C - RW - 32 bits - [GpuF0MMReg:0x26B8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "RCV_DLY" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Turn on receive enable at CL-2 ", }, { col => undef, table => undef, text => " 1=Turn on receive enable at CL-1 ", }, { col => undef, table => undef, text => " 2=Turn on receive enable at CL ", }, { col => undef, table => undef, text => " 3=Turn on receive enable at CL+1 ", }, { col => undef, table => undef, text => " 4=Turn on receive enable at CL+2 ", }, { col => undef, table => undef, text => " 5=Turn on receive enable at CL+3 ", }, { col => undef, table => undef, text => " 6=Turn on receive enable at CL+4 ", }, { col => undef, table => undef, text => " 7=Turn on receive enable at CL+5 ", }, ], }, { num => 28, text => [ { col => 0, table => 0, text => "RCV_EXT" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=DQS receive enable not extended " }, { col => 3, table => 0, text => " 1=DQS receive enable extended by 1 cycle ", }, { col => 3, table => 0, text => " 2=DQS receive enable extended by 2 cycles ", }, { col => 3, table => 0, text => " 3=DQS receive enable extended by 3 cycles ", }, { col => 3, table => 0, text => " 4=DQS receive enable extended by 4 cycles ", }, { col => 3, table => 0, text => " 5=DQS receive enable extended by 5 cycles ", }, { col => 3, table => 0, text => " 6=DQS receive enable extended by 6 cycles ", }, { col => 3, table => 0, text => " 7=DQS receive enable extended by 7 cycles ", }, { col => 3, table => 0, text => " 8=DQS receive enable always on " }, { col => 0, table => 0, text => "RST_SEL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 0=Reset pointers off " }, { col => 3, table => 0, text => " 1=Reset pointers on " }, { col => 3, table => 0, text => " 2=Reset pointers before read " }, { col => 3, table => 0, text => " 3=Reset pointers during refresh " }, { col => 0, table => 0, text => "RST_HLD" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable reset by 11 cycles " }, { col => 3, table => 0, text => " 1=Disable reset by 12 cycles " }, { col => 3, table => 0, text => " 2=Disable reset by 13 cycles " }, { col => 3, table => 0, text => " 3=Disable reset by 14 cycles " }, { col => 3, table => 0, text => " 4=Disable reset by 15 cycles " }, { col => 3, table => 0, text => " 5=Disable reset by 16 cycles " }, { col => 3, table => 0, text => " 6=Disable reset by 17 cycles " }, { col => 3, table => 0, text => " 7=Disable reset by 18 cycles " }, { col => 3, table => 0, text => " 8=Disable reset by 19 cycles " }, { col => 3, table => 0, text => " 9=Disable reset by 20 cycles " }, { col => 3, table => 0, text => " 10=Disable reset by 21 cycles " }, { col => 3, table => 0, text => " 11=Disable reset by 22 cycles " }, { col => 3, table => 0, text => " 12=Disable reset by 23 cycles " }, { col => 3, table => 0, text => " 13=Disable reset by 24 cycles " }, { col => 3, table => 0, text => " 14=Disable reset by 25 cycles " }, { col => 0, table => 0, text => "STR_PRE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read pre strobe " }, { col => 3, table => 0, text => " 1=Extra read pre strobe " }, { col => 0, table => 0, text => "STR_PST" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No read post strobe " }, { col => 3, table => 0, text => " 1=Extra read post strobe " }, { col => 0, table => 0, text => "RBS_DLY" }, { col => 1, table => 0, text => "24:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Assert RBS valid at CL+8 " }, { col => 3, table => 0, text => " 1=Assert RBS valid at CL+9 " }, { col => 3, table => 0, text => " 2=Assert RBS valid at CL+10 " }, { col => 3, table => 0, text => " 3=Assert RBS valid at CL+11 " }, { col => 3, table => 0, text => " 4=Assert RBS valid at CL+12 " }, { col => 3, table => 0, text => " 5=Assert RBS valid at CL+13 " }, { col => 3, table => 0, text => " 6=Assert RBS valid at CL+14 " }, { col => 3, table => 0, text => " 7=Assert RBS valid at CL+15 " }, { col => 3, table => 0, text => " 8=Assert RBS valid at CL+16 " }, { col => 3, table => 0, text => " 9=Assert RBS valid at CL+17 " }, { col => 3, table => 0, text => " 10=Assert RBS valid at CL+18 " }, { col => 3, table => 0, text => " 11=Assert RBS valid at CL+19 " }, { col => 3, table => 0, text => " 12=Assert RBS valid at CL+20 " }, { col => 3, table => 0, text => " 13=Assert RBS valid at CL+21 " }, { col => 3, table => 0, text => " 14=Assert RBS valid at CL+22 " }, { col => 3, table => 0, text => " 15=Assert RBS valid at CL+23 " }, { col => 3, table => 0, text => " 16=Assert RBS valid at CL+24 " }, { col => 3, table => 0, text => " 17=Assert RBS valid at CL+25 " }, { col => undef, table => undef, text => "MC_SEQ_WR_CTL_D0_C - RW - 32 bits - [GpuF0MMReg:0x26BC]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DAT_DLY" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "DQS_DLY" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "DQS_XTR" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=No write preamble " }, { col => undef, table => undef, text => " 1=Write preamble " }, ], }, { num => 29, text => [ { col => undef, table => undef, text => "OEN_DLY" }, { col => undef, table => undef, text => "15:12" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "OEN_EXT" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=output enable not extended ", }, { col => undef, table => undef, text => " 1=output eanble extended by one cycle ", }, { col => undef, table => undef, text => "OEN_SEL" }, { col => undef, table => undef, text => "21:20" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "ODT_DLY" }, { col => undef, table => undef, text => "27:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "ODT_EXT" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=ODT not extended " }, { col => undef, table => undef, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 0, text => "MC_SEQ_WR_CTL_D1_C - RW - 32 bits - [GpuF0MMReg:0x26C0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAT_DLY" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_DLY" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "DQS_XTR" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No write preamble " }, { col => 3, table => 0, text => " 1=Write preamble " }, { col => 0, table => 0, text => "OEN_DLY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "OEN_EXT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=output enable not extended " }, { col => 3, table => 0, text => " 1=output eanble extended by one cycle ", }, { col => 0, table => 0, text => "OEN_SEL" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x3" }, { col => 0, table => 0, text => "ODT_DLY" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ODT_EXT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=ODT not extended " }, { col => 3, table => 0, text => " 1=ODT extended by one cycle " }, { col => "heading", table => 1, text => "MC_SEQ_IO_CTL_D0 - RW - 32 bits - [GpuF0MMReg:0x265C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ADR_DLY" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Delays address output by half a hclk.", }, { col => 0, table => 1, text => "CMD_DLY" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Delays command output by half a hclk.", }, { col => 0, table => 1, text => "CKN_TRI" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off negative clock manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKP_TRI" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off positive clock manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "MIO_TRI" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Turns off address and command manually.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKE_BIT" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " Bypass value for clock enable.", }, { col => 0, table => 1, text => "CKE_SEL" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " Selects clock enable bypass value.", }, { col => 3, table => 1, text => " 0=Normal CKE " }, { col => 3, table => 1, text => " 1=Set CKE bit " }, { col => 0, table => 1, text => "STRD2" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " Channel 0's misc. control parameters.", }, { col => "heading", table => 2, text => "MC_SEQ_IO_CTL_D1 - RW - 32 bits - [GpuF0MMReg:0x2660]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ADR_DLY" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "CMD_DLY" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 30, text => [ { col => 0, table => 0, text => "CKN_TRI" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "CKP_TRI" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "MIO_TRI" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Tristate " }, { col => 0, table => 0, text => "CKE_BIT" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CKE_SEL" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Normal CKE " }, { col => 3, table => 0, text => " 1=Set CKE bit " }, { col => 0, table => 0, text => "STRD2" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " Channel 1's misc. control parameters. See MC_SEQ_IO_CTL_I0.", }, { col => "heading", table => 1, text => "MC_SEQ_IO_CTL_UNUSED - RW - 32 bits - [GpuF0MMReg:0x2898]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CKN_TRI" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "CKP_TRI" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "MIO_TRI" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "DAT_TRI" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Tristate " }, { col => 0, table => 1, text => "STRD2" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Turn off reserved figures " }, { col => undef, table => undef, text => " 1=Turn on reserved figures " }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "Unused channel misc. control parameters. This is intended for the second 64-bit IO. ", }, { col => "heading", table => 2, text => "MC_SEQ_NPL_CTL_D0 - RW - 32 bits - [GpuF0MMReg:0x2664]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LD_INIT" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " NPL FIFO's pointer offset." }, { col => 0, table => 2, text => "SYC_SEL" }, { col => 1, table => 2, text => "5:4" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " Selects mclk/yclk synchronization mode.", }, { col => 3, table => 2, text => " 0=mclk/yclk sync off " }, { col => 3, table => 2, text => " 1=mclk/yclk sync on " }, { col => 3, table => 2, text => " 2=mclk/yclk sync during refresh " }, { col => 3, table => 2, text => " 3=periodically turn on mclk/yclk sync ", }, { col => 0, table => 2, text => "SYC_IDLE_CNT" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " number of cycles a mclk/yclk sync will be ", }, { col => undef, table => undef, text => "forced " }, { col => undef, table => undef, text => " Channel 0's NPL control parameters.", }, { col => undef, table => undef, text => "MC_SEQ_NPL_CTL_D1 - RW - 32 bits - [GpuF0MMReg:0x2668]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "LD_INIT" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SYC_SEL" }, { col => undef, table => undef, text => "5:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " Selects mclk/yclk synchronization mode. The value ", }, { col => undef, table => undef, text => "should be same as MC_SEQ_NPL_CTL_D0 for 32bit mode", }, { col => undef, table => undef, text => " 0=mclk/yclk sync off " }, { col => undef, table => undef, text => " 1=mclk/yclk sync on " }, { col => undef, table => undef, text => " 2=mclk/yclk sync during refresh ", }, { col => undef, table => undef, text => " 3=periodically turn on mclk/yclk sync ", }, ], }, { num => 31, text => [ { col => 0, table => 0, text => "SYC_IDLE_CNT" }, { col => 1, table => 0, text => "31:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " " }, { col => 3, table => 0, text => "number of cycles a mclk/yclk sync will be ", }, { col => 3, table => 0, text => "forced. The value should be same as " }, { col => undef, table => undef, text => "MC_SEQ_NPL_CTL_D0 for 32bit mode ", }, { col => undef, table => undef, text => " Channel 1's NPL control parameters. See MC_SEQ_NPL_CTL_I0.", }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D0 - RW - 32 bits - [GpuF0MMReg:0x27F0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_MASTER_SYNC" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "For 32bit mode, this value should be same as ", }, { col => 3, table => 1, text => "MC_IO_PAD_CNTL_D1" }, { col => 0, table => 1, text => "DIFF_STR" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe single ended " }, { col => 3, table => 1, text => " 1=Strobe differential " }, { col => 0, table => 1, text => "UNI_STR" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Bidirectional strobes " }, { col => undef, table => undef, text => " 1=Unidirectional strobes " }, { col => undef, table => undef, text => "General Pad control" }, { col => "heading", table => 2, text => "MC_IO_PAD_CNTL_D1 - RW - 32 bits - [GpuF0MMReg:0x27F4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DELAY_MASTER_SYNC" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DIFF_STR" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Strobe single ended " }, { col => 3, table => 2, text => " 1=Strobe differential " }, { col => 0, table => 2, text => "UNI_STR" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Bidirectional strobes " }, { col => 3, table => 2, text => " 1=Unidirectional strobes " }, { col => "heading", table => 3, text => "MC_SEQ_CK_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x266C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_SEQ_CK_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2670]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "NMOS_PD" }, { col => 1, table => 4, text => "1:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "PSTR_OFF_H" }, { col => 1, table => 4, text => "7:4" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "NSTR_OFF_H" }, { col => 1, table => 4, text => "11:8" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "USE_CAL_STR" }, { col => 1, table => 4, text => 12 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Ignore cal ctl str " }, { col => 3, table => 4, text => " 1=Use cal ctl str " }, { col => 0, table => 4, text => "LOAD_STR" }, { col => 1, table => 4, text => 13 }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 32, text => [ { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_CMD_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2674]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_CMD_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2678]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_DQ_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x267C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_DQ_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2680]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "NMOS_PD" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PSTR_OFF_H" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NSTR_OFF_H" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 33, text => [ { col => 0, table => 0, text => "USE_CAL_STR" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Ignore cal ctl str " }, { col => 3, table => 0, text => " 1=Use cal ctl str " }, { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_QS_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2684]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_QS_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2688]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_A_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x268C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "MC_SEQ_A_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2690]", }, ], }, { num => 34, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "NMOS_PD" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_H" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_H" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "USE_CAL_STR" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Ignore cal ctl str " }, { col => 3, table => 0, text => " 1=Use cal ctl str " }, { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2704]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_DATA_SYNC" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay data sync " }, { col => 3, table => 1, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_STR_SYNC" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay strobe sync " }, { col => 3, table => 1, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CLK_SYNC" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay clk sync " }, { col => 3, table => 1, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CMD_SYNC" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay cmd sync " }, { col => 3, table => 1, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_ADR_SYNC" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay adr sync " }, { col => 3, table => 1, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 1, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Data out on YCLK rise " }, { col => 3, table => 1, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 1, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 1, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Command out on YCLK rise " }, { col => 3, table => 1, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Address out on YCLK rise " }, { col => 3, table => 1, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "FORCE_EN_RD_STR" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Read strb enabled by MC " }, { col => 3, table => 1, text => " 1=Always enable read strb " }, { col => 0, table => 1, text => "EN_RD_STR_DLY" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=count rising edge " }, { col => 3, table => 1, text => " 1=count falling edge " }, { col => 0, table => 1, text => "DISABLE_CMD" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Drive command " }, { col => 3, table => 1, text => " 1=Disable command " }, { col => 0, table => 1, text => "DISABLE_ADR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Drive address " }, { col => 3, table => 1, text => " 1=Disable address " }, { col => 0, table => 1, text => "VREFI_EN" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VREFI disable " }, { col => 3, table => 1, text => " 1=VREFI enable " }, { col => 0, table => 1, text => "VREFI_SEL" }, { col => 1, table => 1, text => "19:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "CK_AUTO_EN" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No CK duty cycle correction " }, { col => 3, table => 1, text => " 1=Correct CK duty cycle " }, { col => 0, table => 1, text => "CK_DELAY_SEL" }, { col => 1, table => 1, text => 21 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Use register value " }, { col => 3, table => 1, text => " 1=Use auto cal value " }, { col => 0, table => 1, text => "CK_DELAY_N" }, { col => 1, table => 1, text => "23:22" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "CK_DELAY_P" }, { col => 1, table => 1, text => "25:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2708]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 35, text => [ { col => 0, table => 0, text => "DELAY_DATA_SYNC" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay data sync " }, { col => 3, table => 0, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_STR_SYNC" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay strobe sync " }, { col => 3, table => 0, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CLK_SYNC" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay clk sync " }, { col => 3, table => 0, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CMD_SYNC" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay cmd sync " }, { col => 3, table => 0, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_ADR_SYNC" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay adr sync " }, { col => 3, table => 0, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 0, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Data out on YCLK rise " }, { col => 3, table => 0, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 0, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 0, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Command out on YCLK rise " }, { col => 3, table => 0, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_DQ_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2710]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MADJ0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_DQ_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2714]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MADJ0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 36, text => [ { col => "heading", table => 0, text => "MC_IO_RD_QS_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2718]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DLY0" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY1" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY2" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_QS_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x271C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_QS2_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2720]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_QS2_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2724]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "31:24" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_WR_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2728]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CK_DLY" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "CMD_DLY" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "ADR_DLY" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 37, text => [ { col => "heading", table => 0, text => "MC_IO_WR_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x272C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CK_DLY" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CMD_DLY" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "ADR_DLY" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_CK_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2730]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INTR" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_CK_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2734]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INTR" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_CMD_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2738]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "PTERM" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NTERM" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PDRV" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "NDRV" }, { col => undef, table => undef, text => "15:12" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "RECV_DUTY" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 38, text => [ { col => undef, table => undef, text => "DRV_DUTY" }, { col => undef, table => undef, text => "19:18" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PREAMP" }, { col => undef, table => undef, text => "21:20" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SELFTIME" }, { col => undef, table => undef, text => 22 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SLEW" }, { col => undef, table => undef, text => "24:23" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "VMODE" }, { col => undef, table => undef, text => 25 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "VREF_INT" }, { col => undef, table => undef, text => "27:26" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 0, text => "MC_IO_CMD_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x273C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_DQ_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2740]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_DQ_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2744]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 39, text => [ { col => "heading", table => 0, text => "MC_IO_QS_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2748]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_QS_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x274C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PTERM" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NTERM" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PDRV" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NDRV" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_A_PAD_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2750]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VREF_INT" }, { col => 1, table => 2, text => "27:26" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 40, text => [ { col => "heading", table => 0, text => "MC_IO_A_PAD_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2754]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PTERM" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NTERM" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PDRV" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NDRV" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "RECV_DUTY" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DRV_DUTY" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PREAMP" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELFTIME" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SLEW" }, { col => 1, table => 0, text => "24:23" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VMODE" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_WR_DQ_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2758]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_WR_DQ_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x275C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DLY0" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY1" }, { col => undef, table => undef, text => "5:3" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY2" }, { col => undef, table => undef, text => "8:6" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DLY3" }, { col => undef, table => undef, text => "11:9" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_WR_QS_CNTL_D0_I0 - RW - 32 bits - [GpuF0MMReg:0x2760]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_QS_CNTL_D0_I1 - RW - 32 bits - [GpuF0MMReg:0x2764]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 41, text => [ { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B0_D0 - RW - 32 bits - [GpuF0MMReg:0x26E8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit0 select" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit1 select" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit2 select" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit3 select" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit4 select" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit5 select" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit6 select" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit7 select" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte0", }, { col => "heading", table => 2, text => "MC_IO_RD_STR_NCNTL_B1_D0 - RW - 32 bits - [GpuF0MMReg:0x280C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEL0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit0 select" }, { col => 0, table => 2, text => "SEL1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit1 select" }, { col => 0, table => 2, text => "SEL2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit2 select" }, { col => 0, table => 2, text => "SEL3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit3 select" }, { col => 0, table => 2, text => "SEL4" }, { col => 1, table => 2, text => "14:12" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit4 select" }, { col => 0, table => 2, text => "SEL5" }, { col => 1, table => 2, text => "17:15" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit5 select" }, { col => 0, table => 2, text => "SEL6" }, { col => 1, table => 2, text => "20:18" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit6 select" }, { col => 0, table => 2, text => "SEL7" }, { col => 1, table => 2, text => "23:21" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit7 select" }, { col => 0, table => 2, text => "SELM" }, { col => 1, table => 2, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte1", }, { col => "heading", table => 3, text => "MC_IO_RD_STR_NCNTL_B2_D0 - RW - 32 bits - [GpuF0MMReg:0x26F8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SEL0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit0 select" }, { col => 0, table => 3, text => "SEL1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit1 select" }, { col => 0, table => 3, text => "SEL2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit2 select" }, { col => 0, table => 3, text => "SEL3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit3 select" }, { col => 0, table => 3, text => "SEL4" }, { col => 1, table => 3, text => "14:12" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit4 select" }, { col => 0, table => 3, text => "SEL5" }, { col => 1, table => 3, text => "17:15" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit5 select" }, { col => 0, table => 3, text => "SEL6" }, { col => 1, table => 3, text => "20:18" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit6 select" }, { col => 0, table => 3, text => "SEL7" }, { col => 1, table => 3, text => "23:21" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit7 select" }, { col => 0, table => 3, text => "SELM" }, { col => 1, table => 3, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Falling Edge Strobe Select For Read Data Byte2", }, { col => undef, table => undef, text => "MC_IO_RD_STR_NCNTL_B3_D0 - RW - 32 bits - [GpuF0MMReg:0x27F8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "SEL0" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Bit0 select" }, ], }, { num => 42, text => [ { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, 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=> 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_QS_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2780]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, ], }, { num => 45, text => [ { col => 0, table => 0, text => "LOAD_STR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "PSTR_OFF_V" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "NSTR_OFF_V" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_SEQ_QS_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x2784]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "NMOS_PD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_H" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_H" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "USE_CAL_STR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Ignore cal ctl str " }, { col => 3, table => 1, text => " 1=Use cal ctl str " }, { col => 0, table => 1, text => "LOAD_STR" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSTR_OFF_V" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "NSTR_OFF_V" }, { col => 1, table => 1, text => "23:20" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_A_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2788]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "NMOS_PD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_H" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_H" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "USE_CAL_STR" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore cal ctl str " }, { col => 3, table => 2, text => " 1=Use cal ctl str " }, { col => 0, table => 2, text => "LOAD_STR" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSTR_OFF_V" }, { col => 1, table => 2, text => "19:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NSTR_OFF_V" }, { col => 1, table => 2, text => "23:20" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_SEQ_A_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x278C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NMOS_PD" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_H" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_H" }, { col => 1, table => 3, text => "11:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "USE_CAL_STR" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Ignore cal ctl str " }, { col => 3, table => 3, text => " 1=Use cal ctl str " }, { col => 0, table => 3, text => "LOAD_STR" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PSTR_OFF_V" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "NSTR_OFF_V" }, { col => 1, table => 3, text => "23:20" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_PAD_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2790]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 46, text => [ { col => 0, table => 0, text => "DELAY_DATA_SYNC" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay data sync " }, { col => 3, table => 0, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_STR_SYNC" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay strobe sync " }, { col => 3, table => 0, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CLK_SYNC" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay clk sync " }, { col => 3, table => 0, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_CMD_SYNC" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay cmd sync " }, { col => 3, table => 0, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 0, text => "DELAY_ADR_SYNC" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Don't delay adr sync " }, { col => 3, table => 0, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 0, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Data out on YCLK rise " }, { col => 3, table => 0, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 0, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 0, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Command out on YCLK rise " }, { col => 3, table => 0, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x2794]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DELAY_DATA_SYNC" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay data sync " }, { col => 3, table => 1, text => " 1=delay data sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_STR_SYNC" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay strobe sync " }, { col => 3, table => 1, text => " 1=delay strobe sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CLK_SYNC" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay clk sync " }, { col => 3, table => 1, text => " 1=delay clk sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_CMD_SYNC" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay cmd sync " }, { col => 3, table => 1, text => " 1=delay cmd sync by 1 yclk " }, { col => 0, table => 1, text => "DELAY_ADR_SYNC" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Don't delay adr sync " }, { col => 3, table => 1, text => " 1=delay adr sync by 1 yclk " }, { col => 0, table => 1, text => "MEM_FALL_OUT_DATA" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Data out on YCLK rise " }, { col => 3, table => 1, text => " 1=Data out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_STR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Strobe out on YCLK rise " }, { col => 3, table => 1, text => " 1=Strobe out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CLK" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Clk out on YCLK rise " }, { col => 3, table => 1, text => " 1=Clk out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 1, text => "MEM_FALL_OUT_CMD" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Command out on YCLK rise " }, { col => 3, table => 1, text => " 1=Command out on YCLK fall, 1/4 clock delay ", }, ], }, { num => 47, text => [ { col => 0, table => 0, text => "MEM_FALL_OUT_ADR" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Address out on YCLK rise " }, { col => 3, table => 0, text => " 1=Address out on YCLK fall, 1/4 clock delay ", }, { col => 0, table => 0, text => "FORCE_EN_RD_STR" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Read strb enabled by MC " }, { col => 3, table => 0, text => " 1=Always enable read strb " }, { col => 0, table => 0, text => "EN_RD_STR_DLY" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=count rising edge " }, { col => 3, table => 0, text => " 1=count falling edge " }, { col => 0, table => 0, text => "DISABLE_CMD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive command " }, { col => 3, table => 0, text => " 1=Disable command " }, { col => 0, table => 0, text => "DISABLE_ADR" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Drive address " }, { col => 3, table => 0, text => " 1=Disable address " }, { col => 0, table => 0, text => "VREFI_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=VREFI disable " }, { col => 3, table => 0, text => " 1=VREFI enable " }, { col => 0, table => 0, text => "VREFI_SEL" }, { col => 1, table => 0, text => "19:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_AUTO_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No CK duty cycle correction " }, { col => 3, table => 0, text => " 1=Correct CK duty cycle " }, { col => 0, table => 0, text => "CK_DELAY_SEL" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use register value " }, { col => 3, table => 0, text => " 1=Use auto cal value " }, { col => 0, table => 0, text => "CK_DELAY_N" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CK_DELAY_P" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_DQ_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x2798]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MADJ0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "MADJ3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_DQ_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x279C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MADJ0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "MADJ3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_QS_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27A0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "31:24" }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 48, text => [ { col => "heading", table => 0, text => "MC_IO_RD_QS_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DLY0" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY1" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY2" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DLY3" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_QS2_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27A8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_QS2_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27AC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27B0]", }, { col => 0, table => 3, text => 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text => "RECV_DUTY" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DRV_DUTY" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PREAMP" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELFTIME" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SLEW" }, { col => 1, table => 1, text => "24:23" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VMODE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "VREF_INT" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_A_PAD_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27DC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PTERM" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NTERM" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PDRV" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "NDRV" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RECV_DUTY" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DRV_DUTY" }, { col => 1, table => 2, text => "19:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PREAMP" }, { col => 1, table => 2, text => "21:20" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELFTIME" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SLEW" }, { col => 1, table => 2, text => "24:23" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VMODE" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 52, text => [ { col => 0, table => 0, text => "VREF_INT" }, { col => 1, table => 0, text => "27:26" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_WR_DQ_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27E0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLY0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DLY3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_WR_DQ_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27E4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLY0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DLY3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_WR_QS_CNTL_D1_I0 - RW - 32 bits - [GpuF0MMReg:0x27E8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DLY0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DLY3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_WR_QS_CNTL_D1_I1 - RW - 32 bits - [GpuF0MMReg:0x27EC]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DLY0" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY1" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY2" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DLY3" }, { col => 1, table => 4, text => "11:9" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "MC_IO_RD_STR_NCNTL_B0_D1 - RW - 32 bits - [GpuF0MMReg:0x2820]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "SEL0" }, { col => 1, table => 5, text => "2:0" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL1" }, { col => 1, table => 5, text => "5:3" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL2" }, { col => 1, table => 5, text => "8:6" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL3" }, { col => 1, table => 5, text => "11:9" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL4" }, { col => 1, table => 5, text => "14:12" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL5" }, { col => 1, table => 5, text => "17:15" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL6" }, { col => 1, table => 5, text => "20:18" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SEL7" }, { col => 1, table => 5, text => "23:21" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "SELM" }, { col => 1, table => 5, text => "26:24" }, { col => 2, table => 5, text => "0x0" }, { col => undef, table => undef, text => "MC_IO_RD_STR_NCNTL_B1_D1 - RW - 32 bits - [GpuF0MMReg:0x2828]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 53, text => [ { col => 0, table => 0, text => "SEL0" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL2" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL4" }, { col => 1, table => 0, text => "14:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL5" }, { col => 1, table => 0, text => "17:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL6" }, { col => 1, table => 0, text => "20:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL7" }, { col => 1, table => 0, text => "23:21" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELM" }, { col => 1, table => 0, text => "26:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B2_D1 - RW - 32 bits - [GpuF0MMReg:0x2830]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_IO_RD_STR_NCNTL_B3_D1 - RW - 32 bits - [GpuF0MMReg:0x2838]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEL0" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL1" }, { col => 1, table => 2, text => "5:3" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL2" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL3" }, { col => 1, table => 2, text => "11:9" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL4" }, { col => 1, table => 2, text => "14:12" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL5" }, { col => 1, table => 2, text => "17:15" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL6" }, { col => 1, table => 2, text => "20:18" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SEL7" }, { col => 1, table => 2, text => "23:21" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "SELM" }, { col => 1, table => 2, text => "26:24" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "MC_IO_RD_STR_NCNTL_B4_D1 - RW - 32 bits - [GpuF0MMReg:0x2840]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SEL0" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL1" }, { col => 1, table => 3, text => "5:3" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL2" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL3" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL4" }, { col => 1, table => 3, text => "14:12" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL5" }, { col => 1, table => 3, text => "17:15" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL6" }, { col => 1, table => 3, text => "20:18" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SEL7" }, { col => 1, table => 3, text => "23:21" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SELM" }, { col => 1, table => 3, text => "26:24" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "MC_IO_RD_STR_NCNTL_B5_D1 - RW - 32 bits - [GpuF0MMReg:0x2848]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "SEL0" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "SEL1" }, { col => 1, table => 4, text => "5:3" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "SEL2" }, { col => 1, table => 4, text => "8:6" }, { col => 2, table => 4, text => "0x0" }, ], }, { num => 54, text => [ { col => undef, table => undef, text => "SEL3" }, { col => undef, table => undef, text => "11:9" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL4" }, { col => undef, table => undef, text => "14:12" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL5" }, { col => undef, table => undef, text => "17:15" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL6" }, { col => undef, table => undef, text => "20:18" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SEL7" }, { col => undef, table => undef, text => "23:21" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "SELM" }, { col => undef, table => undef, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => "heading", table => 0, text => "MC_IO_RD_STR_NCNTL_B6_D1 - RW - 32 bits - [GpuF0MMReg:0x2850]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "SEL0" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL1" }, { col => 1, table => 0, text => "5:3" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL2" }, { col => 1, table => 0, text => "8:6" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL3" }, { col => 1, table => 0, text => "11:9" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL4" }, { col => 1, table => 0, text => "14:12" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL5" }, { col => 1, table => 0, text => "17:15" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL6" }, { col => 1, table => 0, text => "20:18" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SEL7" }, { col => 1, table => 0, text => "23:21" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "SELM" }, { col => 1, table => 0, text => "26:24" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "MC_IO_RD_STR_NCNTL_B7_D1 - RW - 32 bits - [GpuF0MMReg:0x2858]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEL0" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL1" }, { col => 1, table => 1, text => "5:3" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL2" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL3" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL4" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL5" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL6" }, { col => 1, table => 1, text => "20:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SEL7" }, { col => 1, table => 1, text => "23:21" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SELM" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "MC_SEQ_GENERAL_CONFIG - RW - 32 bits - [GpuF0MMReg:0x26D8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MODE_32BIT" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=64-bit channel mode " }, { col => 3, table => 2, text => " 1=32-bit channel mode " }, { col => 0, table => 2, text => "DUAL_IO" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Single IO configuration " }, { col => 3, table => 2, text => " 1=Dual IO configuration " }, { col => 0, table => 2, text => "MODE_16BIT" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => " 1=16-bit channel mode " }, { col => undef, table => undef, text => "General SEQ configuration" }, { col => "heading", table => 3, text => "MC_SEQ_RS_CNTL - RW - 32 bits - [GpuF0MMReg:0x26DC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RRDREQ_LCL_CREDIT" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x4" }, { col => 0, table => 3, text => "XBF_HWM" }, { col => 1, table => 3, text => "9:4" }, { col => 2, table => 3, text => "0x12" }, { col => 3, table => 3, text => "High water mark for mclk to sclk async FIFO, for 64bit BO4, ", }, { col => 3, table => 3, text => "the water mark should be increased" }, { col => 0, table => 3, text => "DAT_INV" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Disable read data inversion " }, { col => 3, table => 3, text => " 1=Enable read data inversion " }, { col => 0, table => 3, text => "MSK_DFI" }, { col => 1, table => 3, text => 13 }, { col => 2, table => 3, text => "0x1" }, { col => 3, table => 3, text => " 0=Inverse mask active low " }, { col => 3, table => 3, text => " 1=Inverse mask active high " }, ], }, { num => 55, text => [ { col => undef, table => undef, text => "RRDREQ_RETURN_PEND" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Return the read data to RS whenever the data is ready ", }, { col => undef, table => undef, text => " 1=Return the read data to RS after all the data for that ", }, { col => undef, table => undef, text => "burst has been received " }, { col => undef, table => undef, text => " 2=Return the read data to RS when the data is ready and ", }, { col => undef, table => undef, text => "the last read for that burst has been sent out to the memory ", }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "RRDREQ_RS_CREDIT" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x8" }, { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "SEQ to RS control register " }, { col => "heading", table => 0, text => "MC_SEQ_STATUS_M - RW - 32 bits - [GpuF0MMReg:0x26C8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PWRUP_COMPL_D0 (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 SDRAM init in progress " }, { col => 3, table => 0, text => " 1=CHAN_D0 SDRAM ready " }, { col => 0, table => 0, text => "PWRUP_COMPL_D1 (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 SDRAM init in progress " }, { col => 3, table => 0, text => " 1=CHAN_D1 SDRAM ready " }, { col => 0, table => 0, text => "CMD_RDY_D0 (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 Command register busy " }, { col => 3, table => 0, text => " 1=CHAN_D0 Command register ready " }, { col => 0, table => 0, text => "CMD_RDY_D1 (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 Command register busy " }, { col => 3, table => 0, text => " 1=CHAN_D1 Command register ready " }, { col => 0, table => 0, text => "SLF_D0 (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D0 Not in Self Refresh mode " }, { col => 3, table => 0, text => " 1=CHAN_D0 In Self Refresh mode " }, { col => 0, table => 0, text => "SLF_D1 (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=CHAN_D1 Not in Self Refresh mode " }, { col => 3, table => 0, text => " 1=CHAN_D1 In Self Refresh mode " }, { col => 0, table => 0, text => "SEQ00_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ00 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ01_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ01 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ10_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ10 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ11_ARB_CMD_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 arb interface cmd fifo not empty ", }, { col => 3, table => 0, text => " 1=SEQ11 arb interface cmd fifo empty ", }, { col => 0, table => 0, text => "SEQ00_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ00 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ01_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ01 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ10_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ10 rs interface data fifo full " }, { col => 0, table => 0, text => "SEQ11_RS_DATA_FIFO_FULL (R)" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 rs interface data fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ11 rs interface data fifo full " }, { col => "heading", table => 1, text => "MC_SEQ_STATUS_S - RW - 32 bits - [GpuF0MMReg:0x288C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEQ00_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ00 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ00 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ01_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ01 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ01 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ10_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ10 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ10 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ11_ARB_DATA_FIFO_FULL (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ11 arb interface data fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ11 arb interface data fifo full ", }, { col => 0, table => 1, text => "SEQ00_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ00 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ00 arb interface cmd fifo full " }, { col => 0, table => 1, text => "SEQ01_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ01 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ01 arb interface cmd fifo full " }, { col => 0, table => 1, text => "SEQ10_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SEQ10 arb interface cmd fifo not full ", }, { col => 3, table => 1, text => " 1=SEQ10 arb interface cmd fifo full " }, ], }, { num => 56, text => [ { col => 0, table => 0, text => "SEQ11_ARB_CMD_FIFO_FULL (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 arb interface cmd fifo not full ", }, { col => 3, table => 0, text => " 1=SEQ11 arb interface cmd fifo full " }, { col => 0, table => 0, text => "SEQ00_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ00 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ00 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ01_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ01 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ01 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ10_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ10 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ10 rs interface data fifo EMPTY ", }, { col => 0, table => 0, text => "SEQ11_RS_DATA_FIFO_EMPTY (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=SEQ11 rs interface data fifo not EMPTY ", }, { col => 3, table => 0, text => " 1=SEQ11 rs interface data fifo EMPTY ", }, { col => "heading", table => 1, text => "MC_NPL_STATUS - RW - 32 bits - [GpuF0MMReg:0x2888]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D0_I0_PDELAY (R)" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_NDELAY (R)" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_PEARLY (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I0_NEARLY (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_PDELAY (R)" }, { col => 1, table => 1, text => "7:6" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_NDELAY (R)" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_PEARLY (R)" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D0_I1_NEARLY (R)" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_PDELAY (R)" }, { col => 1, table => 1, text => "13:12" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_NDELAY (R)" }, { col => 1, table => 1, text => "15:14" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_PEARLY (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I0_NEARLY (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_PDELAY (R)" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_NDELAY (R)" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_PEARLY (R)" }, { col => 1, table => 1, text => 22 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "D1_I1_NEARLY (R)" }, { col => 1, table => 1, text => 23 }, { col => 2, table => 1, text => "0x0" }, ], }, { num => 57, text => [ { col => undef, table => undef, text => "2.2" }, { col => undef, table => undef, text => "Bus Interface Registers" }, { col => "heading", table => 0, text => "MM_INDEX - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MM_OFFSET" }, { col => 1, table => 0, text => "30:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field specifies the offset (in MM space) of the register ", }, { col => 3, table => 0, text => "or the offset in FB memory to be accessed. ", }, { col => 3, table => 0, text => "All accesses must be dword aligned, therefore, ", }, { col => 3, table => 0, text => "bits 1:0 are tied to zero." }, { col => 3, table => 0, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "MM_APER" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit specifies whether the address offset is for Register ", }, { col => 3, table => 0, text => "aperture or FB aperture (Linear Aperture).", }, { col => 3, table => 0, text => " 0=Register Aperture " }, { col => undef, table => undef, text => " 1=Linear Aperture 0 " }, { col => undef, table => undef, text => "General Memory Access. The MM_INDEX and MM_DATA pair of registers are used to indirectly accessed ", }, { col => undef, table => undef, text => "all other memory mapped registers in the lower 64KB space and the Frame buffer.", }, { col => "heading", table => 1, text => "MM_DATA - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MM_DATA" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field contains the data to be written to or the data read ", }, { col => undef, table => undef, text => "from the address specified in MM_INDEX.", }, { col => undef, table => undef, text => "General Memory Access. The MM_INDEX and MM_DATA pair of registers are used to indirectly access ", }, { col => undef, table => undef, text => "all other BIF memory mapped registers and the frame buffer.", }, { col => "heading", table => 2, text => "BUS_CNTL - RW - 32 bits - [GpuF0MMReg:0x5420]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "BIOS_ROM_WRT_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Unused" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "BIOS_ROM_DIS" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Unused" }, { col => 3, table => 2, text => " 0=Enable " }, { col => 3, table => 2, text => " 1=Disable " }, { col => 0, table => 2, text => "PMI_IO_DIS" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 2, text => "program the power state. If the power ", }, { col => 3, table => 2, text => "state is D1-D3, then IO access is disabled. If this bit is set ", }, { col => 3, table => 2, text => "to 1, it will enable IO access.", }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Disable " }, { col => 0, table => 2, text => "PMI_MEM_DIS" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 2, text => "program the power state. If the power ", }, { col => 3, table => 2, text => "state is D1-D3, then MEM access is disabled. If this bit is ", }, { col => 3, table => 2, text => "set to 1, it will enable MEM access.", }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Disable " }, ], }, { num => 58, text => [ { col => 0, table => 0, text => "PMI_BM_DIS" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 0, text => "program the power state. If the power ", }, { col => 3, table => 0, text => "state is D1-D3, then bus mastering is disabled. If this bit is ", }, { col => 3, table => 0, text => "set to 1, it will enable bus mastering.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "PMI_INT_DIS" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The PMI_STATUS_CNTL.POWER_STATE is used to ", }, { col => 3, table => 0, text => "program the power state. If the power ", }, { col => 3, table => 0, text => "state is D1-D3, then INTx messages are disabled. If this bit ", }, { col => 3, table => 0, text => "is set to 1, it will enable sending INTx ", }, { col => 3, table => 0, text => "messages." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "VGA_REG_COHERENCY_DIS" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable VGA register coherency." }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "VGA_MEM_COHERENCY_DIS" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable VGA memory coherency." }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "BIF_ERR_RTR_BKPRESSURE_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Wrapper backpressure RTR to Gijoe3 when a ", }, { col => 3, table => 0, text => "previous error is pending. When Gijoe3 ", }, { col => 3, table => 0, text => "signals error is done, Wrapper will assert RTR to accept the ", }, { col => 3, table => 0, text => "next request" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "VGA_COHE_SPEC_TIMER_DIS" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "ALLOW_TC_TO_PCIE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Allow the traffic class bit from clients to propagate to PCIE ", }, { col => 3, table => 0, text => "core. If not, it will be tied to 0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "PCI Express Bus Control Register", }, { col => "heading", table => 1, text => "CONFIG_CNTL - RW - 32 bits - [GpuF0MMReg:0x5424]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CFG_VGA_RAM_EN (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA RAM enable" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "VGA_DIS" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA Disable. Unused." }, { col => 0, table => 1, text => "GENMO_MONO_ADDRESS_B (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Monochrome emulation or Colour emulation", }, { col => 3, table => 1, text => " 0=Monochrome emulation, regs at 0x3Bx ", }, { col => 3, table => 1, text => " 1=Color/Graphic emulation, regs at 0x3Dx ", }, { col => 0, table => 1, text => "GRPH_ADRSEL (R)" }, { col => 1, table => 1, text => "4:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Graphics address and aperture size select", }, { col => 3, table => 1, text => " 0=A0000-128K " }, { col => 3, table => 1, text => " 1=A0000-64K " }, { col => 3, table => 1, text => " 2=B0000-32K " }, { col => undef, table => undef, text => " 3=B8000-32K " }, { col => undef, table => undef, text => "Configuration Control Register" }, { col => "heading", table => 2, text => "CONFIG_MEMSIZE - RW - 32 bits - [GpuF0MMReg:0x5428]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 59, text => [ { col => 0, table => 0, text => "CONFIG_MEMSIZE" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Configuration memory size" }, { col => undef, table => undef, text => "NOTE: Bits 0:19 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Scratch regsiter for BIOS to inform driver memory size", }, { col => "heading", table => 1, text => "CONFIG_F0_BASE - R - 32 bits - [GpuF0MMReg:0x542C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "F0_BASE" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "F0 Base Address" }, { col => undef, table => undef, text => "NOTE: Bits 0:24 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Configuration F0 Base Register" }, { col => "heading", table => 2, text => "CONFIG_APER_SIZE - R - 32 bits - [GpuF0MMReg:0x5430]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "APER_SIZE" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Strap-loadable register based on strap MEM_AP_SIZE", }, { col => undef, table => undef, text => "NOTE: Bits 0:23 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Function 0 Configuration Memory Aperture Size", }, { col => "heading", table => 3, text => "CONFIG_REG_APER_SIZE - R - 32 bits - [GpuF0MMReg:0x5434]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "REG_APER_SIZE" }, { col => 1, table => 3, text => "19:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Strap-loadable register based on strap REG_AP_SIZE", }, { col => undef, table => undef, text => "Function 0 Configuration Register Aperture Size", }, ], }, { num => 60, text => [ { col => undef, table => undef, text => "2.3" }, { col => undef, table => undef, text => "PCI-E Registers" }, { col => "heading", table => 0, text => "PCIE_INDEX - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x30]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PCIE_INDEX" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "index of bifdec" }, { col => undef, table => undef, text => "Index register for the PCI Express common indirect registers", }, { col => "heading", table => 1, text => "PCIE_DATA - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x34]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PCIE_DATA" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "data of bifdec" }, { col => undef, table => undef, text => "Data register for the PCI Express common indirect registers", }, { col => "heading", table => 2, text => "PCIE_RX_NUM_NACK - R - 32 bits - PCIEIND:0xE", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_NUM_NACK" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Total number of nacks received" }, { col => undef, table => undef, text => "Num nacks received" }, { col => "heading", table => 3, text => "PCIE_RX_NUM_NACK_GENERATED - R - 32 bits - PCIEIND:0xF", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RX_NUM_NACK_GENERATED" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Total number of nacks generated" }, { col => undef, table => undef, text => "Num nacks generated" }, { col => "heading", table => 4, text => "PCIE_CI_CNTL - RW - 32 bits - PCIEIND:0x20", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CI_BE_SPLIT_MODE" }, { col => 1, table => 4, text => "1:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Normal byte splitting rules for PCI-Express 1.0A ", }, { col => 3, table => 4, text => " 1=Force a split on QW boundary with maximum packet ", }, { col => 3, table => 4, text => "length = 2 " }, { col => 3, table => 4, text => " 2=Bypass mode that forces full byte enables ", }, { col => 0, table => 4, text => "CI_SLAVE_SPLIT_MODE" }, { col => 1, table => 4, text => 2 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Completions split on Channels" }, { col => 3, table => 4, text => " 0=RC - Full completions from Channel A or B ", }, { col => 3, table => 4, text => " 1=RC - Completions split on Channel A and B evenly ", }, { col => 0, table => 4, text => "CI_SLAVE_GEN_USR_DIS" }, { col => 1, table => 4, text => 3 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Sends USR for invalid addresses" }, { col => 3, table => 4, text => " 0=Sends USR for invalid addresses " }, { col => 3, table => 4, text => " 1=Disables slave from sending USR, and instead ", }, { col => 3, table => 4, text => "sends a successful CMPLT_D with dummy data. ", }, { col => 0, table => 4, text => "CI_MST_CMPL_DUMMY_DATA" }, { col => 1, table => 4, text => 4 }, { col => 2, table => 4, text => "0x1" }, { col => 3, table => 4, text => "0xDEADBEEF or 0xFFFFFFFF" }, { col => 3, table => 4, text => " 0=0xDEADBEEF " }, { col => 3, table => 4, text => " 1=0xFFFFFFFF " }, { col => 0, table => 4, text => "CI_MST_TAG_MODE" }, { col => 1, table => 4, text => 5 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "incremental tag or first available tag" }, { col => 3, table => 4, text => " 0=incremental tag " }, { col => 3, table => 4, text => " 1=first available tag " }, ], }, { num => 61, text => [ { col => 0, table => 0, text => "CI_SLV_RC_RD_REQ_SIZE" }, { col => 1, table => 0, text => "7:6" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Slave read requests supported size to client.", }, { col => 3, table => 0, text => " 0=32/64 byte requests supported " }, { col => 3, table => 0, text => " 1=64 byte requests only " }, { col => 3, table => 0, text => " 2=16/32/64 " }, { col => 0, table => 0, text => "CI_SLV_ORDERING_DIS" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable slave ordering logic" }, { col => 3, table => 0, text => " 0=Enable slave ordering logic " }, { col => 3, table => 0, text => " 1=Disable slave ordering logic " }, { col => 0, table => 0, text => "CI_RC_ORDERING_DIS" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable RC ordering logic" }, { col => 3, table => 0, text => " 0=Enable RC ordering logic " }, { col => 3, table => 0, text => " 1=Disable RC ordering logic " }, { col => 0, table => 0, text => "CI_SLV_CPL_ALLOC_DIS" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Slave CPL buffer is sub-divided or not" }, { col => 3, table => 0, text => " 0=Slave CPL buffer is sub-divided between ports based ", }, { col => 3, table => 0, text => "on number of lanes active " }, { col => 3, table => 0, text => " 1=Slave CPL buffer is not sub-divided ", }, { col => 0, table => 0, text => "CI_SLV_CPL_ALLOC_MODE (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0Slave Cpl buffer method for sub-division. 0 - dynamic, 1 - ", }, { col => undef, table => undef, text => "register limits CI_SLV_CPL_STATIC_ALLOC_LIMIT_(N)S", }, { col => undef, table => undef, text => "chip interface control register" }, { col => "heading", table => 1, text => "PCIE_LC_STATE6 - R - 32 bits - PCIEIND:0x22", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_PREV_STATE24" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "24th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE25" }, { col => 1, table => 1, text => "13:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "25th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE26" }, { col => 1, table => 1, text => "21:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "26th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE27" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "27th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 2, text => "PCIE_LC_STATE7 - R - 32 bits - PCIEIND:0x23", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_PREV_STATE28" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "28th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE29" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "29th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE30" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "30th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE31" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "31st previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 3, text => "PCIE_LC_STATE8 - R - 32 bits - PCIEIND:0x24", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "LC_PREV_STATE32" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "32nd previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE33" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "33rd previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE34" }, { col => 1, table => 3, text => "21:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "34th previous state" }, { col => 0, table => 3, text => "LC_PREV_STATE35" }, { col => 1, table => 3, text => "29:24" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "35th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => undef, table => undef, text => "PCIE_LC_STATE9 - R - 32 bits - PCIEIND:0x25", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 62, text => [ { col => 0, table => 0, text => "LC_PREV_STATE36" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "36th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE37" }, { col => 1, table => 0, text => "13:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "37th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE38" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "38th previous state" }, { col => 0, table => 0, text => "LC_PREV_STATE39" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "39th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 1, text => "PCIE_LC_STATE10 - R - 32 bits - PCIEIND:0x26", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_PREV_STATE40" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "40th previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE41" }, { col => 1, table => 1, text => "13:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "41st previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE42" }, { col => 1, table => 1, text => "21:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "42nd previous state" }, { col => 0, table => 1, text => "LC_PREV_STATE43" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "43rd previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 2, text => "PCIE_LC_STATE11 - R - 32 bits - PCIEIND:0x27", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_PREV_STATE44" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "44th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE45" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "45th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE46" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "46th previous state" }, { col => 0, table => 2, text => "LC_PREV_STATE47" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "47th previous state" }, { col => undef, table => undef, text => "Link Control State Registers" }, { col => "heading", table => 3, text => "PCIE_P_CNTL - RW - 32 bits - PCIEIND:0x40", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "P_PWRDN_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down transmitter and receiver pads along ", }, { col => 3, table => 3, text => "with PLL macros", }, { col => 0, table => 3, text => "P_SYMALIGN_MODE" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Data Valid generation bit - iMODE = 0 (Relax Mode): ", }, { col => 3, table => 3, text => "update its symbol right away when detect ", }, { col => 3, table => 3, text => "any bit shift, i.e. data_valid will always ", }, { col => 3, table => 3, text => "assert. iMODE = 1 (Aggressive Mode): need confirmation ", }, { col => 3, table => 3, text => "before muxing out the data", }, { col => 0, table => 3, text => "P_PLL_PWRDN_IN_L1L23" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable PLL powerdown in L1 or L23 Ready states - only if ", }, { col => 3, table => 3, text => "all the associated LC's are in Sates L1 / ", }, { col => 3, table => 3, text => "L23 corresponding to 4 / 2 lanes based ", }, { col => 3, table => 3, text => "on mpConfig and architecture" }, { col => 0, table => 3, text => "P_PLL_BUF_PDNB" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x1" }, { col => 3, table => 3, text => "Disable 10X clock pad on a per PLL basis - should be 1'b0 ", }, { col => 3, table => 3, text => "in order to activate this powersafe feature.", }, { col => 3, table => 3, text => " 0=Enable PLL Buffer to power down during L1 ", }, { col => 3, table => 3, text => " 1=Always keep PLL Buffer running " }, { col => 0, table => 3, text => "P_TXCLK_SND_PWRDN" }, { col => 1, table => 3, text => 5 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down TXCLK clock pads on the transmit ", }, { col => 3, table => 3, text => "side. Each clock pad corresponds to logic ", }, { col => 3, table => 3, text => "associated with 4 lanes." }, { col => 0, table => 3, text => "P_TXCLK_RCV_PWRDN" }, { col => 1, table => 3, text => 6 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable powering down TXCLK clock pads on the receive ", }, { col => 3, table => 3, text => "side. Each clock pad corresponds to logic ", }, { col => 3, table => 3, text => "associated with 4 lanes." }, ], }, { num => 63, text => [ { col => 0, table => 0, text => "PI_SYMALIGN_DIS_ELIDLE" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol Alignment Statemachine control signal: ", }, { col => 3, table => 0, text => "iDIS_ELIDLE = 0, ElectIdle assertion will ", }, { col => 3, table => 0, text => "be effective in state machine ", }, { col => 3, table => 0, text => "re-initialization. iDIS_ELIDLE = 1, ElectIdle will be ", }, { col => 3, table => 0, text => "ineffective in state machine ", }, { col => 3, table => 0, text => "re-initialization" }, { col => 0, table => 0, text => "P_MASK_RCVR_EIDLE_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable EIDLE mask for powered down receivers.", }, { col => 3, table => 0, text => " 0=dont intercept ELEC_IDLE in power down ", }, { col => 3, table => 0, text => " 1=intercept ELEC_IDLE in RX power down ", }, { col => 0, table => 0, text => "P_PLL_PDNB" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Enable PLL only (not the buffer) to power down in L1 or ", }, { col => 3, table => 0, text => "L23ready states." }, { col => 3, table => 0, text => " 0=Enable PLL to power down during L1 ", }, { col => 3, table => 0, text => " 1=Always keep PLL running " }, { col => 0, table => 0, text => "P_EBUF_SYNC_MODE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=double flops " }, { col => 3, table => 0, text => " 1=single flop " }, { col => 0, table => 0, text => "P_LDSK_MASK_RCVR_ELEC_IDLE" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=GEN1:not mask-off GEN2: mask-off " }, { col => 3, table => 0, text => " 1=mask-off for GEN1 and GEN2 " }, { col => 0, table => 0, text => "P_ALLOW_PRX_FRONTEND_SHUTOFF" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable PHY's RX FRONTEND to shut off during L1 when ", }, { col => 3, table => 0, text => "PLL power down is enabled." }, { col => 3, table => 0, text => " 0=RX Frontend is always power on " }, { col => 3, table => 0, text => " 1=RX Frontend is shutoff during L1 when PLL power ", }, { col => 3, table => 0, text => "down is enabled " }, { col => 0, table => 0, text => "P_ALWAYS_USE_FAST_TXCLK" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bypass TXCLK_SWITCH and use 500MHz TXCLK from ", }, { col => 3, table => 0, text => "PLL for both GEN1 and GEN2 speed." }, { col => 3, table => 0, text => " 0=TXCLK will be either 250MHz or 500MHz depends on ", }, { col => 3, table => 0, text => "port speeds " }, { col => 3, table => 0, text => " 1=Bypass TXCLK_SWITCH and always use 500MHz ", }, { col => 3, table => 0, text => "TXCLK " }, { col => 0, table => 0, text => "P_ELEC_IDLE_MODE" }, { col => 1, table => 0, text => "15:14" }, { col => 2, table => 0, text => "0x0Electrical Idle Mode for PI (Physical Layer).", }, { col => 3, table => 0, text => " 0=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:infer, ", }, { col => 3, table => 0, text => "exit:PHY " }, { col => 3, table => 0, text => " 1=GEN1 - entry:infer, exit:PHY; GEN2 - entry:infer, exit ", }, { col => 3, table => 0, text => "PHY " }, { col => 3, table => 0, text => " 2=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:PHY, ", }, { col => 3, table => 0, text => "exit:PHY " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "RXP_XBAR_MUX0" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b0", }, { col => 0, table => 0, text => "RXP_XBAR_MUX1" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b1", }, { col => 0, table => 0, text => "RXP_XBAR_MUX2" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b2", }, { col => 0, table => 0, text => "RXP_XBAR_MUX3" }, { col => 1, table => 0, text => "23:22" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => "Data routing cross bar mux - default 1'b3", }, { col => 0, table => 0, text => "PI_RXEN_GATER" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x2" }, { col => 0, table => 0, text => "RXP_REALIGN_ON_EACH_TSX_OR_S" }, { col => 0, table => 0, text => "KP" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=LDSK only taking deskew on deskewing error detect ", }, { col => 3, table => 0, text => " 1=taking deskew on every TSX and SKP OS ", }, { col => 0, table => 0, text => "LC_RXP_DONT_ALIGN_ON_TSx" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Control Lane Deskew TS detection in L1 and L23", }, { col => 3, table => 0, text => " 0=Don't mask out TS ordered sets during L1 and L23. ", }, { col => 3, table => 0, text => " 1=Mask out lane deskew TSx detection during L1 and ", }, { col => undef, table => undef, text => "L23. " }, { col => undef, table => undef, text => "PHY Control Register" }, { col => undef, table => undef, text => "PCIE_P_BUF_STATUS - RW - 32 bits - PCIEIND:0x41", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_0" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_1" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "P_ELASTIC_BUF_OVERFLOW_2" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => undef, table => undef, text => 2 }, ], }, { num => 64, text => [ { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_3" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 3 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_4" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 4 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_5" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 5 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_6" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 6 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_7" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 7 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_8" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 8 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_9" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 9 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_10" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 10 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_11" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 11 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_12" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 12 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_13" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 13 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_14" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 14 }, { col => 0, table => 0, text => "P_ELASTIC_BUF_OVERFLOW_15" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Rx to Tx time domain hand-off buffer under/over flow: lane ", }, { col => 3, table => 0, text => 15 }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 0", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_1" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 1", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_2" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 2", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_3" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 3", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_4" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 4", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_5" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 5", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_6" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 6", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_7" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 7", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_8" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 8", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_9" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 9", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_10" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 10", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_11" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 11", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_12" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 12", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_13" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 13", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_14" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Symbol skew buffer over/underflow: lane 14", }, { col => 0, table => 0, text => "P_DESKEW_BUF_OVERFLOW_15" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Symbol skew buffer over/underflow: lane 15", }, { col => undef, table => undef, text => "PHY BUFFER STATUS REGISTER" }, { col => undef, table => undef, text => "PCIE_P_DECODER_STATUS - RW - 32 bits - PCIEIND:0x42", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_DECODE_ERR_0" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_1" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_2" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DECODE_ERR_3" }, { col => undef, table => undef, text => 3 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the decoding error, i.e. Can't ", }, { col => undef, table => undef, text => "decode the incoming data. bit15 => Lane ", }, { col => undef, table => undef, text => "15 (0 = OK, 1 = error), etc" }, ], }, { num => 66, text => [ { col => undef, table => undef, text => "P_DISPARITY_ERR_13" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DISPARITY_ERR_14" }, { col => undef, table => undef, text => 30 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "P_DISPARITY_ERR_15" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Indicates which lane has the link error: bit15 => Lane 15 (0 ", }, { col => undef, table => undef, text => "= OK, 1 = error), etc" }, { col => undef, table => undef, text => "PHY DECODER STATUS REGISTER" }, { col => "heading", table => 0, text => "PCIE_P_MISC_DEBUG_STATUS - RW - 32 bits - PCIEIND:0x43", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "P_LANE_REVERSAL (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Lane Reversal" }, { col => 3, table => 0, text => " 0=All lane order is normal " }, { col => 3, table => 0, text => " 1=All lane order is reversed " }, { col => 0, table => 0, text => "P_HW_DEBUG" }, { col => 1, table => 0, text => "15:4" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "P_INSERT_ERROR_0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 0", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane0 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_1" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 1", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane1 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_2" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 2", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane2 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_3" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 3", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane3 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_4" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 4", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane4 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_5" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 5", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane5 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_6" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 6", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane6 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_7" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 7", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane7 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_8" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 8", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane8 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_9" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 9", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane9 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, { col => 0, table => 0, text => "P_INSERT_ERROR_10" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Transmit invalid symbol 10'b0001111001 on lane 10", }, { col => 3, table => 0, text => " 0=Normal Operation " }, { col => 3, table => 0, text => " 1=Inserting error on Transmitting Lane10 by replacing one ", }, { col => 3, table => 0, text => "symbol with an invalid symbol " }, ], }, { num => 67, text => [ { col => undef, table => undef, text => "P_INSERT_ERROR_11" }, { col => undef, table => undef, text => 27 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 11", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane11 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_12" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 12", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane12 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_13" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 13", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane13 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_14" }, { col => undef, table => undef, text => 30 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 14", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane14 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "P_INSERT_ERROR_15" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Transmit invalid symbol 10'b0001111001 on lane 15", }, { col => undef, table => undef, text => " 0=Normal Operation " }, { col => undef, table => undef, text => " 1=Inserting error on Transmitting Lane15 by replacing one ", }, { col => undef, table => undef, text => "symbol with an invalid symbol " }, { col => undef, table => undef, text => "PHY MISCELLANEOUS DEBUG STATUS REGISTER", }, { col => "heading", table => 1, text => "PCIE_P_SYMSYNC_CTL - RW - 32 bits - PCIEIND:0x46", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "P_SYMSYNC_ELECT_IDLE_DET_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Use Electrical Idle Detect to filter out garbage data", }, { col => 0, table => 1, text => "P_SYMSYNC_SYNC_MODE" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "SYMSYNC synchronous mode - 1 look for iMGood ", }, { col => 3, table => 1, text => "consecutive good COMMAs, 0 look for iMGood consecutive ", }, { col => 3, table => 1, text => "good symbols" }, { col => 0, table => 1, text => "P_SYMSYNC_M_GOOD" }, { col => 1, table => 1, text => "9:2" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "M parameter of Good symbols or Commas (should be ", }, { col => 3, table => 1, text => "greater than two)" }, { col => 0, table => 1, text => "P_SYMSYNC_N_BAD" }, { col => 1, table => 1, text => "17:10" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "N parameter of Bad symbols (can be 1 or more)", }, { col => 0, table => 1, text => "P_SYMSYNC_PAD_MODE" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "Mode select of Good known symbols for replacement of the ", }, { col => 3, table => 1, text => "Bad symbols" }, { col => 0, table => 1, text => "P_SYMSYNC_BYPASS_MODE" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Bypass mode - 1 just let data and DValid flow through", }, { col => 3, table => 1, text => " 0=Bypass Symsync and Disable Symsync ", }, { col => 3, table => 1, text => " 1=Enable Symsync " }, { col => 0, table => 1, text => "P_SYMSYNC_ENABLE_IN_GEN1" }, { col => 1, table => 1, text => 21 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable Symsync for GEN1" }, { col => 3, table => 1, text => " 0=SYMSYNC is enabled for GEN2 only " }, { col => undef, table => undef, text => " 1=Enable Symsync for GEN1 as well ", }, { col => undef, table => undef, text => "SYMSYNC Control Registers" }, { col => undef, table => undef, text => "PCIE_P_IMP_CNTL_STRENGTH - RW - 32 bits - PCIEIND:0x60", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "P_TX_STR_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of current controller", }, { col => undef, table => undef, text => "P_TX_IMP_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of TX impedance controller", }, { col => undef, table => undef, text => "P_RX_IMP_CNTL_READ_BACK (R)" }, { col => undef, table => undef, text => "11:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Store the readback value of RX impedance controller", }, { col => undef, table => undef, text => "P_TX_STR_CNTL" }, { col => undef, table => undef, text => "19:16" }, { col => undef, table => undef, text => "0x7" }, { col => undef, table => undef, text => "Set the initial default current strength to 4'b0111", }, { col => undef, table => undef, text => "P_TX_IMP_CNTL" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x6" }, { col => undef, table => undef, text => "Default TX impedance control value", }, { col => undef, table => undef, text => "P_RX_IMP_CNTL" }, { col => undef, table => undef, text => "27:24" }, { col => undef, table => undef, text => "0x6" }, { col => undef, table => undef, text => "Default RX impedance control value", }, { col => undef, table => undef, text => "PI_HALT_IMP_CAL" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "P_PAD_MANUAL_OVERRIDE" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable Current and Impedance control values to override", }, { col => undef, table => undef, text => " 0=Allow normal impedance compensation operation ", }, { col => undef, table => undef, text => " 1=Default to manual settings ", }, ], }, { num => 68, text => [ { col => undef, table => undef, text => "PHY IMPEDANCE CONTROL STRENGTH REGISTER", }, { col => "heading", table => 0, text => "PCIE_P_IMP_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x61", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "P_IMP_PAD_UPDATE_RATE" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0xe" }, { col => 3, table => 0, text => "PAD's update interval" }, { col => 3, table => 0, text => " 0=PHY130 default 0xf " }, { col => 3, table => 0, text => " 1=PHY90 default 0xe " }, { col => 0, table => 0, text => "P_IMP_PAD_SAMPLE_DELAY" }, { col => 1, table => 0, text => "12:8" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Sampling window" }, { col => 0, table => 0, text => "P_IMP_PAD_INC_THRESHOLD" }, { col => 1, table => 0, text => "20:16" }, { col => 2, table => 0, text => "0x18" }, { col => 3, table => 0, text => "Incremental resolution" }, { col => 0, table => 0, text => "P_IMP_PAD_DEC_THRESHOLD" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x8" }, { col => undef, table => undef, text => "Decremental resolution" }, { col => undef, table => undef, text => "Impedance PAD defaults" }, { col => "heading", table => 1, text => "PCIE_P_STR_CNTL_UPDATE - RW - 32 bits - PCIEIND:0x62", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "P_STR_PAD_UPDATE_RATE" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0xf" }, { col => 3, table => 1, text => "PAD's update interval" }, { col => 3, table => 1, text => " 0=PHY130 default 0xf " }, { col => 3, table => 1, text => " 1=PHY90 default 0xe " }, { col => 0, table => 1, text => "P_STR_PAD_SAMPLE_DELAY" }, { col => 1, table => 1, text => "12:8" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Sampling window" }, { col => 0, table => 1, text => "P_STR_PAD_INC_THRESHOLD" }, { col => 1, table => 1, text => "20:16" }, { col => 2, table => 1, text => "0x18" }, { col => 3, table => 1, text => "Incremental resolution" }, { col => 0, table => 1, text => "P_STR_PAD_DEC_THRESHOLD" }, { col => 1, table => 1, text => "28:24" }, { col => 2, table => 1, text => "0x8" }, { col => undef, table => undef, text => "Decremental resolution" }, { col => undef, table => undef, text => "Current PAD defaults" }, { col => "heading", table => 2, text => "PCIE_P_PAD_MISC_CNTL - RW - 32 bits - PCIEIND:0x63", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "P_PAD_I_DUMMYOUT (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 0 if PMOS cur is stronger", }, { col => 0, table => 2, text => "P_PAD_IMP_DUMMYOUT (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 0 if PMOS imp is stronger", }, { col => 0, table => 2, text => "P_PAD_IMP_TESTOUT (R)" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Input from analog - 1 if NMOS imp is stronger", }, { col => 0, table => 2, text => "P_LINK_RETRAIN_ON_ERR_EN" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Disable error counts in LaneDeskew if Symbol unlocking, ", }, { col => 3, table => 2, text => "Code Errors or Deskew Errors are detected", }, { col => 0, table => 2, text => "P_PLLCAL_INC_LOWER_PHASE" }, { col => 1, table => 2, text => "6:4" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=0us " }, { col => 3, table => 2, text => " 1=1us " }, { col => 3, table => 2, text => " 2=2us " }, { col => 3, table => 2, text => " 3=4us " }, { col => 3, table => 2, text => " 4=8us " }, { col => 3, table => 2, text => " 5=12us " }, { col => 3, table => 2, text => " 6=16us " }, { col => undef, table => undef, text => " 7=24us " }, { col => undef, table => undef, text => "Pad Miscellaneous Control Registers", }, { col => undef, table => undef, text => "PCIE_P_DECODE_ERR_CNTL - RW - 32 bits - PCIEIND:0xEF", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "CODE_ERR_CNT_RESET" }, { col => undef, table => undef, text => "15:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DISPARITY_ERR_CNT_RESET" }, { col => undef, table => undef, text => "31:16" }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 69, text => [ { col => "heading", table => 0, text => "PCIE_P_DECODE_ERR_CNT_0 - R - 32 bits - PCIEIND:0xF0", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CODE_ERR_CNT_0" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_0" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_1 - R - 32 bits - PCIEIND:0xF1", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_1" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_1" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_2 - R - 32 bits - PCIEIND:0xF2", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_2" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_2" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_3 - R - 32 bits - PCIEIND:0xF3", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_3" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_3" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_4 - R - 32 bits - PCIEIND:0xF4", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_4" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_4" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "PCIE_P_DECODE_ERR_CNT_5 - R - 32 bits - PCIEIND:0xF5", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, ], }, { num => 70, text => [ { col => 0, table => 0, text => "CODE_ERR_CNT_5" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_5" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_6 - R - 32 bits - PCIEIND:0xF6", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_6" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_6" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_7 - R - 32 bits - PCIEIND:0xF7", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_7" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_7" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_8 - R - 32 bits - PCIEIND:0xF8", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_8" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_8" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_9 - R - 32 bits - PCIEIND:0xF9", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_9" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_9" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "PCIE_P_DECODE_ERR_CNT_10 - R - 32 bits - PCIEIND:0xFA", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "CODE_ERR_CNT_10" }, { col => 1, table => 5, text => "15:0" }, { col => 2, table => 5, text => "0x0" }, { col => 0, table => 5, text => "DISPARITY_ERR_CNT_10" }, { col => 1, table => 5, text => "31:16" }, { col => 2, table => 5, text => "0x0" }, { col => undef, table => undef, text => "PCIE_P_DECODE_ERR_CNT_11 - R - 32 bits - PCIEIND:0xFB", }, ], }, { num => 71, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CODE_ERR_CNT_11" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DISPARITY_ERR_CNT_11" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "PCIE_P_DECODE_ERR_CNT_12 - R - 32 bits - PCIEIND:0xFC", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CODE_ERR_CNT_12" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DISPARITY_ERR_CNT_12" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "PCIE_P_DECODE_ERR_CNT_13 - R - 32 bits - PCIEIND:0xFD", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CODE_ERR_CNT_13" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "DISPARITY_ERR_CNT_13" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "PCIE_P_DECODE_ERR_CNT_14 - R - 32 bits - PCIEIND:0xFE", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CODE_ERR_CNT_14" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DISPARITY_ERR_CNT_14" }, { col => 1, table => 3, text => "31:16" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "PCIE_P_DECODE_ERR_CNT_15 - R - 32 bits - PCIEIND:0xFF", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CODE_ERR_CNT_15" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => 0, table => 4, text => "DISPARITY_ERR_CNT_15" }, { col => 1, table => 4, text => "31:16" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "PCIE_TX_CNTL - RW - 32 bits - PCIEIND_P:0x20", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TX_REPLAY_NUM_COUNT (R)" }, { col => undef, table => undef, text => "9:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TX Replay Number Counter - counter to keep track of the ", }, { col => undef, table => undef, text => "number of replays that have occured", }, { col => undef, table => undef, text => "TX_SNR_OVERRIDE" }, { col => undef, table => undef, text => "11:10" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Snoop Not Required Override - control of the Snoop bit for ", }, { col => undef, table => undef, text => "master requests" }, { col => undef, table => undef, text => " 0=Generate bit as normal " }, { col => undef, table => undef, text => " 1=Override equation, and always set bit ", }, { col => undef, table => undef, text => " 2=Override equation, and always clear bit ", }, { col => undef, table => undef, text => " 3=Invalid " }, ], }, { num => 72, text => [ { col => 0, table => 0, text => "TX_RO_OVERRIDE" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Relaxed Ordering Override - control relaxed ordering bit for ", }, { col => 3, table => 0, text => "master requests" }, { col => 3, table => 0, text => " 0=Generate bit as normal " }, { col => 3, table => 0, text => " 1=Override equation, and always set bit ", }, { col => 3, table => 0, text => " 2=Override equation, and always clear bit ", }, { col => 3, table => 0, text => " 3=Invalid " }, { col => 0, table => 0, text => "TX_PACK_PACKET_DIS" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Packet Packing Disable - back-to-back packing of TLP and ", }, { col => 3, table => 0, text => "DLLP" }, { col => 3, table => 0, text => " 0=Place packets as close as allowable ", }, { col => 3, table => 0, text => " 1=Place STP/SDP in lane 0 only " }, { col => 0, table => 0, text => "TX_GENERATE_CRC_ERR" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Generate CRC errors from TX by zeroing CRC field.", }, { col => 3, table => 0, text => " 0=Generate proper CRC " }, { col => 3, table => 0, text => " 1=Generate bad CRC " }, { col => 0, table => 0, text => "TX_GAP_BTW_PKTS" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of idle cycles between DLLP and TLP", }, { col => 0, table => 0, text => "TX_FLUSH_TLP_DIS" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Disable flushing TLPs when Data Link is down", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "TX_CPL_PASS_P" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ordering rule: Let Completion Pass Posted", }, { col => 3, table => 0, text => " 0=no pass " }, { col => 3, table => 0, text => " 1=CPL pass " }, { col => 0, table => 0, text => "TX_NP_PASS_P" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ordering rule: Let Non-Posted Pass Posted", }, { col => 3, table => 0, text => " 0=no pass " }, { col => 3, table => 0, text => " 1=NP pass " }, { col => 0, table => 0, text => "TX_FC_UPDATE_TIMEOUT_SEL" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "To adjust the length of the timeout interval before sending ", }, { col => 3, table => 0, text => "out flow control update" }, { col => 3, table => 0, text => " 0=Disable flow control " }, { col => 3, table => 0, text => " 1=4x clock cycle " }, { col => 3, table => 0, text => " 2=1024x clock cycle " }, { col => 3, table => 0, text => " 3=4096x clock cycle " }, { col => 0, table => 0, text => "TX_FC_UPDATE_TIMEOUT" }, { col => 1, table => 0, text => "31:26" }, { col => 2, table => 0, text => "0x7" }, { col => undef, table => undef, text => "Interval length to send flow control update", }, { col => undef, table => undef, text => "TX Control Register" }, { col => "heading", table => 1, text => "PCIE_TX_SEQ - R - 32 bits - PCIEIND_P:0x24", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TX_NEXT_TRANSMIT_SEQ" }, { col => 1, table => 1, text => "11:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Next Transmit Sequence Number to send out", }, { col => 0, table => 1, text => "TX_ACKD_SEQ" }, { col => 1, table => 1, text => "27:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Last Acknowledged Sequence Number", }, { col => undef, table => undef, text => "TX Sequence Register" }, { col => "heading", table => 2, text => "PCIE_TX_REPLAY - RW - 32 bits - PCIEIND_P:0x25", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TX_REPLAY_NUM" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "Register to control Replay Number before Link goes to ", }, { col => 3, table => 2, text => "Retrain" }, { col => 0, table => 2, text => "TX_REPLAY_TIMER_OVERWRITE" }, { col => 1, table => 2, text => 15 }, { col => 2, table => 2, text => "0x0Trigger for Replay Timer" }, { col => 0, table => 2, text => "TX_REPLAY_TIMER" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x90" }, { col => undef, table => undef, text => "Replay Timer - when expired do Replay", }, { col => undef, table => undef, text => "TX Replay Register" }, { col => "heading", table => 3, text => "PCIE_ERR_CNTL - RW - 32 bits - PCIEIND_P:0x6A", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ERR_REPORTING_DIS" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Disable PCI Express Advanced Error Reporting", }, ], }, { num => 73, text => [ { col => 0, table => 0, text => "ERR_GEN_INTERRUPT" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Interrupt Generation for errors" }, { col => 0, table => 0, text => "SYM_UNLOCKED_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Reporting of Symbol Unlocked Errors", }, { col => 3, table => 0, text => " 0=disable reporting unlocked symbol errors ", }, { col => undef, table => undef, text => " 1=report unlocked symbol errors ", }, { col => undef, table => undef, text => "Error Control Registers" }, { col => "heading", table => 1, text => "PCIE_RX_CNTL - RW - 32 bits - PCIEIND_P:0x70", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "RX_IGNORE_IO_ERR" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed I/O TLP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_BE_ERR" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Byte Enable TLP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_MSG_ERR" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Message Error" }, { col => 0, table => 1, text => "RX_IGNORE_CRC_ERR (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore CRC Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CFG_ERR" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Configuration Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CPL_ERR" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Completion Errors" }, { col => 0, table => 1, text => "RX_IGNORE_EP_ERR" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed EP Errors" }, { col => 0, table => 1, text => "RX_IGNORE_LEN_MISMATCH_ERR" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Length Mismatch Errors" }, { col => 0, table => 1, text => "RX_IGNORE_MAX_PAYLOAD_ERR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Maximum Payload Errors" }, { col => 0, table => 1, text => "RX_IGNORE_TC_ERR" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Malformed Traffic Class Errors" }, { col => 0, table => 1, text => "RX_IGNORE_CFG_UR" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "RX_IGNORE_IO_UR" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "RX_IGNORE_VEND0_UR" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Ignore Vendor Type 0 Messages" }, { col => 0, table => 1, text => "RX_NAK_IF_FIFO_FULL" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Send NAK if RX internal FIFO is full" }, { col => 0, table => 1, text => "RX_GEN_ONE_NAK" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Generate NAK only for the first bad packet until replayed", }, { col => 0, table => 1, text => "RX_FC_INIT_FROM_REG" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Flow Control Initialization from registers", }, { col => 3, table => 1, text => " 0=Init FC from FIFO sizes " }, { col => 3, table => 1, text => " 1=Init FC from registers " }, { col => 0, table => 1, text => "RX_RCB_CPL_TIMEOUT" }, { col => 1, table => 1, text => "18:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RCB cpl timeout" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=50us " }, { col => 3, table => 1, text => " 2=2.5ms " }, { col => 3, table => 1, text => " 3=6.25ms " }, { col => 3, table => 1, text => " 4=12.5ms " }, { col => 3, table => 1, text => " 5=25ms " }, { col => 3, table => 1, text => " 6=125ms " }, { col => 3, table => 1, text => " 7=0.25ms " }, { col => 0, table => 1, text => "RX_RCB_CPL_TIMEOUT_MODE" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RCB cpl timeout on link down" }, { col => 0, table => 1, text => "RX_PCIE_CPL_TIMEOUT_DIS" }, { col => 1, table => 1, text => 20 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "RX Control Register" }, { col => "heading", table => 2, text => "PCIE_RX_CREDITS_ALLOCATED_P - R - 32 bits - PCIEIND_P:0x80", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_CREDITS_ALLOCATED_PD" }, { col => 1, table => 2, text => "11:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP data, t h e n u m b e r o f F C u n i t s g r a n t e d ", }, { col => 3, table => 2, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 2, text => "RX_CREDITS_ALLOCATED_PH" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP header, the number of FC units granted ", }, { col => undef, table => undef, text => "to transmitter since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Allocated Register (Posted)", }, { col => "heading", table => 3, text => "PCIE_RX_CREDITS_ALLOCATED_NP - R - 32 bits - PCIEIND_P:0x81", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 74, text => [ { col => 0, table => 0, text => "RX_CREDITS_ALLOCATED_NPD" }, { col => 1, table => 0, text => "11:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For non-posted TLP data, the number of F C u n i t s g r a n t e d ", }, { col => 3, table => 0, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 0, text => "RX_CREDITS_ALLOCATED_NPH" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For non-posted TLP header, the number of FC units ", }, { col => 3, table => 0, text => "granted to transmitter since initialization, ", }, { col => undef, table => undef, text => "modulo 256" }, { col => undef, table => undef, text => "RX Credits Allocated Register (Non-Posted)", }, { col => "heading", table => 1, text => "PCIE_RX_CREDITS_ALLOCATED_CPL - R - 32 bits - PCIEIND_P:0x82", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "R X _ C R E D I T S _ A L L O C A T E D _ C P L D", }, { col => 2, table => 1, text => "1 1 : 0" }, { col => 3, table => 1, text => "0 x 0" }, { col => 3, table => 1, text => "F o r c o m p l e t i o n T L P d a t a , t h e n u m b e r o f F C u n i t s g r a n t e d ", }, { col => 3, table => 1, text => "to transmitter since initialization, modulo 4096", }, { col => 0, table => 1, text => "RX_CREDITS_ALLOCATED_CPLH" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "For completion TLP header, the number of FC units granted ", }, { col => undef, table => undef, text => "to transmitter since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Allocated Register (Completion)", }, { col => "heading", table => 2, text => "PCIE_RX_CREDITS_RECEIVED_P - R - 32 bits - PCIEIND_P:0x83", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RX_CREDITS_RECEIVED_PD" }, { col => 1, table => 2, text => "11:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted T L P d a t a , t h e n u m b e r o f F C u n i t s c o n s u m e d ", }, { col => 3, table => 2, text => "by valid TLP received since initialization, modulo 4096", }, { col => 0, table => 2, text => "RX_CREDITS_RECEIVED_PH" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For posted TLP header, the number of FC units consumed ", }, { col => undef, table => undef, text => "by valid TLP received since initialization, modulo 256", }, { col => undef, table => undef, text => "RX Credits Received Register (Posted)", }, { col => "heading", table => 3, text => "PCIE_RX_CREDITS_RECEIVED_NP - R - 32 bits - PCIEIND_P:0x84", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RX_CREDITS_RECEIVED_NPD" }, { col => 1, table => 3, text => "11:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "For non-posted TLP data, the number of FC units ", }, { col => 3, table => 3, text => "consumed by valid TLP received since ", }, { col => 3, table => 3, text => "initialization, modulo 4096" }, { col => 0, table => 3, text => "RX_CREDITS_RECEIVED_NPH" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "For non-posted TLP header, the number of FC units ", }, { col => 3, table => 3, text => "consumed by valid TLP received since ", }, { col => undef, table => undef, text => "initialization, modulo 256" }, { col => undef, table => undef, text => "RX Credits Received Register (Non-Posted)", }, { col => "heading", table => 4, text => "PCIE_RX_CREDITS_RECEIVED_CPL - R - 32 bits - PCIEIND_P:0x85", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "RX_CREDITS_RECEIVED_CPLD" }, { col => 1, table => 4, text => "11:0" }, { col => 2, table => 4, text => "0x0For completion TLP data, the number of FC units consumed ", }, { col => 3, table => 4, text => " by valid TLP received since " }, { col => 3, table => 4, text => "initialization, module 4096" }, { col => 0, table => 4, text => "RX_CREDITS_RECEIVED_CPLH" }, { col => 1, table => 4, text => "23:16" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "For completion TLP header, the number of FC units ", }, { col => 3, table => 4, text => "consumed by valid TLP received since ", }, { col => undef, table => undef, text => "initialization, module 256" }, { col => undef, table => undef, text => "RX Credits Received Register (Completion)", }, ], }, { num => 75, text => [ { col => "heading", table => 0, text => "PCIE_LC_CNTL - RW - 32 bits - PCIEIND_P:0xA0", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "LC_CM_HI_ENABLE_COUNT" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable count for CM_HIGH - when transmitter is to be ", }, { col => 3, table => 0, text => "turned on stop when the counter reaches ", }, { col => 3, table => 0, text => "CM_HI_COUNT_LIMIT_ON. If number ", }, { col => 3, table => 0, text => "o f l a n e s = 1 o r 2 : C M _ H I _ C O U N T _ L I M I T _ O N = 1 2 o r 1 0 . ", }, { col => 3, table => 0, text => "If number of lanes = 3 or 4: CM_HI_COUNT_LIMIT_ON = ", }, { col => 3, table => 0, text => "10 or 12. If number of lanes > 4: ", }, { col => 3, table => 0, text => "CM_HI_COUNT_LIMIT_ON = 10 or 15." }, { col => 0, table => 0, text => "LC_DONT_ENTER_L23_IN_D0" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Do not enter L23 in D0 state." }, { col => 0, table => 0, text => "LC_RESET_L_IDLE_COUNT_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable reset of electrical idle counter.", }, { col => 0, table => 0, text => "LC_RESET_LINK" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reset an individual link without resetting the other ports.", }, { col => 0, table => 0, text => "LC_16X_CLEAR_TX_PIPE" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x5" }, { col => 3, table => 0, text => "Adjust the time that the LC waits for the pipe to be idle. ", }, { col => 3, table => 0, text => "Setting this field to 0 results in the maximum time. ", }, { col => 3, table => 0, text => "Otherwise, the delay increases as this field is incremented.", }, { col => 0, table => 0, text => "LC_L0S_INACTIVITY" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "L0s inactivity timer setting" }, { col => 3, table => 0, text => " 0=L0s is disabled " }, { col => 3, table => 0, text => " 1=40ns " }, { col => 3, table => 0, text => " 2=80ns " }, { col => 3, table => 0, text => " 3=120ns " }, { col => 3, table => 0, text => " 4=200ns " }, { col => 3, table => 0, text => " 5=400ns " }, { col => 3, table => 0, text => " 6=1us " }, { col => 3, table => 0, text => " 7=2us " }, { col => 3, table => 0, text => " 8=4us " }, { col => 3, table => 0, text => " 9=10us " }, { col => 3, table => 0, text => " 10=40us " }, { col => 3, table => 0, text => " 11=100us " }, { col => 3, table => 0, text => " 12=400us " }, { col => 3, table => 0, text => " 13=1ms " }, { col => 3, table => 0, text => " 14=4ms " }, { col => 0, table => 0, text => "LC_L1_INACTIVITY" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "L1 inactivity timer setting" }, { col => 3, table => 0, text => " 0=L1 is disabled " }, { col => 3, table => 0, text => " 1=1us " }, { col => 3, table => 0, text => " 2=2us " }, { col => 3, table => 0, text => " 3=4us " }, { col => 3, table => 0, text => " 4=10us " }, { col => 3, table => 0, text => " 5=20us " }, { col => 3, table => 0, text => " 6=40us " }, { col => 3, table => 0, text => " 7=100us " }, { col => 3, table => 0, text => " 8=400us " }, { col => 3, table => 0, text => " 9=1ms " }, { col => 3, table => 0, text => " 10=4ms " }, { col => 3, table => 0, text => " 11=10ms " }, { col => 3, table => 0, text => " 12=40ms " }, { col => 3, table => 0, text => " 13=100ms " }, { col => 3, table => 0, text => " 14=400ms " }, { col => 0, table => 0, text => "LC_PMI_TO_L1_DIS" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable the transition to L1 caused by programming ", }, { col => 3, table => 0, text => "PMI_STATE to non-D0" }, { col => 0, table => 0, text => "LC_INC_N_FTS_EN" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable incrementing N_FTS for each transition to recovery", }, { col => 0, table => 0, text => "LC_LOOK_FOR_IDLE_IN_L1L23" }, { col => 1, table => 0, text => "19:18" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the number of clocks to wait for Electrical Idle set ", }, { col => 3, table => 0, text => "in L1, L23" }, { col => 3, table => 0, text => " 0=250 " }, { col => 3, table => 0, text => " 1=100 " }, { col => 3, table => 0, text => " 2=10000 " }, { col => 3, table => 0, text => " 3=3000000 " }, { col => 0, table => 0, text => "LC_FACTOR_IN_EXT_SYNC" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Factor in the extended sync bit in the calculation for the ", }, { col => 3, table => 0, text => "replay timer adjustment" }, ], }, { num => 76, text => [ { col => 0, table => 0, text => "LC_WAIT_FOR_PM_ACK_DIS" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disables waiting for PM_ACK in L23 ready entry handshake", }, { col => 0, table => 0, text => "LC_WAKE_FROM_L23" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For upstream component, wake the link from L23 ready", }, { col => 0, table => 0, text => "LC_L1_IMMEDIATE_ACK" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Always ACK an ASPM L1 entry DLLP (ie. never generate ", }, { col => 3, table => 0, text => "PM_NAK)" }, { col => 0, table => 0, text => "LC_ASPM_TO_L1_DIS" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disable ASPM L1" }, { col => 0, table => 0, text => "LC_DELAY_COUNT" }, { col => 1, table => 0, text => "26:25" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls minimum amount of time to stay in L0s or L1", }, { col => 3, table => 0, text => " 0=255/ 4095 (Power-down) " }, { col => 3, table => 0, text => " 1=1250 / 16383 (Power-down) " }, { col => 3, table => 0, text => " 2=5000/ 65535 (Power-down) " }, { col => 3, table => 0, text => " 3=25000 / 262143 (Power-down) " }, { col => 0, table => 0, text => "LC_DELAY_L0S_EXIT" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable staying in L0s for a minimum time", }, { col => 0, table => 0, text => "LC_DELAY_L1_EXIT" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable staying in L1 for a minimum time" }, { col => 0, table => 0, text => "LC_EXTEND_WAIT_FOR_EL_IDLE" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Wait for Electrical idle in L1/L23 ready value", }, { col => 0, table => 0, text => "LC_ESCAPE_L1L23_EN" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Enable L1/L23 entry escape arcs" }, { col => 0, table => 0, text => "LC_GATE_RCVR_IDLE" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ignore PHY Electrical idle detector" }, { col => 3, table => 0, text => " 0=LC will look for PE_LC_IdleDetected ", }, { col => 3, table => 0, text => " 1=To gate off PE_LC_IdleDetected to LC, so that LC ", }, { col => undef, table => undef, text => "never sees receivers enter EIDLE ", }, { col => undef, table => undef, text => "Link Control Register" }, { col => undef, table => undef, text => "PCIE_LC_CNTL2 - RW - 32 bits - PCIEIND_P:0xB1", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "LC_TIMED_OUT_STATE (R)" }, { col => undef, table => undef, text => "5:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "State that the LC was in when the deadman timer expired.", }, { col => undef, table => undef, text => "LC_STATE_TIMED_OUT" }, { col => undef, table => undef, text => 6 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Deadman timer expired." }, { col => undef, table => undef, text => "LC_LOOK_FOR_BW_REDUCTION" }, { col => undef, table => undef, text => 7 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Enable check for bandwidth change when reporting Link ", }, { col => undef, table => undef, text => "Bandwidth Notification Status." }, { col => undef, table => undef, text => " 0=Do not check if bandwidth was reduced. ", }, { col => undef, table => undef, text => " 1=Check if bandwidth was reduced. ", }, { col => undef, table => undef, text => "LC_MORE_TS2_EN" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Send out 128 sets instead of 16.", }, { col => undef, table => undef, text => "LC_X12_NEGOTIATION_DIS" }, { col => undef, table => undef, text => 9 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Disable x12 negotiation." }, { col => undef, table => undef, text => "LC_LINK_UP_REVERSAL_EN" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Allow reversal for a wider width in link up.", }, { col => undef, table => undef, text => "LC_ILLEGAL_STATE" }, { col => undef, table => undef, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The LC is in an illegal state." }, { col => undef, table => undef, text => "LC_ILLEGAL_STATE_RESTART_EN" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable the LC to be restarted when it is in an illegal state.", }, { col => undef, table => undef, text => "LC_WAIT_FOR_OTHER_LANES_MODE" }, { col => undef, table => undef, text => 13 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Eliminate delay introduced by waiting for other lanes.", }, { col => undef, table => undef, text => " 0=Identical Training Set based . ", }, { col => undef, table => undef, text => " 1=Timer based. " }, { col => undef, table => undef, text => "LC_ELEC_IDLE_MODE" }, { col => undef, table => undef, text => "15:14" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Electrical Idle Mode for LC." }, { col => undef, table => undef, text => " 0=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:infer, ", }, { col => undef, table => undef, text => "exit:PHY " }, { col => undef, table => undef, text => " 1=GEN1 - entry:infer, exit:PHY; GEN2 - entry:infer, exit ", }, { col => undef, table => undef, text => "PHY " }, { col => undef, table => undef, text => " 2=GEN1 - entry:PHY, exit:PHY ; GEN2 - entry:PHY, ", }, { col => undef, table => undef, text => "exit:PHY " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "LC_DISABLE_INFERRED_ELEC_IDLE_" }, { col => undef, table => undef, text => "DET" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Disable Inferred Electrical Idle detection.", }, { col => undef, table => undef, text => " 0=Inferred Electrical Idle Detection is enabled ", }, { col => undef, table => undef, text => " 1=Inferred Electrical Idle Detection is disabled ", }, { col => undef, table => undef, text => "LC_ALLOW_PDWN_IN_L1" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set the BIF_CHIP_CLK_PDWN output to 1 when the LC is ", }, { col => undef, table => undef, text => "in the L1 state." }, { col => undef, table => undef, text => "LC_ALLOW_PDWN_IN_L23" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set the BIF_CHIP_CLK_PDWN output to 1 when the LC is ", }, { col => undef, table => undef, text => "in the L23_Ready state." }, { col => undef, table => undef, text => "LC_DEASSERT_RX_EN_IN_L0S" }, { col => undef, table => undef, text => 19 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Turn off transmitters when the link is in L0s.", }, { col => undef, table => undef, text => "LC_BLOCK_EL_IDLE_IN_L0" }, { col => undef, table => undef, text => 20 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Prevent the Electrical Idle from causing a transition from ", }, { col => undef, table => undef, text => "Rcv_L0 to Rcv_L0s." }, { col => undef, table => undef, text => "LC_RCV_L0_TO_RCV_L0S_DIS" }, { col => undef, table => undef, text => 21 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Disable transition from Rcv_L0 to Rcv_L0s", }, { col => undef, table => undef, text => "LC_ASSERT_INACTIVE_DURING_HOL" }, { col => undef, table => undef, text => "D" }, { col => undef, table => undef, text => 22 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Assert the INACTIVE_LANES signals when ", }, { col => undef, table => undef, text => "CHIP_BIF_hold_training is high." }, { col => undef, table => undef, text => "LC_WAIT_FOR_LANES_IN_LW_NEG" }, { col => undef, table => undef, text => "24:23" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "LC_PWR_DOWN_NEG_OFF_LANES" }, { col => undef, table => undef, text => 25 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "LC_DISABLE_LOST_SYM_LOCK_ARCS" }, { col => undef, table => undef, text => 26 }, { col => undef, table => undef, text => "0x1" }, ], }, { num => 77, text => [ { col => 0, table => 0, text => "LC_LINK_BW_NOTIFICATION_DIS (R)" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "LC_ENABLE_RX_CR_EN_DEASSERTIO" }, { col => 0, table => 0, text => "N" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "To enable deassertion of PG2RX_CR_EN to lock clock ", }, { col => 3, table => 0, text => "recovery parameter when lane is in electrical idle", }, { col => 3, table => 0, text => " 0=CR_EN is always asserted " }, { col => 3, table => 0, text => " 1=CR_EN is deasserted when RX_EN is deasserted ", }, { col => 3, table => 0, text => "during L0s/L1 and inactive lanes " }, { col => 0, table => 0, text => "LC_TEST_TIMER_SEL" }, { col => 1, table => 0, text => "30:29" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "State timeout select" }, { col => 3, table => 0, text => " 0=LTSSM uses spec compliant timeout values. ", }, { col => 3, table => 0, text => " 1=LTSSM uses simulation timeout values. ", }, { col => 3, table => 0, text => " 2=LTSSM uses decreased timeout values for lab testing. ", }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "LC_ENABLE_INFERRED_ELEC_IDLE_F" }, { col => 0, table => 0, text => "OR_PI" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Enable Inferred Electrical Idle Detection for PI (Physical ", }, { col => 3, table => 0, text => "Layer blocks)" }, { col => 3, table => 0, text => " 0=Inferred Electrical Idle Detection is disabled for PI ", }, { col => 3, table => 0, text => "(Physical Layer block) " }, { col => 3, table => 0, text => " 1=Inferred Electrical Idle Detection is enabled for PI ", }, { col => undef, table => undef, text => "(Physical Layer block) " }, { col => undef, table => undef, text => "Link Control Register 2" }, { col => "heading", table => 1, text => "PCIE_LC_LINK_WIDTH_CNTL - RW - 32 bits - PCIEIND_P:0xA2", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_LINK_WIDTH" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x6" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "LC_LINK_WIDTH_RD (R)" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Read back link width" }, { col => 0, table => 1, text => "LC_RECONFIG_ARC_MISSING_ESCAP" }, { col => 0, table => 1, text => "E" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "LC_RECONFIG_NOW" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "LC_RENEGOTIATION_SUPPORT (R)" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 3, table => 1, text => " 0=Other end does not support link width renegotiation. ", }, { col => 3, table => 1, text => " 1=Other end does support link width renegotiation. ", }, { col => 0, table => 1, text => "LC_RENEGOTIATE_EN" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable re-negotiation" }, { col => 0, table => 1, text => "LC_SHORT_RECONFIG_EN" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "RESERVED" }, { col => 0, table => 1, text => "LC_UPCONFIGURE_SUPPORT" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "LC_UPCONFIGURE_DIS" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "LC_UPCFG_WAIT_FOR_RCVR_DIS" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Enable " }, { col => 3, table => 1, text => " 1=Disable " }, { col => 0, table => 1, text => "LC_UPCFG_TIMER_SEL" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=1 msec " }, { col => 3, table => 1, text => " 1=use LC_WAIT_FOR_LANES_IN_LW_NEG values ", }, { col => 0, table => 1, text => "LC_DEASSERT_TX_PDNB" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "TX_PDNB Control for unused lanes" }, { col => 3, table => 1, text => " 0=Keep TX_PDNB asserts for unused lanes. ", }, { col => undef, table => undef, text => " 1=Deassert TX_PDNB for unused lanes ", }, { col => undef, table => undef, text => "Link Width Control" }, { col => "heading", table => 2, text => "PCIE_LC_N_FTS_CNTL - RW - 32 bits - PCIEIND_P:0xA3", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_XMIT_N_FTS" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xc" }, { col => 3, table => 2, text => "Number of FTS to override the strap value", }, { col => 0, table => 2, text => "LC_XMIT_N_FTS_OVERRIDE_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable the previous field to override the strap value.", }, { col => 0, table => 2, text => "LC_XMIT_FTS_BEFORE_RECOVERY" }, { col => 1, table => 2, text => 9 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Transmit FTS before Recovery." }, { col => 0, table => 2, text => "LC_XMIT_N_FTS_LIMIT" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "Limit that the number of FTS can increment to when ", }, { col => 3, table => 2, text => "incrementing is enabled." }, { col => 0, table => 2, text => "LC_N_FTS (R)" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Number of FTS captured from the other end of the link.", }, { col => undef, table => undef, text => "LC Number of FTS Control" }, ], }, { num => 78, text => [ { col => "heading", table => 0, text => "PCIE_LC_STATE0 - R - 32 bits - PCIEIND_P:0xA5", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "LC_CURRENT_STATE" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Current LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE1" }, { col => 1, table => 0, text => "13:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "1st Previous LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE2" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "2nd Previous LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE3" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "3rd Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, { col => "heading", table => 1, text => "PCIE_LC_STATE1 - R - 32 bits - PCIEIND_P:0xA6", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LC_PREV_STATE4" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "4th Previous LC State" }, { col => 0, table => 1, text => "LC_PREV_STATE5" }, { col => 1, table => 1, text => "13:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "5th Previous LC State" }, { col => 0, table => 1, text => "LC_PREV_STATE6" }, { col => 1, table => 1, text => "21:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "6th Previous LC State" }, { col => 0, table => 1, text => "LC_PREV_STATE7" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "7th Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, { col => "heading", table => 2, text => "PCIE_LC_STATE2 - R - 32 bits - PCIEIND_P:0xA7", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "LC_PREV_STATE8" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "8th Previous LC State" }, { col => 0, table => 2, text => "LC_PREV_STATE9" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "9th Previous LC State" }, { col => 0, table => 2, text => "LC_PREV_STATE10" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "10th Previous LC State" }, { col => 0, table => 2, text => "LC_PREV_STATE11" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "11th Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, { col => "heading", table => 3, text => "PCIE_LC_STATE3 - R - 32 bits - PCIEIND_P:0xA8", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "LC_PREV_STATE12" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "12th Previous LC State" }, { col => 0, table => 3, text => "LC_PREV_STATE13" }, { col => 1, table => 3, text => "13:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "13th Previous LC State" }, { col => 0, table => 3, text => "LC_PREV_STATE14" }, { col => 1, table => 3, text => "21:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "14th Previous LC State" }, { col => 0, table => 3, text => "LC_PREV_STATE15" }, { col => 1, table => 3, text => "29:24" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "15th Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, { col => "heading", table => 4, text => "PCIE_LC_STATE4 - R - 32 bits - PCIEIND_P:0xA9", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "LC_PREV_STATE16" }, { col => 1, table => 4, text => "5:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "16th Previous LC State" }, { col => 0, table => 4, text => "LC_PREV_STATE17" }, { col => 1, table => 4, text => "13:8" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "17th Previous LC State" }, { col => 0, table => 4, text => "LC_PREV_STATE18" }, { col => 1, table => 4, text => "21:16" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "18th Previous LC State" }, { col => 0, table => 4, text => "LC_PREV_STATE19" }, { col => 1, table => 4, text => "29:24" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "19th Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, ], }, { num => 79, text => [ { col => "heading", table => 0, text => "PCIE_LC_STATE5 - R - 32 bits - PCIEIND_P:0xAA", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "LC_PREV_STATE20" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "20th Previous LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE21" }, { col => 1, table => 0, text => "13:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "21st Previous LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE22" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "22nd Previous LC State" }, { col => 0, table => 0, text => "LC_PREV_STATE23" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "23rd Previous LC State" }, { col => undef, table => undef, text => "Link Control State Register" }, { col => "heading", table => 1, text => "VENDOR_ID - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VENDOR_ID (R)" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x1002" }, { col => 3, table => 1, text => "This field identifies the manufacturer of the device. 0FFFFh ", }, { col => undef, table => undef, text => "is an invalid value for Vendor ID.", }, { col => undef, table => undef, text => "Vendor Identification" }, { col => "heading", table => 2, text => "DEVICE_ID - R - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x2]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DEVICE_ID" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "This field identifies the particular device. This identifier is ", }, { col => undef, table => undef, text => "allocated by the vendor." }, { col => undef, table => undef, text => "Device Identification" }, { col => undef, table => undef, text => "COMMAND - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "IO_ACCESS_EN" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls a device's response to I/O Space accesses. A ", }, { col => undef, table => undef, text => "value of 0 disables the device response. A value of 1 allows ", }, { col => undef, table => undef, text => "the device to respond to I/O Space accesses.State after ", }, { col => undef, table => undef, text => "RST# is 0." }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "MEM_ACCESS_EN" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls a device's response to Memory Space accesses. ", }, { col => undef, table => undef, text => "A value of 0 disables the device response. A value of 1 ", }, { col => undef, table => undef, text => "allows the device to respond to Memory Space accesses. ", }, { col => undef, table => undef, text => "State after RST# is 0." }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "BUS_MASTER_EN" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls the ability of a PCI Express Endpoint to issue ", }, { col => undef, table => undef, text => "Memory and I/O Read/Write Requests, and the ability of a ", }, { col => undef, table => undef, text => "Root or Switch Port to forward Memory and I/O Read/Write ", }, { col => undef, table => undef, text => "Requests in the upstream direction.", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, ], }, { num => 80, text => [ { col => 0, table => 0, text => "SPECIAL_CYCLE_EN (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "MEM_WRITE_INVALIDATE_EN (R)" }, { col => 1, table => 0, text => "40x0" }, { col => 3, table => 0, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "PAL_SNOOP_EN (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "PARITY_ERROR_RESPONSE" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Parity Error Response. Default value of this field is 0.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "AD_STEPPING (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Address and Data Stepping. Does not apply to PCI ", }, { col => 3, table => 0, text => "Express. Hardwired to 0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "SERR_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When set, enables reporting of Non-fatal and Fatal errors ", }, { col => 3, table => 0, text => "detected by the device to the Root Complex.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "FAST_B2B_EN (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "INT_DIS" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the ability of a PCI Express device to generate ", }, { col => 3, table => 0, text => "INTx interrupt Messages. When set, devices are prevented ", }, { col => 3, table => 0, text => "from generating INTx interrupt Messages. Default value 0", }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "The Command register provides coarse control over a device's ability to generate and respond to PCI cycles.", }, { col => "heading", table => 1, text => "STATUS - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x6]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "INT_STATUS (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Indicates that an INTx interrupt Message is pending ", }, { col => 3, table => 1, text => "internally to the device." }, { col => 0, table => 1, text => "CAP_LIST (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Indicates the presence of an extended capability list item. ", }, { col => 3, table => 1, text => "Since all PCI Express devices are required to implement ", }, { col => 3, table => 1, text => "the PCI Express capability structure, this bit must be set to ", }, { col => 3, table => 1, text => "1." }, { col => 0, table => 1, text => "PCI_66_EN (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 0, table => 1, text => "UDF_EN (R)" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "User Defined Status Enable" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "FAST_BACK_CAPABLE (R)" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 0, table => 1, text => "MASTER_DATA_PARITY_ERROR" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This bit is set by Requestor if its Parity Error Enable bit is ", }, { col => 3, table => 1, text => "s e t a n d e i t h e r o f t h e f o l l o w i n g t w o c o n d i t i o n s o c c u r s : ", }, { col => 3, table => 1, text => "1) Requestor receives a Completion marked poisoned ", }, { col => 3, table => 1, text => "2) Requestor poisons a write Request" }, { col => 3, table => 1, text => " 0=Inactive " }, { col => 3, table => 1, text => " 1=Active " }, { col => 0, table => 1, text => "DEVSEL_TIMING (R)" }, { col => 1, table => 1, text => "10:9" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 0, table => 1, text => "SIGNAL_TARGET_ABORT (R)" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This bit is set when a device completes a Request using ", }, { col => 3, table => 1, text => "Completer Abort Completion Status." }, { col => 3, table => 1, text => " 0=No Abort " }, { col => 3, table => 1, text => " 1=Target Abort " }, ], }, { num => 81, text => [ { col => 0, table => 0, text => "RECEIVED_TARGET_ABORT" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit is set when a Requestor receives a Completion with ", }, { col => 3, table => 0, text => "Unsupported Request Completion Status." }, { col => 3, table => 0, text => " 0=Inactive " }, { col => 3, table => 0, text => " 1=Active " }, { col => 0, table => 0, text => "RECEIVED_MASTER_ABORT" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit is set when a Requestor receives a Completion with ", }, { col => 3, table => 0, text => "Unsupported Request Completion Status." }, { col => 3, table => 0, text => " 0=Inactive " }, { col => 3, table => 0, text => " 1=Active " }, { col => 0, table => 0, text => "SIGNALED_SYSTEM_ERROR" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit must be set whenever the device asserts SERR#.", }, { col => 3, table => 0, text => " 0=No Error " }, { col => 3, table => 0, text => " 1=SERR assert " }, { col => 0, table => 0, text => "PARITY_ERROR_DETECTED" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit is set when a device sends an ERR_FATAL or ", }, { col => 3, table => 0, text => "ERR_NONFATAL Message, and the SERR Enable bit in ", }, { col => undef, table => undef, text => "the Command register is 1." }, { col => undef, table => undef, text => "The Status register is used to record status information for PCI bus related events.", }, { col => "heading", table => 1, text => "REVISION_ID - R - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MINOR_REV_ID" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Major revision ID. Set by the vendor." }, { col => 0, table => 1, text => "MAJOR_REV_ID" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Minor revision ID. Set by the vendor.", }, { col => undef, table => undef, text => "Specifies a device specific revision identifier. The value is chosen by the vendor.", }, { col => "heading", table => 2, text => "PROG_INTERFACE - R - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x9]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "PROG_INTERFACE" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Unused, only in test environment", }, { col => undef, table => undef, text => "Register-Level Programming Interface Register", }, { col => "heading", table => 3, text => "SUB_CLASS - R - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SUB_CLASS" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "The Class Code register is read-only and is used with the ", }, { col => undef, table => undef, text => "Base Class Code to identify the specific type of device.", }, { col => undef, table => undef, text => "Sub Class Code Register" }, { col => "heading", table => 4, text => "BASE_CLASS - R - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xB]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "BASE_CLASS" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "The Class Code register is read-only and is used to identify ", }, { col => undef, table => undef, text => "the generic function of the device.", }, { col => undef, table => undef, text => "Base Class Code Register" }, ], }, { num => 82, text => [ { col => "heading", table => 0, text => "CACHE_LINE - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xC]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CACHE_LINE_SIZE" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This read/write register specifies the system cacheline size ", }, { col => undef, table => undef, text => "in units of DWORDs." }, { col => undef, table => undef, text => "Cache Line Size Register" }, { col => "heading", table => 1, text => "LATENCY - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xD]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LATENCY_TIMER (R)" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary/Master latency timer does not apply to PCI ", }, { col => undef, table => undef, text => "Express. Register is hardwired to 0.", }, { col => undef, table => undef, text => "Master Latency Timer Register" }, { col => "heading", table => 2, text => "HEADER - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xE]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "HEADER_TYPE (R)" }, { col => 1, table => 2, text => "6:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Type 0 or Type 1 Configuration Space" }, { col => 0, table => 2, text => "DEVICE_TYPE (R)" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Single function or multi function device", }, { col => 3, table => 2, text => " 0=Single-Function Device " }, { col => undef, table => undef, text => " 1=Multi-Function Device " }, { col => undef, table => undef, text => "Configuration Space Header" }, { col => "heading", table => 3, text => "BIST - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xF]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "BIST_COMP (R)" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "A value of 0 means the device has passed its test. Non-zero ", }, { col => 3, table => 3, text => "values mean the device failed. Device-specific failure codes ", }, { col => 3, table => 3, text => "can be encoded in the non-zero value." }, { col => 0, table => 3, text => "BIST_STRT (R)" }, { col => 1, table => 3, text => 6 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Write a 1 to invoke BIST. Device resets the bit when BIST is ", }, { col => 3, table => 3, text => "complete. Software should fail the device if BIST is not ", }, { col => 3, table => 3, text => "complete after 2 seconds." }, { col => 0, table => 3, text => "BIST_CAP (R)" }, { col => 1, table => 3, text => 7 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "This bit is read-only and returns 1 the bridge supports BIST, ", }, { col => undef, table => undef, text => "otherwise 0 is returned" }, { col => undef, table => undef, text => "Built In Self Test Register used for control and status of built-in self tests", }, { col => "heading", table => 4, text => "CAP_PTR - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x34]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CAP_PTR (R)" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x50" }, { col => 3, table => 4, text => "Pointer to a linked list of additional capabilities implemented ", }, { col => 3, table => 4, text => "by this device." }, { col => undef, table => undef, text => " 50=Point to PM Capability " }, { col => undef, table => undef, text => "Capability Pointer" }, ], }, { num => 83, text => [ { col => "heading", table => 0, text => "INTERRUPT_LINE - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x3C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "INTERRUPT_LINE" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0xff" }, { col => 3, table => 0, text => "Interrupt Line register communicates interrupt line routing ", }, { col => undef, table => undef, text => "information." }, { col => undef, table => undef, text => "Interrupt Line Register" }, { col => "heading", table => 1, text => "INTERRUPT_PIN - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x3D]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "INTERRUPT_PIN (R)" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The Interrupt Pin is a read-only register that identifies the ", }, { col => 3, table => 1, text => "legacy interrupt Message(s) the device (or device function) ", }, { col => 3, table => 1, text => "uses" }, { col => undef, table => undef, text => "NOTE: Bits 3:7 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Interrupt Pin Register" }, { col => "heading", table => 2, text => "ADAPTER_ID - R - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x2C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SUBSYSTEM_VENDOR_ID" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Subsystem Vendor ID. Specified by the vendor.", }, { col => 0, table => 2, text => "SUBSYSTEM_ID" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Subsystem ID. Specified by the vendor.", }, { col => undef, table => undef, text => "Subsystem Vendor and Subsystem ID Register", }, { col => "heading", table => 3, text => "MIN_GRANT - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x3E]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "MIN_GNT (R)" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Registers do not apply to PCI Express. Hardwired to 0.", }, { col => "heading", table => 4, text => "MAX_LATENCY - RW - 8 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x3F]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "MAX_LAT (R)" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Registers do not apply to PCI Express. Hardwired to 0.", }, { col => undef, table => undef, text => "ADAPTER_ID_W - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x4C]", }, ], }, { num => 84, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "SUBSYSTEM_VENDOR_ID" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Subsystem Vendor ID. Specified by the vendor.", }, { col => 0, table => 0, text => "SUBSYSTEM_ID" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Subsystem Vendor ID. Specified by the vendor.", }, { col => undef, table => undef, text => "Adapter ID" }, { col => "heading", table => 1, text => "PMI_CAP_LIST - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x50]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_ID (R)" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Capability ID Must be set to 01h" }, { col => 3, table => 1, text => " 1=PCIE Power Management Registers " }, { col => 0, table => 1, text => "NEXT_PTR (R)" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x58" }, { col => undef, table => undef, text => "Next Capability Pointer" }, { col => undef, table => undef, text => "Power Management Capbility List" }, { col => "heading", table => 2, text => "PMI_CAP - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x52]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VERSION (R)" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "Version" }, { col => 3, table => 2, text => " 3=PMI Spec 1.2 " }, { col => 0, table => 2, text => "PME_CLOCK (R)" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Does not apply to PCI Express. Hardwired to 0.", }, { col => 0, table => 2, text => "DEV_SPECIFIC_INIT (R)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Device Specific Initialization" }, { col => 0, table => 2, text => "AUX_CURRENT (R)" }, { col => 1, table => 2, text => "8:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "AUX Current" }, { col => 0, table => 2, text => "D1_SUPPORT (R)" }, { col => 1, table => 2, text => 9 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "D1 Support" }, { col => 3, table => 2, text => " 1=Support D1 PM State. " }, { col => 0, table => 2, text => "D2_SUPPORT (R)" }, { col => 1, table => 2, text => 10 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "D2 Support" }, { col => 3, table => 2, text => " 1=Support D2 PM State. " }, { col => 0, table => 2, text => "PME_SUPPORT (R)" }, { col => 1, table => 2, text => "15:11" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "For a device, this indicates the power states in which the ", }, { col => undef, table => undef, text => "device may generate a PME." }, { col => undef, table => undef, text => "Power Management Capabilities Register", }, { col => "heading", table => 3, text => "PMI_STATUS_CNTL - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x54]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "POWER_STATE" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Power State" }, { col => 0, table => 3, text => "NO_SOFT_RESET (R)" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "PME_EN (R)" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "PME Enable" }, { col => 0, table => 3, text => "DATA_SELECT (R)" }, { col => 1, table => 3, text => "12:9" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Data Select" }, { col => 0, table => 3, text => "DATA_SCALE (R)" }, { col => 1, table => 3, text => "14:13" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Data Scale" }, { col => 0, table => 3, text => "PME_STATUS (R)" }, { col => 1, table => 3, text => 15 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "PME Status" }, { col => 0, table => 3, text => "B2_B3_SUPPORT (R)" }, { col => 1, table => 3, text => 22 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "B2/B3 Support Does not apply to PCI Express. Hardwired ", }, { col => 3, table => 3, text => "to 0." }, { col => 0, table => 3, text => "BUS_PWR_EN (R)" }, { col => 1, table => 3, text => 23 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bus Power/Clock Control Enable Does not apply to PCI ", }, { col => 3, table => 3, text => "Express. Hardwired to 0." }, { col => 0, table => 3, text => "PMI_DATA (R)" }, { col => 1, table => 3, text => "31:24" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Data" }, { col => undef, table => undef, text => "Power Management Status/Control Register", }, { col => "heading", table => 4, text => "PCIE_CAP_LIST - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x58]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 85, text => [ { col => undef, table => undef, text => "CAP_ID (R)" }, { col => undef, table => undef, text => "7:0" }, { col => undef, table => undef, text => "0x10" }, { col => undef, table => undef, text => "Indicates the PCI Express Capability structure. This field ", }, { col => undef, table => undef, text => "must return a Capability ID of 10h indicating that this is a ", }, { col => undef, table => undef, text => "PCI Express Capability structure.", }, { col => undef, table => undef, text => " 10=PCI Express capable " }, { col => undef, table => undef, text => "NEXT_PTR (R)" }, { col => undef, table => undef, text => "15:8" }, { col => undef, table => undef, text => "0xa0" }, { col => undef, table => undef, text => "Next Capability Pointer -- The offset to the next PCI ", }, { col => undef, table => undef, text => "capability structure or 00h if no other items exist in the ", }, { col => undef, table => undef, text => "linked list of capabilities." }, { col => undef, table => undef, text => "The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 2.3 configuration space ", }, { col => undef, table => undef, text => "capability list." }, { col => "heading", table => 0, text => "PCIE_CAP - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x5A]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VERSION (R)" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "Indicates PCI-SIG defined PCI Express capability structure ", }, { col => 3, table => 0, text => "version number." }, { col => 3, table => 0, text => " 0=PCI Express Cap Version " }, { col => 0, table => 0, text => "DEVICE_TYPE (R)" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates the type of PCI Express logical device.", }, { col => 3, table => 0, text => " 0=PCI Express Endpoint " }, { col => 3, table => 0, text => " 1=Legacy PCI Express Endpoint " }, { col => 3, table => 0, text => " 4=PCI Express Root Complex " }, { col => 0, table => 0, text => "SLOT_IMPLEMENTED (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit when set indicates that the PCI Express Link ", }, { col => 3, table => 0, text => "associated with this Port is connected to a slot", }, { col => 0, table => 0, text => "INT_MESSAGE_NUM (R)" }, { col => 1, table => 0, text => "13:9" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt Message Number." }, { col => 0, table => 0, text => "TCS_ROUTING_SUPPORTED (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Trusted Configuration Routing supported.", }, { col => undef, table => undef, text => "The PCI Express Capabilities register identifies PCI Express device type and associated capabilities.", }, { col => "heading", table => 1, text => "DEVICE_CAP - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x5C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MAX_PAYLOAD_SUPPORT (R)" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the maximum payload size that the ", }, { col => 3, table => 1, text => "device can support for TLPs." }, { col => 3, table => 1, text => " 0=128B size " }, { col => 0, table => 1, text => "PHANTOM_FUNC (R)" }, { col => 1, table => 1, text => "4:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the support for use of unclaimed function ", }, { col => 3, table => 1, text => "numbers to extend the number of outstanding transactions ", }, { col => 3, table => 1, text => "allowed by logically combining unclaimed function numbers ", }, { col => 3, table => 1, text => "with the Tag identifier." }, { col => 3, table => 1, text => " 0=No Phantom Functions " }, { col => 0, table => 1, text => "EXTENDED_TAG (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "This field indicates the maximum supported size of the Tag ", }, { col => 3, table => 1, text => "field as a Requester." }, { col => 3, table => 1, text => " 0=8 Bit Tag Supported " }, { col => 0, table => 1, text => "L0S_ACCEPTABLE_LATENCY (R)" }, { col => 1, table => 1, text => "8:6" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the acceptable total latency that an ", }, { col => 3, table => 1, text => "Endpoint can withstand due to the transition from L0s state ", }, { col => 3, table => 1, text => "to the L0 state." }, { col => 0, table => 1, text => "L1_ACCEPTABLE_LATENCY (R)" }, { col => 1, table => 1, text => "11:9" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the acceptable latency that an Endpoint ", }, { col => 3, table => 1, text => "can withstand due to the transition from L1 state to the L0 ", }, { col => 3, table => 1, text => "state." }, { col => 0, table => 1, text => "ROLE_BASED_ERR_REPORTING (R)" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Role-Based Error Reporting Disabled ", }, { col => 3, table => 1, text => " 1=Role-Based Error Reporting Enabled ", }, { col => 0, table => 1, text => "CAPTURED_SLOT_POWER_LIMIT (R)" }, { col => 1, table => 1, text => "25:18" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "(Upstream Ports only) In combination with the Slot Power ", }, { col => 3, table => 1, text => "Limit Scale value, specifies the upper limit on power ", }, { col => 3, table => 1, text => "supplied by slot." }, { col => 0, table => 1, text => "CAPTURED_SLOT_POWER_SCALE (R)" }, { col => 1, table => 1, text => "27:26" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Specifies the scale used for the Slot Power Limit Value.", }, { col => 0, table => 1, text => "FLR_CAPABLE (R)" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates that a device is capable of initiating ", }, { col => undef, table => undef, text => "Function Level Resets." }, { col => undef, table => undef, text => "The Device Capabilities register identifies PCI Express device specific capabilities.", }, ], }, { num => 86, text => [ { col => undef, table => undef, text => "DEVICE_CNTL - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x60]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CORR_ERR_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit controls reporting of correctable errors. Default ", }, { col => 3, table => 0, text => "value of this field is 0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "NON_FATAL_ERR_EN" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit controls reporting of Non-fatal errors. Default value ", }, { col => 3, table => 0, text => "of this field is 0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "FATAL_ERR_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit controls reporting of Fatal errors. Default value of ", }, { col => 3, table => 0, text => "this field is 0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "USR_REPORT_EN" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit enables reporting of Unsupported Requests when ", }, { col => 3, table => 0, text => "set. Default value of this field is 0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "RELAXED_ORD_EN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "If this bit is set, the device is permitted to set the Relaxed ", }, { col => 3, table => 0, text => "Ordering bit in the Attributes field of ", }, { col => 3, table => 0, text => "transactions it initiates that do not require strong write ", }, { col => 3, table => 0, text => "ordering. Default value of this bit is 1.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "MAX_PAYLOAD_SIZE (R)" }, { col => 1, table => 0, text => "7:5" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field sets maximum TLP payload size for the device. ", }, { col => 3, table => 0, text => "Default value of this field is 000b." }, { col => 3, table => 0, text => " 0=128B size " }, { col => 0, table => 0, text => "EXTENDED_TAG_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When set, this bit enables a device to use an 8-bit Tag field ", }, { col => 3, table => 0, text => "as a requester. If the bit is cleared, the device ", }, { col => 3, table => 0, text => "is restricted to a 5-bit Tag field. Default value of this field is ", }, { col => 3, table => 0, text => "0." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "PHANTOM_FUNC_EN (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When set, this bit enables a device to use unclaimed ", }, { col => 3, table => 0, text => "functions as Phantom Functions to extend ", }, { col => 3, table => 0, text => "the number of outstanding transaction identifiers. If the bit is ", }, { col => 3, table => 0, text => "cleared, the device is not allowed to use ", }, { col => 3, table => 0, text => "Phantom Functions." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "AUX_POWER_PM_EN (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit when set enables a device to draw AUX power ", }, { col => 3, table => 0, text => "independent of PME AUX power." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "NO_SNOOP_EN" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "If this bit is set to 1, the device is permitted to set the No ", }, { col => 3, table => 0, text => "Snoop bit in the Requester Attributes of ", }, { col => 3, table => 0, text => "transactions it initiates that do not require hardware ", }, { col => 3, table => 0, text => "enforced cache coherency. Default value of this bit is 1.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "MAX_REQUEST_SIZE (R)" }, { col => 1, table => 0, text => "14:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field sets the maximum Read Request size for the ", }, { col => 3, table => 0, text => "Device as a Requester. Default value of this field is 010b.", }, { col => 3, table => 0, text => " 0=128B size " }, { col => 0, table => 0, text => "BRIDGE_CFG_RETRY_EN (R)" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "The Device Control register controls PCI Express device specific parameters.", }, ], }, { num => 87, text => [ { col => "heading", table => 0, text => "DEVICE_STATUS - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x62]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CORR_ERR" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit indicates status of correctable errors detected.", }, { col => 0, table => 0, text => "NON_FATAL_ERR" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit indicates status of Nonfatal errors detected.", }, { col => 0, table => 0, text => "FATAL_ERR" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit indicates status of Fatal errors detected.", }, { col => 0, table => 0, text => "USR_DETECTED" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit indicates that the device received an Unsupported ", }, { col => 3, table => 0, text => "Request." }, { col => 0, table => 0, text => "AUX_PWR (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Devices that require AUX power report this bit as set if AUX ", }, { col => 3, table => 0, text => "power is detected by the device." }, { col => 0, table => 0, text => "TRANSACTIONS_PEND (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Endpoints: This bit when set indicates that the device has ", }, { col => 3, table => 0, text => "issued Non-Posted Requests which have not been ", }, { col => 3, table => 0, text => "completed. Root and Switch Ports: This bit ", }, { col => 3, table => 0, text => "when set indicates that a Port has issued Non-Posted ", }, { col => 3, table => 0, text => "Requests on its own behalf (using the Port's own Requester ", }, { col => undef, table => undef, text => "ID) which have not been completed.", }, { col => undef, table => undef, text => "The Device Status register provides information about PCI Express device specific parameters.", }, { col => "heading", table => 1, text => "LINK_CAP - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x64]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LINK_SPEED (R)" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "This field indicates the maximum Link speed of the given ", }, { col => 3, table => 1, text => "PCI Express Link." }, { col => 3, table => 1, text => " 1=2.5 Gb/s " }, { col => 3, table => 1, text => " 2=5.0 Gb/s " }, { col => 0, table => 1, text => "LINK_WIDTH (R)" }, { col => 1, table => 1, text => "9:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the maximum width of the given PCI ", }, { col => 3, table => 1, text => "Express Link." }, { col => 3, table => 1, text => " 1=x1 " }, { col => 3, table => 1, text => " 2=x2 " }, { col => 3, table => 1, text => " 4=x4 " }, { col => 3, table => 1, text => " 8=x8 " }, { col => 3, table => 1, text => " 12=x12 " }, { col => 3, table => 1, text => " 16=x16 " }, { col => 3, table => 1, text => " 32=x32 " }, { col => 0, table => 1, text => "PM_SUPPORT (R)" }, { col => 1, table => 1, text => "11:10" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "This field indicates the level of ASPM supported on the ", }, { col => 3, table => 1, text => "given PCI Express Link." }, { col => 0, table => 1, text => "L0S_EXIT_LATENCY (R)" }, { col => 1, table => 1, text => "14:12" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "This field indicates the L0s exit latency for the given PCI ", }, { col => 3, table => 1, text => "Express Link. The value reported indicates ", }, { col => 3, table => 1, text => "the length of time this Port requires to complete transition ", }, { col => 3, table => 1, text => "from L0s to L0." }, { col => 0, table => 1, text => "L1_EXIT_LATENCY (R)" }, { col => 1, table => 1, text => "17:15" }, { col => 2, table => 1, text => "0x2" }, { col => 3, table => 1, text => "This field indicates the L0s exit latency for the given PCI ", }, { col => 3, table => 1, text => "Express Link. The value reported indicates ", }, { col => 3, table => 1, text => "the length of time this Port requires to complete transition ", }, { col => 3, table => 1, text => "from L0s to L0." }, { col => 0, table => 1, text => "CLOCK_POWER_MANAGEMENT (R)" }, { col => 1, table => 1, text => 18 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "SURPRISE_DOWN_ERR_REPORTING " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "DL_ACTIVE_REPORTING_CAPABLE (R)" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "LINK_BW_NOTIFICATION_CAP (R)" }, { col => 1, table => 1, text => 21 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PORT_NUMBER (R)" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This field indicates the PCI Express Port number for the ", }, { col => undef, table => undef, text => "given PCI Express Link." }, { col => undef, table => undef, text => "The Link Capabilities register identifies PCI Express Link specific capabilities.", }, ], }, { num => 88, text => [ { col => "heading", table => 0, text => "LINK_CNTL - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x68]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "PM_CONTROL" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field controls the level of ASPM supported on the given ", }, { col => 3, table => 0, text => "PCI Express Link. Defined encodings are: ", }, { col => 3, table => 0, text => "00b Disabled 01b L0s Entry ", }, { col => 3, table => 0, text => "Enabled 10b L1 Entry ", }, { col => 3, table => 0, text => "Enabled 11b L0s and L1 ", }, { col => 3, table => 0, text => "Entry Enabled" }, { col => 0, table => 0, text => "READ_CPL_BOUNDARY (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read Completion Boundary. Indicates the RCB value for ", }, { col => 3, table => 0, text => "the Root Port" }, { col => 3, table => 0, text => " 0=64 Byte " }, { col => 3, table => 0, text => " 1=128 Byte " }, { col => 0, table => 0, text => "LINK_DIS (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit disables the Link when set to 1b. Default value of ", }, { col => 3, table => 0, text => "this field is 0b." }, { col => 0, table => 0, text => "RETRAIN_LINK (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "A write of 1b to this bit initiates Link retraining by directing ", }, { col => 3, table => 0, text => "the Physical Layer LTSSM to the Recovery ", }, { col => 3, table => 0, text => "state. Reads of this bit always return 0b.", }, { col => 0, table => 0, text => "COMMON_CLOCK_CFG" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit when set indicates that this component and the ", }, { col => 3, table => 0, text => "component at the opposite end of this Link ", }, { col => 3, table => 0, text => "are operating with a distributed common reference clock. ", }, { col => 3, table => 0, text => "Default value of this field is 0b." }, { col => 0, table => 0, text => "EXTENDED_SYNC" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit when set forces the transmission of 4096 FTS ", }, { col => 3, table => 0, text => "ordered sets in the L0s state followed by ", }, { col => 3, table => 0, text => "a single SKP ordered set" }, { col => 0, table => 0, text => "CLOCK_POWER_MANAGEMENT_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit determines if device is permitted to use CLKREQ# ", }, { col => 3, table => 0, text => "signal to power manage link clock." }, { col => 0, table => 0, text => "HW_AUTONOMOUS_WIDTH_DISABLE" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When set to 1, this bit disables hardware from changing the ", }, { col => 3, table => 0, text => "link width for reasons other than attempting to ", }, { col => 3, table => 0, text => "correct unreliable link operation by reducing link width.", }, { col => 0, table => 0, text => "LINK_BW_MANAGEMENT_INT_EN (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "LINK_AUTONOMOUS_BW_INT_EN (R)" }, { col => 1, table => 0, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Link Control register controls PCI Express Link specific parameters.", }, { col => undef, table => undef, text => "LINK_STATUS - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x6A]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "CURRENT_LINK_SPEED (R)" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Indicates the negotiated Link speed of the given PCI ", }, { col => undef, table => undef, text => "Express Link" }, { col => undef, table => undef, text => " 1=2.5 Gb/s " }, { col => undef, table => undef, text => " 2=5.0 Gb/s " }, { col => undef, table => undef, text => "NEGOTIATED_LINK_WIDTH (R)" }, { col => undef, table => undef, text => "9:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This field indicates the negotiated width of the given PCI ", }, { col => undef, table => undef, text => "Express Link. Defined encodings are: ", }, { col => undef, table => undef, text => "000001b X1 000010b X2 ", }, { col => undef, table => undef, text => "000100b X4 001000b X8 ", }, { col => undef, table => undef, text => "001100b X12 010000b X16 ", }, { col => undef, table => undef, text => "100000b X32 All other ", }, { col => undef, table => undef, text => "encodings are reserved." }, { col => undef, table => undef, text => " 1=x1 " }, { col => undef, table => undef, text => " 2=x2 " }, { col => undef, table => undef, text => " 4=x4 " }, { col => undef, table => undef, text => " 8=x8 " }, { col => undef, table => undef, text => " 12=x12 " }, { col => undef, table => undef, text => " 16=x16 " }, { col => undef, table => undef, text => " 32=x32 " }, ], }, { num => 89, text => [ { col => 0, table => 0, text => "LINK_TRAINING (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This read-only bit indicates that Link training is in progress ", }, { col => 3, table => 0, text => "(Physical Layer LTSSM in Configuration or ", }, { col => 3, table => 0, text => "Recovery state) or that 1b was written to the Retrain Link bit ", }, { col => 3, table => 0, text => "but Link training has not yet begun. ", }, { col => 3, table => 0, text => "Hardware clears this bit once Link training is complete.", }, { col => 0, table => 0, text => "SLOT_CLOCK_CFG (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "This bit indicates that the component uses the same ", }, { col => 3, table => 0, text => "physical reference clock that the platform ", }, { col => 3, table => 0, text => "provides on the connector. If the device uses an ", }, { col => 3, table => 0, text => "independent clock irrespective of the ", }, { col => 3, table => 0, text => "presence of a reference on the connector, this bit must be ", }, { col => 3, table => 0, text => "clear." }, { col => 3, table => 0, text => " 0=Diff Clock " }, { col => 3, table => 0, text => " 1=Same Clock " }, { col => 0, table => 0, text => "DL_ACTIVE (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "LINK_BW_MANAGEMENT_STATUS (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "LINK_AUTONOMOUS_BW_STATUS (R)" }, { col => 1, table => 0, text => 15 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Link Status register provides information about PCI Express Link specific parameters.", }, { col => "heading", table => 1, text => "DEVICE_CAP2 - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x7C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CPL_TIMEOUT_RANGE_SUP (R)" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "PCIE completion timeout range supported" }, { col => 0, table => 1, text => "CPL_TIMEOUT_DIS_SUP (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "PCIE completion timeout disabled supported", }, { col => undef, table => undef, text => "The Device Capabilities 2 register identifies PCI Express device specific capabilities.", }, { col => "heading", table => 2, text => "DEVICE_CNTL2 - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x80]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CPL_TIMEOUT_VALUE" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "PCIE completion timeout value" }, { col => 0, table => 2, text => "CPL_TIMEOUT_DIS" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Disable PCIE completion timeout" }, { col => undef, table => undef, text => "The Device Control 2 register controls PCI Express device specific parameters.", }, { col => "heading", table => 3, text => "DEVICE_STATUS2 - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x82]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "RESERVED (R)" }, { col => 1, table => 3, text => "15:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Device Status 2 register provides information about PCI Express device specific parameters.", }, { col => "heading", table => 4, text => "LINK_CAP2 - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x84]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "RESERVED (R)" }, { col => 1, table => 4, text => "31:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Link Capabilities 2 register identifies PCI Express Link specific capabilities.", }, ], }, { num => 90, text => [ { col => "heading", table => 0, text => "LINK_CNTL2 - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x88]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TARGET_LINK_SPEED" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "The upper limit on the operational speed. This field restricts ", }, { col => 3, table => 0, text => "the data rate values advertised by an upstream component.", }, { col => 0, table => 0, text => "ENTER_COMPLIANCE" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit forces a port's transmitter to enter Compliance.", }, { col => 0, table => 0, text => "HW_AUTONOMOUS_SPEED_DISABLE" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0Controls the component's ability to autonomously direct ", }, { col => 3, table => 0, text => "changes in link speed." }, { col => 0, table => 0, text => "DE_EMPHASIS_SEL" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selectable de-emphasis (in GEN 2 data rate) 0 : -6dB, 1 : ", }, { col => 3, table => 0, text => "-3.6dB" }, { col => 0, table => 0, text => "DE_EMPHASIS_ENFORCE (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For RC, when this bit is set, CHIP should use de-emphasis ", }, { col => 3, table => 0, text => "value in bit 6 and ignore what was sent in TS1 ordereed ", }, { col => 3, table => 0, text => "sets in Recover.RcvrLock" }, { col => 0, table => 0, text => "XMIT_MARGIN" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "These bits control the value of the non-deemphasized ", }, { col => 3, table => 0, text => "voltage level at the transmitter pins" }, { col => 0, table => 0, text => "ENTER_MOD_COMPLIANCE" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "LTSSM transmits modified compliance pattern in ", }, { col => undef, table => undef, text => "Polling.Compliance if this bit is set to 1.", }, { col => undef, table => undef, text => "The Link Control 2 register controls PCI Express Link specific parameters.", }, { col => "heading", table => 1, text => "LINK_STATUS2 - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x8A]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "RESERVED (R)" }, { col => 1, table => 1, text => "15:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Link Status 2 register provides information about PCI Express Link specific parameters.", }, { col => "heading", table => 2, text => "MSI_CAP_LIST - R - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_ID" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => "Register identifies if a device function is MSI capable", }, { col => 0, table => 2, text => "NEXT_PTR" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Pointer to the next item on the capabilities list", }, { col => undef, table => undef, text => "Message Signaled Interrupt Capability Registers", }, { col => "heading", table => 3, text => "MSI_MSG_CNTL - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA2]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "MSI_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable MSI messaging" }, { col => 3, table => 3, text => " 0=Disable " }, { col => 3, table => 3, text => " 1=Enable " }, { col => 0, table => 3, text => "MSI_MULTI_CAP (R)" }, { col => 1, table => 3, text => "3:1" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Multiple Message Capable register is read to determine the ", }, { col => 3, table => 3, text => "number of requested messages." }, { col => 3, table => 3, text => " 0=1 message allocated " }, { col => 3, table => 3, text => " 1=2 messages allocated " }, { col => 3, table => 3, text => " 2=4 messages allocated " }, { col => 3, table => 3, text => " 3=8 messages allocated " }, { col => 3, table => 3, text => " 4=16 messages allocated " }, { col => 3, table => 3, text => " 5=32 messages allocated " }, { col => 3, table => 3, text => " 6=Reserved " }, { col => 3, table => 3, text => " 7=Reserved " }, ], }, { num => 91, text => [ { col => 0, table => 0, text => "MSI_MULTI_EN" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Multiple Message Enable register is written to indicate the ", }, { col => 3, table => 0, text => "number of allocated messages." }, { col => 3, table => 0, text => " 0=1 message allocated " }, { col => 3, table => 0, text => " 1=2 messages allocated " }, { col => 3, table => 0, text => " 2=4 messages allocated " }, { col => 3, table => 0, text => " 3=8 messages allocated " }, { col => 3, table => 0, text => " 4=16 messages allocated " }, { col => 3, table => 0, text => " 5=32 messages allocated " }, { col => 3, table => 0, text => " 6=Reserved " }, { col => 3, table => 0, text => " 7=Reserved " }, { col => 0, table => 0, text => "MSI_64BIT (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Signifies if a device function is capable of generating a ", }, { col => 3, table => 0, text => "64-bit message address" }, { col => 3, table => 0, text => " 0=Not capable of generating 1 64-bit message address ", }, { col => undef, table => undef, text => " 1=Capable of generating 1 64-bit message address ", }, { col => undef, table => undef, text => "Message Signaled Interrupts Control Register", }, { col => "heading", table => 1, text => "MSI_MSG_ADDR_LO - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MSI_MSG_ADDR_LO" }, { col => 1, table => 1, text => "31:2" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Message Lower Address - use lower 32-bits of address", }, { col => undef, table => undef, text => "Message Lower Address" }, { col => "heading", table => 2, text => "MSI_MSG_ADDR_HI - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MSI_MSG_ADDR_HI" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Message Upper Address - use upper 32-bit of address", }, { col => undef, table => undef, text => "Message Upper Address" }, { col => "heading", table => 3, text => "MSI_MSG_DATA_64 - RW - 16 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xAC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "MSI_DATA_64" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Message Data. System specified." }, { col => undef, table => undef, text => "64-bit MSI Message Data" }, { col => "heading", table => 4, text => "MSI_MSG_DATA - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0xA8]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "MSI_DATA" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "Message Data. System specified." }, { col => undef, table => undef, text => "MSI Message Data" }, { col => "heading", table => 5, text => "PCIE_ADV_ERR_RPT_ENH_CAP_LIST - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x150]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, ], }, { num => 92, text => [ { col => 0, table => 0, text => "CAP_ID (R)" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "This field is a PCI-SIG defined ID number that indicates the ", }, { col => 3, table => 0, text => "nature and format of the extended capability.", }, { col => 0, table => 0, text => "CAP_VER (R)" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "This field is a PCI-SIG defined version number that ", }, { col => 3, table => 0, text => "indicates the version of the capability structure present.", }, { col => 0, table => 0, text => "NEXT_PTR (R)" }, { col => 1, table => 0, text => "31:20" }, { col => 2, table => 0, text => "0x190" }, { col => 3, table => 0, text => "This field contains the offset to the next PCI Express ", }, { col => 3, table => 0, text => "capability structure or 000h if no other items exist in the ", }, { col => undef, table => undef, text => "linked list of capabilities." }, { col => undef, table => undef, text => "Advanced Error Reporting Enhanced Capability header", }, { col => "heading", table => 1, text => "PCIE_UNCORR_ERR_STATUS - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x154]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DLP_ERR_STATUS" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Data Link Protocol Error Status" }, { col => 0, table => 1, text => "SURPDN_ERR_STATUS (R)" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "PSN_ERR_STATUS" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Poisoned TLP Status" }, { col => 0, table => 1, text => "FC_ERR_STATUS (R)" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Flow Control Protocol Error Status" }, { col => 0, table => 1, text => "CPL_TIMEOUT_STATUS" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Completion Timeout Status" }, { col => 0, table => 1, text => "CPL_ABORT_ERR_STATUS (R)" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Completer Abort Status" }, { col => 0, table => 1, text => "UNEXP_CPL_STATUS" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Unexpected Completion Status" }, { col => 0, table => 1, text => "RCV_OVFL_STATUS (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Receiver Overflow Status" }, { col => 0, table => 1, text => "MAL_TLP_STATUS" }, { col => 1, table => 1, text => 18 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Malformed TLP Status" }, { col => 0, table => 1, text => "ECRC_ERR_STATUS (R)" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "ECRC Error Status" }, { col => 0, table => 1, text => "UNSUPP_REQ_ERR_STATUS" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Unsupported Request Error Status", }, { col => undef, table => undef, text => "The Uncorrectable Error Status register reports error status of individual error sources on a PCI Express device.", }, { col => "heading", table => 2, text => "PCIE_UNCORR_ERR_MASK - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x158]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DLP_ERR_MASK" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Data Link Protocol Error Mask" }, { col => 0, table => 2, text => "SURPDN_ERR_MASK (R)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "PSN_ERR_MASK" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Poisoned TLP Mask" }, { col => 0, table => 2, text => "FC_ERR_MASK (R)" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Flow Control Protocol Error Mask" }, { col => 0, table => 2, text => "CPL_TIMEOUT_MASK" }, { col => 1, table => 2, text => 14 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Completion Timeout Mask" }, { col => 0, table => 2, text => "CPL_ABORT_ERR_MASK (R)" }, { col => 1, table => 2, text => 15 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Completer Abort Mask" }, { col => 0, table => 2, text => "UNEXP_CPL_MASK" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Unexpected Completion Mask" }, { col => 0, table => 2, text => "RCV_OVFL_MASK (R)" }, { col => 1, table => 2, text => 17 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Receiver Overflow Mask" }, { col => 0, table => 2, text => "MAL_TLP_MASK" }, { col => 1, table => 2, text => 18 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Malformed TLP Mask" }, { col => 0, table => 2, text => "ECRC_ERR_MASK (R)" }, { col => 1, table => 2, text => 19 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "ECRC Error Mask" }, { col => 0, table => 2, text => "UNSUPP_REQ_ERR_MASK" }, { col => 1, table => 2, text => 20 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Unsupported Request Error Mask" }, { col => undef, table => undef, text => "The Uncorrectable Error Mask register controls reporting of individual errors by the device to the PCI Express Root Complex via ", }, { col => undef, table => undef, text => "a PCI Express error Message." }, { col => undef, table => undef, text => "PCIE_UNCORR_ERR_SEVERITY - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x15C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DLP_ERR_SEVERITY" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Data Link Protocol Error Severity", }, { col => undef, table => undef, text => "SURPDN_ERR_SEVERITY (R)" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "PSN_ERR_SEVERITY" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Poisoned TLP Severity" }, { col => undef, table => undef, text => "FC_ERR_SEVERITY (R)" }, { col => undef, table => undef, text => 13 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Flow Control Protocol Error Severity", }, { col => undef, table => undef, text => "CPL_TIMEOUT_SEVERITY" }, { col => undef, table => undef, text => 14 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Completion Timeout Error Severity", }, { col => undef, table => undef, text => "CPL_ABORT_ERR_SEVERITY (R)" }, { col => undef, table => undef, text => 15 }, { col => undef, table => undef, text => "0x0Completer Abort Error Severity", }, { col => undef, table => undef, text => "UNEXP_CPL_SEVERITY" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Unexpected Completion Error Severity", }, { col => undef, table => undef, text => "RCV_OVFL_SEVERITY (R)" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Receiver Overflow Error Severity", }, { col => undef, table => undef, text => "MAL_TLP_SEVERITY" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Malformed TLP Severity" }, ], }, { num => 93, text => [ { col => 0, table => 0, text => "ECRC_ERR_SEVERITY (R)" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ECRC Error Severity" }, { col => 0, table => 0, text => "UNSUPP_REQ_ERR_SEVERITY" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Unsupported Request Error Severity", }, { col => undef, table => undef, text => "The Uncorrectable Error Severity register controls whether an individual error is reported as a Nonfatal or Fatal error.", }, { col => "heading", table => 1, text => "PCIE_CORR_ERR_STATUS - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x160]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "RCV_ERR_STATUS" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Receiver Error Status (" }, { col => 0, table => 1, text => "BAD_TLP_STATUS" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bad TLP Status" }, { col => 0, table => 1, text => "BAD_DLLP_STATUS" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bad DLLP Status" }, { col => 0, table => 1, text => "REPLAY_NUM_ROLLOVER_STATUS" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "REPLAY_NUM Rollover Status" }, { col => 0, table => 1, text => "REPLAY_TIMER_TIMEOUT_STATUS" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Replay Timer Timeout Status" }, { col => 0, table => 1, text => "ADVISORY_NONFATAL_ERR_STATUS" }, { col => 1, table => 1, text => 13 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The Correctable Error Status register reports error status of individual correctable error sources on a PCI Express device.", }, { col => "heading", table => 2, text => "PCIE_CORR_ERR_MASK - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x164]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RCV_ERR_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Receiver Error Mask" }, { col => 0, table => 2, text => "BAD_TLP_MASK" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bad TLP Mask" }, { col => 0, table => 2, text => "BAD_DLLP_MASK" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bad DLLP Mask" }, { col => 0, table => 2, text => "REPLAY_NUM_ROLLOVER_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0REPLAY_NUM Rollover Mask" }, { col => 0, table => 2, text => "REPLAY_TIMER_TIMEOUT_MASK" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Replay Timer Timeout Mask" }, { col => 0, table => 2, text => "ADVISORY_NONFATAL_ERR_MASK" }, { col => 1, table => 2, text => 13 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "The Correctable Error Mask register controls reporting of individual correctable errors by device to the PCI Express Root ", }, { col => undef, table => undef, text => "Complex via a PCI Express error Message.", }, { col => "heading", table => 3, text => "PCIE_ADV_ERR_CAP_CNTL - RW - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x168]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "FIRST_ERR_PTR (R)" }, { col => 1, table => 3, text => "4:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "The First Error Pointer is a read-only register that identifies ", }, { col => 3, table => 3, text => "the bit position of the first error reported in the ", }, { col => 3, table => 3, text => "Uncorrectable Error Status register." }, { col => 0, table => 3, text => "ECRC_GEN_CAP (R)" }, { col => 1, table => 3, text => 5 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "This bit indicates that the device is capable of generating ", }, { col => 3, table => 3, text => "ECRC" }, { col => 0, table => 3, text => "ECRC_GEN_EN" }, { col => 1, table => 3, text => 6 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "This bit when set enables ECRC generation. Default value ", }, { col => 3, table => 3, text => "of this field is 0." }, { col => 0, table => 3, text => "ECRC_CHECK_CAP (R)" }, { col => 1, table => 3, text => 7 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "This bit indicates that the device is capable of checking ", }, { col => 3, table => 3, text => "ECRC" }, { col => 0, table => 3, text => "ECRC_CHECK_EN" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "This bit when set enables ECRC checking. Default value of ", }, { col => undef, table => undef, text => "this field is 0." }, { col => undef, table => undef, text => "Advanced Error Capabilities and Control Register", }, { col => "heading", table => 4, text => "PCIE_HDR_LOG0 - R - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x16C]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "TLP_HDR" }, { col => 1, table => 4, text => "31:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "TLP Header 1st DW" }, { col => undef, table => undef, text => "Header Log Register captures the Header for the TLP corresponding to a detected error;", }, ], }, { num => 94, text => [ { col => "heading", table => 0, text => "PCIE_HDR_LOG1 - R - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x170]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TLP_HDR" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "TLP Header 2nd DW" }, { col => undef, table => undef, text => "Header Log Register" }, { col => "heading", table => 1, text => "PCIE_HDR_LOG2 - R - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x174]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TLP_HDR" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "TLP Header 3rd DW" }, { col => undef, table => undef, text => "Header Log Register" }, { col => "heading", table => 2, text => "PCIE_HDR_LOG3 - R - 32 bits - [AudioPcie GpuF0Pcie,GpuF1Pcie:0x178]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TLP_HDR" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "TLP Header 4th DW" }, { col => undef, table => undef, text => "Header Log Register" }, ], }, { num => 95, text => [ { col => undef, table => undef, text => "2.4" }, { col => undef, table => undef, text => "Clock Generator Registers" }, { col => "heading", table => 0, text => "PLL_BYPASSCLK_SEL - RW - 32 bits - [GpuF0MMReg:0x608]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "SPLL_CLKOUT_SEL" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 1=VCLK-UPLL " }, { col => 3, table => 0, text => " 2=BCLK " }, { col => 3, table => 0, text => " 4=XTALIN " }, { col => 3, table => 0, text => " 8=PCLK " }, { col => 3, table => 0, text => " 16=MCLK Channel B/ TEST_MCLK " }, { col => 3, table => 0, text => " 32=MCLK CHANNEL C/TEST_MCLK " }, { col => 3, table => 0, text => " 64=TEST_SCLK " }, { col => 3, table => 0, text => " 128=SCAN_SCLK " }, { col => 0, table => 0, text => "MPLL_CLKOUT_SEL" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => " 1=VCLK-UPLL " }, { col => 3, table => 0, text => " 2=BCLK " }, { col => 3, table => 0, text => " 4=XTALIN " }, { col => 3, table => 0, text => " 8=PCLK " }, { col => 3, table => 0, text => " 16=TEST_MCLK " }, { col => 3, table => 0, text => " 32=SPLLOUT " }, { col => 3, table => 0, text => " 64=TEST_SCLK " }, { col => 3, table => 0, text => " 128=SCAN_MCLK " }, { col => "heading", table => 1, text => "SPLL_CNTL_MODE - RW - 32 bits - [GpuF0MMReg:0x60C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SPLL_SW_DIR_CONTROL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=SW controls the PLL directly. SW will make sure the ", }, { col => 3, table => 1, text => "way they program SPLL_FUNC_CNTL register follows the ", }, { col => 3, table => 1, text => "PLL's requested protocol " }, { col => 0, table => 1, text => "SPLL_REFCLK_SRC_SEL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Ref clock from GPIO " }, { col => 3, table => 1, text => " 1=Ref clock from XTALIN " }, { col => 0, table => 1, text => "SPLL_TEST" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable SPLL test mode " }, { col => 0, table => 1, text => "SPLL_FASTEN" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable SPLL fast lock " }, { col => 0, table => 1, text => "SPLL_ENSAT" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable saturation behavior " }, { col => 0, table => 1, text => "SPLL_DIV_SYNC" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable sync of the FB and RF dividers to the FBEN and ", }, { col => 3, table => 1, text => "RFEN clock from SPLL. This is needed if baby stepping ", }, { col => undef, table => undef, text => "option is used. " }, { col => undef, table => undef, text => " Software or HW control." }, { col => undef, table => undef, text => "MPLL_FUNC_CNTL - RW - 32 bits - [GpuF0MMReg:0x610]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "MPLL_RESET" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Run " }, { col => undef, table => undef, text => " 1=Reset " }, { col => undef, table => undef, text => "MPLL_SLEEP" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Power Up " }, { col => undef, table => undef, text => " 1=Power Down " }, { col => undef, table => undef, text => "MPLL_REF_DIV" }, { col => undef, table => undef, text => "4:2" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " Reference Divider DEF=0x1" }, { col => undef, table => undef, text => "MPLL_FB_DIV" }, { col => undef, table => undef, text => "12:5" }, { col => undef, table => undef, text => "0x6f" }, { col => undef, table => undef, text => " Feedback Divider DEF=111" }, { col => undef, table => undef, text => "MPLL_PULSEEN" }, { col => undef, table => undef, text => 13 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Don't pulse clock " }, { col => undef, table => undef, text => " 1=Send the numbre of pulses indicated by PULSENUM ", }, { col => undef, table => undef, text => "MPLL_PULSENUM" }, { col => undef, table => undef, text => "15:14" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " Number of pulses to be sent." }, { col => undef, table => undef, text => "MPLL_SW_HILEN" }, { col => undef, table => undef, text => "19:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " Post divider setting: No of high periods of CLKOP", }, { col => undef, table => undef, text => "MPLL_SW_LOLEN" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " Post divider setting: No of low periods of CLKOP", }, ], }, { num => 96, text => [ { col => 0, table => 0, text => "MPLL_DIVEN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Enable PLL CLKOUT divider " }, { col => 0, table => 0, text => "MPLL_BYPASS_EN" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 1=Enable Bypass mode " }, { col => 0, table => 0, text => "MPLL_MCLK_SEL" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Use MPLL output as mclk " }, { col => 0, table => 0, text => "MPLL_CHG_STATUS (R)" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Previous write/change to MPLL_FUNC_CNTL register ", }, { col => 3, table => 0, text => "has been completed. SW should not issue another write to ", }, { col => 3, table => 0, text => "this register until this bit is asserted ", }, { col => 0, table => 0, text => "MPLL_CTLREQ" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=For debug purpose: when SW_DIR_CONTROL is set, ", }, { col => 3, table => 0, text => "assert this bit will trigger an update of the PLL clock output ", }, { col => 3, table => 0, text => "mux control. Before write to this bit, " }, { col => 3, table => 0, text => "HILEN/LOLEN/PULSEEN/PULSENUM should already ", }, { col => 3, table => 0, text => "contain the new set of value " }, { col => 0, table => 0, text => "MPLL_CTLACK (R)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=For debug purpose: when SW_DIR_CONTROL is set, ", }, { col => 3, table => 0, text => "this value replicates the value of the CTLREQ once the ", }, { col => 3, table => 0, text => "command has been received and it is safe to send another ", }, { col => undef, table => undef, text => "request " }, { col => undef, table => undef, text => " MPLL function control register" }, { col => "heading", table => 1, text => "MPLL_CNTL_MODE - RW - 32 bits - [GpuF0MMReg:0x614]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MPLL_SW_DIR_CONTROL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=SW controls the PLL directly. SW will make sure the ", }, { col => 3, table => 1, text => "way they program MPLL_FUNC_CNTL register follows the ", }, { col => 3, table => 1, text => "PLL's requested protocol " }, { col => 0, table => 1, text => "MPLL_REFCLK_SRC_SEL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Ref clock from GPIO " }, { col => 3, table => 1, text => " 1=Ref clock from XTALIN " }, { col => 0, table => 1, text => "MPLL_TEST" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable MPLL test mode " }, { col => 0, table => 1, text => "MPLL_FASTEN" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable MPLL fast lock " }, { col => 0, table => 1, text => "MPLL_ENSAT" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x1" }, { col => undef, table => undef, text => " 1=Enable saturation behavior ", }, { col => undef, table => undef, text => " Software of HW control." }, { col => "heading", table => 2, text => "GENERAL_PWRMGT - RW - 32 bits - [GpuF0MMReg:0x618]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GLOBAL_PWRMGT_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=dynamic power managerment off " }, { col => 3, table => 2, text => " 1=dynamic power managerment on " }, { col => 0, table => 2, text => "STATIC_PM_EN" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "MOBILE_SU" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Regular " }, { col => 3, table => 2, text => " 1=Optimize power consumption in Suspend mode for ", }, { col => 3, table => 2, text => "mobile. D2 acts as if in D3 power state. ", }, { col => 0, table => 2, text => "THERMAL_PROTECTION_DIS" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=thermal protection Enabled " }, { col => 3, table => 2, text => " 1=thermal protection Disabled " }, { col => 0, table => 2, text => "THERMAL_PROTECTION_TYPE" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Normal protection - do not turn off gfx clock ", }, { col => 3, table => 2, text => " 1= Catastrophic thermal protection - turn off gfx clock ", }, { col => 0, table => 2, text => "ENABLE_GEN2PCIE" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disabled " }, { col => 3, table => 2, text => " 1=Enabled " }, { col => 0, table => 2, text => "SW_GPIO_INDEX" }, { col => 1, table => 2, text => "7:6" }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "LOW_VOLT_D2_ACPI" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Enable low voltage during D2 ACPI state ", }, { col => 0, table => 2, text => "LOW_VOLT_D3_ACPI" }, { col => 1, table => 2, text => 9 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Enable low voltage during D3 ACPI state ", }, { col => 0, table => 2, text => "VOLT_PWRMGT_EN" }, { col => 1, table => 2, text => 10 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Off " }, { col => 3, table => 2, text => " 1=Volt power management on " }, { col => 0, table => 2, text => "OPEN_DRAIN_PADS" }, { col => 1, table => 2, text => 11 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0= Resistor divider type " }, { col => 3, table => 2, text => " 1=Voltage control GPIO PADS are open drain type ", }, { col => 0, table => 2, text => "AVP_SCLK_EN" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn off sclk to AVP " }, { col => 3, table => 2, text => " 1=Turn ON sclk to AVP " }, { col => 0, table => 2, text => "IDCT_SCLK_EN" }, { col => 1, table => 2, text => 13 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => " 0=Turn off sclk to IDCT " }, { col => 3, table => 2, text => " 1=Turn ON sclk to IDCT " }, ], }, { num => 97, text => [ { col => 0, table => 0, text => "GPU_COUNTER_ACPI" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Enable counter in all states " }, { col => 3, table => 0, text => " 1=Stop gpu counter in D1, D2, D3-cold states ", }, { col => 0, table => 0, text => "GPU_COUNTER_CLK" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use 27Mhz crystal clock " }, { col => 3, table => 0, text => " 1=Use 27/2 = 13.5Mhz clock " }, { col => 0, table => 0, text => "BACKBIAS_PAD_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Pad enable for back bias " }, { col => 0, table => 0, text => "BACKBIAS_VALUE" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Back bias disabled in software control mode ", }, { col => 3, table => 0, text => " 1=Back bias enabled in software control mode ", }, { col => 0, table => 0, text => "BACKBIAS_DPM_CNTL" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Back bias software control " }, { col => 3, table => 0, text => " 1=Back bias DPM controlled " }, { col => 0, table => 0, text => "SPREAD_SPECTRUM_INDEX" }, { col => 1, table => 0, text => "20:19" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DYN_SPREAD_SPECTRUM_EN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Enable dynamic spread spectrum ctrl during DPM ", }, { col => 3, table => 0, text => "mode " }, { col => "heading", table => 1, text => "SCLK_PWRMGT_CNTL - RW - 32 bits - [GpuF0MMReg:0x620]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SCLK_PWRMGT_OFF" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=SCLK power managerment on " }, { col => 3, table => 1, text => " 1=SCLK power managerment off " }, { col => 0, table => 1, text => "SCLK_TURNOFF" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=NOT USED. sclk is always on " }, { col => 0, table => 1, text => "SPLL_TURNOFF" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable SPLL Power down during D3 stage, override ", }, { col => 3, table => 1, text => "HW pwrmgt control. " }, { col => 0, table => 1, text => "SU_SCLK_USE_BCLK" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Use slower SCLK under suspend mode ", }, { col => 3, table => 1, text => " 1=Use BCLK as SCLK under suspend mode ", }, { col => 0, table => 1, text => "DYNAMIC_GFX_ISLAND_PWR_DOWN" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0 0=Disable Power Down " }, { col => 3, table => 1, text => " 1=Enable Power Down " }, { col => 0, table => 1, text => "DYNAMIC_GFX_ISLAND_LP" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable Low Power, value retention mode ", }, { col => 3, table => 1, text => " 1=Enable Low Power " }, { col => 0, table => 1, text => "CLK_TURN_ON_STAGGER" }, { col => 1, table => 1, text => 6 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable clock stagger while turning ON clocks ", }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "CLK_TURN_OFF_STAGGER" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 0=Disable clock stagger while turning OFF clocks ", }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "FIR_FORCE_TREND_SEL" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Force Trend select " }, { col => 0, table => 1, text => "FIR_TREND_MODE" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Select UpTrend " }, { col => 3, table => 1, text => " 1=Select DownTrend " }, { col => 0, table => 1, text => "DYN_GFX_CLK_OFF_EN" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable gfx clock to go be turned OFF during dynamic ", }, { col => 3, table => 1, text => "pwr mgmnt " }, { col => 0, table => 1, text => "VDDC3D_TURNOFF_D1" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable GFX sclk to be turned off during D1 state ", }, { col => 0, table => 1, text => "VDDC3D_TURNOFF_D2" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable GFX sclk to be turned off during D2 state ", }, { col => 0, table => 1, text => "VDDC3D_TURNOFF_D3" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable GFX sclk to be turned off during D3 state ", }, { col => 0, table => 1, text => "SPLL_TURNOFF_D2" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable SPLL Power down during D2 stage ", }, { col => 0, table => 1, text => "SCLK_LOW_D1" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 1=Enable SCLK to low state during D1 ", }, { col => 0, table => 1, text => "DYN_GFX_CLK_OFF_MC_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => " 1=Enable gfx clock to be turned OFF for mc tiles during ", }, { col => undef, table => undef, text => "dynamic pwr mgt " }, { col => undef, table => undef, text => "SCLK domain static power managerment", }, { col => "heading", table => 2, text => "MCLK_PWRMGT_CNTL - RW - 32 bits - [GpuF0MMReg:0x624]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MPLL_PWRMGT_OFF" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=MCLK power managerment on during ACPI ", }, { col => 3, table => 2, text => " 1=MCLK power managerment off during ACPI ", }, { col => 0, table => 2, text => "YCLK_TURNOFF" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Turn off YCLK during D2/D3 state " }, { col => 0, table => 2, text => "MPLL_TURNOFF" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Enable M domain PLL to be turned off at power state ", }, { col => 3, table => 2, text => "D3 " }, { col => 0, table => 2, text => "SU_MCLK_USE_BCLK" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Shut down MCLK during suspend mode ", }, { col => 3, table => 2, text => " 1=Use BCLK as MCLK under suspend mode ", }, ], }, { num => 98, text => [ { col => undef, table => undef, text => "DLL_READY" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=DLL is not ready. Status from Software ", }, { col => undef, table => undef, text => " 1=DLL is ready " }, { col => undef, table => undef, text => "MC_BUSY (R)" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=MC is idle " }, { col => undef, table => undef, text => " 1=MC is not idle " }, { col => undef, table => undef, text => "SPARE" }, { col => undef, table => undef, text => 6 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=SPARE " }, { col => undef, table => undef, text => "MC_INT_CNTL" }, { col => undef, table => undef, text => 7 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=SW overwrite - Control the DLL lines through software, ", }, { col => undef, table => undef, text => "if HW control doesnt work " }, { col => undef, table => undef, text => " 1=HW control " }, { col => undef, table => undef, text => "MRDCKA_SLEEP" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel A DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel A DLL " }, { col => undef, table => undef, text => "MRDCKB_SLEEP" }, { col => undef, table => undef, text => 9 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel B DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel B DLL " }, { col => undef, table => undef, text => "MRDCKC_SLEEP" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel C DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel C DLL " }, { col => undef, table => undef, text => "MRDCKD_SLEEP" }, { col => undef, table => undef, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel D DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel D DLL " }, { col => undef, table => undef, text => "MRDCKE_SLEEP" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel E DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel E DLL " }, { col => undef, table => undef, text => "MRDCKF_SLEEP" }, { col => undef, table => undef, text => 13 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel F DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel F DLL " }, { col => undef, table => undef, text => "MRDCKG_SLEEP" }, { col => undef, table => undef, text => 14 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel G DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel G DLL " }, { col => undef, table => undef, text => "MRDCKH_SLEEP" }, { col => undef, table => undef, text => 15 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable Channel H DLL " }, { col => undef, table => undef, text => " 1=PowerDown Channel H DLL " }, { col => undef, table => undef, text => "MRDCKA_RESET" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel A DLL " }, { col => undef, table => undef, text => " 1=Reset Channel A DLL " }, { col => undef, table => undef, text => "MRDCKB_RESET" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel B DLL " }, { col => undef, table => undef, text => " 1=Reset Channel B DLL " }, { col => undef, table => undef, text => "MRDCKC_RESET" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel C DLL " }, { col => undef, table => undef, text => " 1=Reset Channel C DLL " }, { col => undef, table => undef, text => "MRDCKD_RESET" }, { col => undef, table => undef, text => 19 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel D DLL " }, { col => undef, table => undef, text => " 1=Reset Channel D DLL " }, { col => undef, table => undef, text => "MRDCKE_RESET" }, { col => undef, table => undef, text => 20 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel E DLL " }, { col => undef, table => undef, text => " 1=Reset Channel E DLL " }, { col => undef, table => undef, text => "MRDCKF_RESET" }, { col => undef, table => undef, text => 21 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel F DLL " }, { col => undef, table => undef, text => " 1=Reset Channel F DLL " }, { col => undef, table => undef, text => "MRDCKG_RESET" }, { col => undef, table => undef, text => 22 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel G DLL " }, { col => undef, table => undef, text => " 1=Reset Channel G DLL " }, { col => undef, table => undef, text => "MRDCKH_RESET" }, { col => undef, table => undef, text => 23 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Enable Channel H DLL " }, { col => undef, table => undef, text => " 1=Reset Channel H DLL " }, { col => undef, table => undef, text => "DLL_READY_READ (R)" }, { col => undef, table => undef, text => 24 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=DLL is not ready - status from CG ", }, { col => undef, table => undef, text => " 1=DLL is ready " }, { col => undef, table => undef, text => "USE_DISPLAY_GAP" }, { col => undef, table => undef, text => 25 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 0=Not followed " }, { col => undef, table => undef, text => " 1=Display Gap interface followed ", }, { col => undef, table => undef, text => "USE_DISP_URGENT_NORMAL" }, { col => undef, table => undef, text => 26 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 1=Use CG_MC_display_urgent during normal mclk ", }, { col => undef, table => undef, text => "switching " }, { col => undef, table => undef, text => "USE_DISPLAY_GAP_CTXSW" }, { col => undef, table => undef, text => 27 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 1=During context switch use display gap ", }, { col => undef, table => undef, text => "MPLL_TURNOFF_D2" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Enable M domain PLL to be turned off at power state ", }, { col => undef, table => undef, text => "D2 " }, { col => undef, table => undef, text => "USE_DISP_URGENT_CTXSW" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => " 1=Use CG_MC_display_urgent during ctxsw mclk ", }, { col => undef, table => undef, text => "switching " }, { col => "heading", table => 0, text => "DLL_CNTL - RW - 32 bits - [GpuF0MMReg:0x62C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DLL_RESET_TIME" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x1f4" }, { col => 3, table => 0, text => " DEF=500" }, { col => 0, table => 0, text => "DLL_LOCK_TIME" }, { col => 1, table => 0, text => "21:12" }, { col => 2, table => 0, text => "0xfa" }, { col => 3, table => 0, text => " DEF=250" }, { col => 0, table => 0, text => "MRDCKA_BYPASS" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel A DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel A DLL " }, ], }, { num => 99, text => [ { col => 0, table => 0, text => "MRDCKB_BYPASS" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel B DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel B DLL " }, { col => 0, table => 0, text => "MRDCKC_BYPASS" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel C DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel C DLL " }, { col => 0, table => 0, text => "MRDCKD_BYPASS" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel D DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel D DLL " }, { col => 0, table => 0, text => "MRDCKE_BYPASS" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel E DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel E DLL " }, { col => 0, table => 0, text => "MRDCKF_BYPASS" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel F DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel F DLL " }, { col => 0, table => 0, text => "MRDCKG_BYPASS" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel G DLL " }, { col => 3, table => 0, text => " 1=Disable Bypass Channel G DLL " }, { col => 0, table => 0, text => "MRDCKH_BYPASS" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable Bypass Channel H DLL " }, { col => undef, table => undef, text => " 1=Disable Bypass Channel H DLL ", }, { col => undef, table => undef, text => "DLL control register" }, { col => "heading", table => 1, text => "SPLL_TIME - RW - 32 bits - [GpuF0MMReg:0x630]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SPLL_LOCK_TIME" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x2000" }, { col => 3, table => 1, text => " DEF=0x2000" }, { col => 0, table => 1, text => "SPLL_RESET_TIME" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x1f4" }, { col => undef, table => undef, text => " DEF=500" }, { col => undef, table => undef, text => "SPLL related timing counter" }, { col => "heading", table => 2, text => "MPLL_TIME - RW - 32 bits - [GpuF0MMReg:0x634]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MPLL_LOCK_TIME" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x2000" }, { col => 0, table => 2, text => "MPLL_RESET_TIME" }, { col => 1, table => 2, text => "31:16" }, { col => undef, table => undef, text => "0x1f4" }, { col => undef, table => undef, text => "MPLL related timing counter" }, { col => "heading", table => 3, text => "ERROR_STATUS - R - 32 bits - [GpuF0MMReg:0x640]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "OVERCLOCK_DETECTION_SCLK" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=No overclock for SCLK " }, { col => 3, table => 3, text => " 1=SCLK overclock " }, { col => 0, table => 3, text => "OVERCLOCK_DETECTION_YCLK" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=No overclock for YCLK " }, { col => 3, table => 3, text => " 1=YCLK overclock " }, { col => 0, table => 3, text => "SPLL_UNLOCK" }, { col => 1, table => 3, text => 2 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "YPLL_UNLOCK" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "YPLL2_UNLOCK" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "UPLL_UNLOCK" }, { col => 1, table => 3, text => 5 }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "ACPI_STATE" }, { col => 1, table => 3, text => "8:6" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "MCHG_STATE" }, { col => 1, table => 3, text => "11:9" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "FCHANGE_STATE" }, { col => 1, table => 3, text => "15:12" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "DPM_STATE" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SCHANGE_STATE" }, { col => 1, table => 3, text => "22:20" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SPLL_DIVEN_STATE" }, { col => 1, table => 3, text => "24:23" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "VCHG_STAGE" }, { col => 1, table => 3, text => "26:25" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "SPLL_SW_FSM_STATE" }, { col => 1, table => 3, text => "29:27" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CG related error status, any reads to this register will clean the status.", }, ], }, { num => 100, text => [ { col => "heading", table => 0, text => "CG_CLKPIN_CNTL - RW - 32 bits - [GpuF0MMReg:0x644]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "OSC_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Disable Oscillation " }, { col => 3, table => 0, text => " 1=Enable Oscillation " }, { col => 0, table => 0, text => "XTL_LOW_GAIN" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=High Gain " }, { col => 3, table => 0, text => " 1=Low Gain " }, { col => 0, table => 0, text => "CG_CLK_TO_OUTPIN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disabled " }, { col => 3, table => 0, text => " 1=Send out selected clock for jitter test ", }, { col => 0, table => 0, text => "OSC_USE_CORE" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Pad routing OSC " }, { col => 3, table => 0, text => " 1=Core routing OSC " }, { col => 0, table => 0, text => "TEST_MCLK_RE" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Receiver Enable for TEST_MCLK pad " }, { col => 0, table => 0, text => "TEST_YCLK_RE" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Receiver Enable for TEST_YCLK pad " }, { col => 0, table => 0, text => "GENERICA_OE" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Enable selected clock to be observed through ", }, { col => 3, table => 0, text => "GENERICA pad " }, { col => 0, table => 0, text => "MUX_TCLK_TO_XCLK" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 1=Mux free running tclk into xclk " }, { col => "heading", table => 1, text => "PLL_TEST_CNTL - RW - 32 bits - [GpuF0MMReg:0x79C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TST_SRC_SEL" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "TST_REF_SEL" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "REF_TEST_COUNT" }, { col => 1, table => 1, text => "14:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "TST_RESET" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "TEST_COUNT (R)" }, { col => 1, table => 1, text => "31:17" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => " FIX=0" }, { col => undef, table => undef, text => "PLL frequency measurement control", }, { col => "heading", table => 2, text => "CG_TC_JTAG_0 - RW - 32 bits - [GpuF0MMReg:0x7A0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CG_TC_TMS" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " DEF = 0x0" }, { col => 3, table => 2, text => "8 consecutive values for TMS. Bit 0 is sent first.", }, { col => 0, table => 2, text => "CG_TC_TDI" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " DEF = 0x0" }, { col => 3, table => 2, text => "8 consecutive values for TDI. Bit 0 is sent first.", }, { col => 0, table => 2, text => "CG_TC_MODE" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disabled " }, { col => 3, table => 2, text => " 1=CG JTAG mode Enabled " }, { col => 3, table => 2, text => "Indicates what clock should be used for TCK in the JTAG ", }, { col => 3, table => 2, text => "transactions." }, { col => 0, table => 2, text => "CG_TC_TDO_MASK" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "DEF = 0x0" }, { col => 3, table => 2, text => "A mask indicating whether the TDO value should be read ", }, { col => 3, table => 2, text => "back for a given JTAG cycle. Bit 0 corresponds to the first ", }, { col => 3, table => 2, text => "TDO sample. This mask can be used to prevent the ", }, { col => 3, table => 2, text => "readback of unknown values across the bus interface ", }, { col => 3, table => 2, text => "during simulation. This field can be set to all 1's on real ", }, { col => 3, table => 2, text => "hardware." }, { col => undef, table => undef, text => "TAG " }, { col => undef, table => undef, text => "port. These 8 inputs are sent at consecutive TCK clock edges. The final value is held for indefinitely many TCK clock edges until the next write to ", }, { col => undef, table => undef, text => "this register. The register can be used to walk through several states of the JTAG state machine and typically the state machine would be left in ", }, { col => undef, table => undef, text => "a 'paused' state. The TDO values sampled at the 8 edges for which input was provided is available for readback from the TC_CG_TDO field of ", }, { col => undef, table => undef, text => "the CG_TC_JTAG_1 register." }, ], }, { num => 101, text => [ { col => "heading", table => 0, text => "CG_TC_JTAG_1 - R - 32 bits - [GpuF0MMReg:0x7A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TC_CG_TDO" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "8 consecutive sampled values of TDO. Bit 0 corresponds to ", }, { col => 3, table => 0, text => "the cycle that the first bit of CG_TC_JTAG_0.CG_TC_TMS ", }, { col => 3, table => 0, text => "and" }, { col => 3, table => 0, text => "CG_TC_JTAG_0.CG_TC_TDI were sampled by the Test ", }, { col => 3, table => 0, text => "Controller." }, { col => 0, table => 0, text => "TC_CG_DONE" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=We have completed less than 8 JTAG cycles since the ", }, { col => 3, table => 0, text => "last write to CG_TC_JTAG_0 " }, { col => 3, table => 0, text => " 1=All 8 JTAG cycles have been completed since the last ", }, { col => 3, table => 0, text => "write to CG_TC_JTAG_0 " }, { col => 3, table => 0, text => "Indicates whether the JTAG sequence has completed.", }, { col => undef, table => undef, text => "TDO readback and status bits for the CG JTAG interface described in more detail in the CG_TC_JTAG_0 register description.", }, { col => "heading", table => 1, text => "CG_MISC_REG - RW - 32 bits - [GpuF0MMReg:0x7C8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SYNCHRONIZER_COUNTER" }, { col => 1, table => 1, text => "31:28" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " delay for restarting the clock while switching from one clock ", }, { col => undef, table => undef, text => "to another" }, { col => undef, table => undef, text => " Miscellaneous Register" }, ], }, { num => 102, text => [ { col => undef, table => undef, text => "2.5" }, { col => undef, table => undef, text => "VIP/I2C Registers" }, { col => undef, table => undef, text => "2.5.1" }, { col => undef, table => undef, text => "I2C Registers" }, { col => "heading", table => 0, text => "I2C_CNTL_0 - RW - 32 bits - [GpuF0MMReg:0xBC0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "I2C_DONE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. Indicate whether current I2C request is finished ", }, { col => 3, table => 0, text => "or not" }, { col => 3, table => 0, text => " 0=I2c is busy " }, { col => 3, table => 0, text => " 1=transfer is complete " }, { col => 0, table => 0, text => "I2C_NACK" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. Status bit indicate whether I2C slave did not ", }, { col => 3, table => 0, text => "acknowledge." }, { col => 3, table => 0, text => " 1=Slave did not issue acknowledge " }, { col => 0, table => 0, text => "I2C_HALT" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Read only. Status bit indicate where I2C bus transfer is ", }, { col => 3, table => 0, text => "time out." }, { col => 3, table => 0, text => " 1=Time-out condition, transfer is halted ", }, { col => 0, table => 0, text => "I2C_SOFT_RST" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Software reset I2C interface block" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Resets i2c controller " }, { col => 0, table => 0, text => "I2C_DRIVE_EN" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable I2C pad driving pull-up action" }, { col => 3, table => 0, text => " 0=Pullup by external resistor " }, { col => 3, table => 0, text => " 1=I2C pads drive SDA " }, { col => 0, table => 0, text => "I2C_DRIVE_SEL" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "If DRIVE_EN is HIGH, select drive time" }, { col => 3, table => 0, text => " 0=Drive for 10MCLKs " }, { col => 3, table => 0, text => " 1=20MCLKS " }, { col => 0, table => 0, text => "I2C_START" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicate whether use the start condition in I2C protocol.", }, { col => 3, table => 0, text => " 0=No start " }, { col => 3, table => 0, text => " 1=Start " }, { col => 0, table => 0, text => "I2C_STOP" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicate whether use the stop condition in I2C protocol.", }, { col => 3, table => 0, text => " 0=No stop " }, { col => 3, table => 0, text => " 1=Stop " }, { col => 0, table => 0, text => "I2C_RECEIVE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Master receive/transmit mode selection" }, { col => 3, table => 0, text => " 0=Send " }, { col => 3, table => 0, text => " 1=Receive " }, { col => 0, table => 0, text => "I2C_ABORT" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "If 1, abort the current I2C operation by sending STOP bit.", }, { col => 3, table => 0, text => " 0=No abort " }, { col => 3, table => 0, text => " 1=Abort " }, { col => 0, table => 0, text => "I2C_GO" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write this bit initiate I2C operation. Read this bit indicate the ", }, { col => 3, table => 0, text => "I2C operation is finished or not." }, { col => 0, table => 0, text => "I2C_PRESCALE" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "I2C clock divider to generate I2C SCL output. It also ", }, { col => undef, table => undef, text => "indirectly control the sampling rate.", }, { col => undef, table => undef, text => "I2C control registers" }, { col => "heading", table => 1, text => "I2C_CNTL_1 - RW - 32 bits - [GpuF0MMReg:0xBC4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "I2C_DATA_COUNT" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte count for data to be transferred through I2C interface. ", }, { col => 3, table => 1, text => "The data should be in the 16 bytes I2C buffer", }, { col => 0, table => 1, text => "I2C_ADDR_COUNT" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte count for I2C addresses. Maximum 3 bytes of address ", }, { col => 3, table => 1, text => "can be transferred." }, { col => 0, table => 1, text => "I2C_INTRA_BYTE_DELAY" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "I2C_SEL" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Not used in Rage5" }, { col => 3, table => 1, text => " 0=Pullup by external resistor " }, { col => 3, table => 1, text => " 1=I2C pads drive SCL " }, { col => 0, table => 1, text => "I2C_EN" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable I2C" }, { col => 0, table => 1, text => "I2C_TIME_LIMIT" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Time out limit. Total wait time = TIME_LIMIT * 4 * ", }, { col => 3, table => 1, text => "PRESCLAE(15:8) cycles for SCL to be LOW" }, ], }, { num => 103, text => [ { col => undef, table => undef, text => "I2C control registers" }, { col => undef, table => undef, text => "I2C_DATA - RW - 32 bits - [GpuF0MMReg:0xBC8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "I2C_DATA" }, { col => undef, table => undef, text => "7:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "I2C data interface. Programmers use this 8bits interface to ", }, { col => undef, table => undef, text => "write and read I2C bus data." }, { col => undef, table => undef, text => "I2C data registers. Programmers use this 8bits interface to write and read I2C bus data.", }, { col => "heading", table => 0, text => "DC_I2C_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D30]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_GO (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write 1 to start I2C transfer." }, { col => 0, table => 0, text => "DC_I2C_SOFT_RESET" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write 1 to reset I2C controller" }, { col => 0, table => 0, text => "DC_I2C_SEND_RESET" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to send reset sequence (9 clocks with no data) at ", }, { col => 3, table => 0, text => "start of transfer. This sequence is sent after DC_I2C_GO is ", }, { col => 3, table => 0, text => "written to 1, before the first transaction only.", }, { col => 0, table => 0, text => "DC_I2C_SW_STATUS_RESET" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write 1 to reset DC_I2C_SW_STATUS flags, will reset ", }, { col => 3, table => 0, text => "SW_DONE, ABORTED, TIMEOUT, SW_INTERRUPTED, ", }, { col => 3, table => 0, text => "BUFFER_OVERFLOW, STOPPED_ON_NACK, NACK0, ", }, { col => 3, table => 0, text => "NACK1, NACK2, NACK3" }, { col => 0, table => 0, text => "DC_I2C_SDVO_EN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to send two transactions to configure SDVO bus for ", }, { col => 3, table => 0, text => "DDC before main transaction." }, { col => 3, table => 0, text => "The SDVO transaction is as follows:" }, { col => 3, table => 0, text => " S-AAw-a-07-a-02-a-P-S-AAw-a-08-a-7A-a-P", }, { col => 3, table => 0, text => " where AA is the address and is selected by ", }, { col => 3, table => 0, text => "DC_I2C_SDVO_ADDR_SEL." }, { col => 3, table => 0, text => "The SDVO transactions take place after the RESET ", }, { col => 3, table => 0, text => "transaction (if enabled) and before the remaining ", }, { col => 3, table => 0, text => "transactions." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DC_I2C_SDVO_ADDR_SEL" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to select address for SDVO I2C bus configuration", }, { col => 3, table => 0, text => " 0=0x70 " }, { col => 3, table => 0, text => " 1=0x72 " }, { col => 0, table => 0, text => "DC_I2C_DDC_SELECT" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select DDC pins set, dddc1, ddc2, ddc3" }, { col => 3, table => 0, text => " 0=0 = DDC1 " }, { col => 3, table => 0, text => " 1=1 = DDC2 " }, { col => 3, table => 0, text => " 2=2 = DDC3 " }, { col => 3, table => 0, text => " 3=3-7 = Reserved " }, { col => 0, table => 0, text => "DC_I2C_TRANSACTION_COUNT" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of transactions to be done in current transfer.", }, { col => 3, table => 0, text => " 0=transaction0 only " }, { col => 3, table => 0, text => " 1=transaction0, transaction1 " }, { col => 3, table => 0, text => " 2=transaction0, transaction1, transaction2 ", }, { col => 3, table => 0, text => " 3=transaction0, transaction1, transaction2, transaction3 ", }, { col => 3, table => 0, text => "(DC_I2C_REPEAT=0 only) " }, ], }, { num => 104, text => [ { col => undef, table => undef, text => "DC_I2C_ARBITRATION - RW - 32 bits - [GpuF0MMReg:0x7D34]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DC_I2C_SW_PRIORITY" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Sets priority for software I2C requests. This setting applies ", }, { col => undef, table => undef, text => "only when HDCP is using I2C bus and software also wants ", }, { col => undef, table => undef, text => "to use the same I2C bus" }, { col => undef, table => undef, text => " 0=Normal - If DC_I2C_NO_QUEUED_SW_GO = 0, ", }, { col => undef, table => undef, text => "software I2C transaction will be queued after HW I2C. If ", }, { col => undef, table => undef, text => "DC_I2C_NO_QUEUED_SW_GO = 1, software I2C ", }, { col => undef, table => undef, text => "transaction is not queued, in this case, software have to poll ", }, { col => undef, table => undef, text => "for DC_I2C_DDCx_HW_DONE doing any I2C transaction ", }, { col => undef, table => undef, text => " 1=High - Software always interrupts HW I2C if HDCP is ", }, { col => undef, table => undef, text => "using the same I2C bus, HW I2C will automatically resume ", }, { col => undef, table => undef, text => "once software I2C is completed " }, { col => undef, table => undef, text => " 2=Reserved " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "DC_I2C_NO_QUEUED_SW_GO" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to disable queuing of software I2C GO. If this bit is ", }, { col => undef, table => undef, text => "set, then if software writes DC_I2C_GO while I2C is in use ", }, { col => undef, table => undef, text => "by hardware, the GO request will be ignored and the ", }, { col => undef, table => undef, text => "DC_I2C_SW_INTERRUPTED bit set." }, { col => undef, table => undef, text => "DC_I2C_NO_RESTART_SW_GO" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to disable restart of software I2C transaction that ", }, { col => undef, table => undef, text => "was interrupted by hardware. Typically this bit should be 0, ", }, { col => undef, table => undef, text => "unless there is a problem with the I2C restart mechanism. ", }, { col => undef, table => undef, text => "When this bit is set to 0, the DC_I2C_SW_DONE bit will not ", }, { col => undef, table => undef, text => "be set if hardware interrupts the software transfer.", }, { col => undef, table => undef, text => "DC_I2C_ABORT_HW_XFER (W)" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Write 1 to abort current HW transfer (send stop if transfer ", }, { col => undef, table => undef, text => "has started)" }, { col => undef, table => undef, text => "DC_I2C_ABORT_SW_XFER (W)" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Write 1 to abort current SW transfer (send stop if transfer ", }, { col => undef, table => undef, text => "has started)" }, { col => undef, table => undef, text => "Configure arbitration between hardware and software use of the DC_I2C engine", }, { col => "heading", table => 0, text => "DC_I2C_INTERRUPT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D38]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_SW_DONE_INT (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "SW_DONE interrupt status" }, { col => 0, table => 0, text => "DC_I2C_SW_DONE_ACK (W)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Acknowledge bit for DC_I2C_SW_DONE_INT. Write 1 to ", }, { col => 3, table => 0, text => "clear interrupt." }, { col => 0, table => 0, text => "DC_I2C_SW_DONE_MASK" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Mask bit for DC_I2C_SW_DONE_INT. Set to 1 to enable ", }, { col => 3, table => 0, text => "interrupt." }, { col => 0, table => 0, text => "DC_I2C_DDC1_HW_DONE_INT (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC1 HW_DONE interrupt status" }, { col => 0, table => 0, text => "DC_I2C_DDC1_HW_DONE_ACK (W)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC1 Acknowledge bit for " }, { col => 3, table => 0, text => "DC_I2C_HW_DDC1_DONE_INT. Write 1 to clear interrupt.", }, { col => 0, table => 0, text => "DC_I2C_DDC1_HW_DONE_MASK" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC1 Mask bit for DC_I2C_HW_DDC1_DONE_INT. Set ", }, { col => 3, table => 0, text => "to 1 to enable interrupt." }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_DONE_INT (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC2 HW_DONE interrupt status" }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_DONE_ACK (W)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC2 Acknowledge bit for " }, { col => 3, table => 0, text => "DC_I2C_HW_DDC2_DONE_INT. Write 1 to clear interrupt.", }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_DONE_MASK" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC2 Mask bit for DC_I2C_HW_DDC2_DONE_INT. Set ", }, { col => 3, table => 0, text => "to 1 to enable interrupt." }, { col => 0, table => 0, text => "DC_I2C_DDC3_HW_DONE_INT (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC3 HW_DONE interrupt status" }, { col => 0, table => 0, text => "DC_I2C_DDC3_HW_DONE_ACK (W)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC3 Acknowledge bit for " }, { col => 3, table => 0, text => "DC_I2C_HW_DDC3_DONE_INT. Write 1 to clear interrupt.", }, { col => 0, table => 0, text => "DC_I2C_DDC3_HW_DONE_MASK" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DDC3 Mask bit for DC_I2C_HW_DDC3_DONE_INT. Set ", }, { col => 3, table => 0, text => "to 1 to enable interrupt." }, { col => 0, table => 0, text => "DC_I2C_DDC4_HW_DONE_INT (R)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DC_I2C_DDC4_HW_DONE_ACK (W)" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DC_I2C_DDC4_HW_DONE_MASK" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, ], }, { num => 105, text => [ { col => "heading", table => 0, text => "DC_I2C_SW_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D3C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_SW_STATUS (R)" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Current SW status of DC_I2C" }, { col => 3, table => 0, text => " 0=Idle " }, { col => 3, table => 0, text => " 1=In use by SW " }, { col => 3, table => 0, text => " 2=In use by HW " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "DC_I2C_SW_DONE (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set on completion of SW transfer. Cleared by writing ", }, { col => 3, table => 0, text => "DC_I2C_SW_DONE_ACK to 1" }, { col => 0, table => 0, text => "DC_I2C_SW_ABORTED (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that abort request ccurred during SW transfer, ", }, { col => 3, table => 0, text => "stopping transfer. Cleared on GO." }, { col => 0, table => 0, text => "DC_I2C_SW_TIMEOUT (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that timeout condition occurred during SW ", }, { col => 3, table => 0, text => "transfer, stopping transfer. Cleared on GO.", }, { col => 0, table => 0, text => "DC_I2C_SW_INTERRUPTED (R)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that SW transfer was interrupted by hardware ", }, { col => 3, table => 0, text => "request. Cleared on GO." }, { col => 0, table => 0, text => "DC_I2C_SW_BUFFER_OVERFLOW (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that buffer overflow occurred during SW transfer, ", }, { col => 3, table => 0, text => "stopping transfer. Cleared on GO." }, { col => 0, table => 0, text => "DC_I2C_SW_STOPPED_ON_NACK (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that SW transfer was interrpted due to NACK ", }, { col => 3, table => 0, text => "when STOP_ON_NACK=1. Cleared on GO." }, { col => 0, table => 0, text => "DC_I2C_SW_SDVO_NACK (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "DC_I2C_SW_NACK0 (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that I2C slave did not issue an acknowledge ", }, { col => 3, table => 0, text => "during the first SW transaction. Cleared on GO.", }, { col => 0, table => 0, text => "DC_I2C_SW_NACK1 (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that I2C slave did not issue an acknowledge ", }, { col => 3, table => 0, text => "during the second SW transaction. Cleared on GO.", }, { col => 0, table => 0, text => "DC_I2C_SW_NACK2 (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that I2C slave did not issue an acknowledge ", }, { col => 3, table => 0, text => "during the third SW transaction. Cleared on GO.", }, { col => 0, table => 0, text => "DC_I2C_SW_NACK3 (R)" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that I2C slave did not issue an acknowledge ", }, { col => 3, table => 0, text => "during the fourth SW transaction. Cleared on GO.", }, { col => 0, table => 0, text => "DC_I2C_SW_REQ (R)" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Software requests use of DC_I2C interface (indicates that ", }, { col => 3, table => 0, text => "request is pending - i.e. queued). Cleared when request ", }, { col => undef, table => undef, text => "becomes active or by DC_I2C_ABORT_SW_XFER.", }, { col => undef, table => undef, text => "Status fields for DC_I2C engine" }, { col => "heading", table => 1, text => "DC_I2C_DDC1_HW_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D40]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DDC1_HW_STATUS (R)" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Current HW status of DC_I2C" }, { col => 3, table => 1, text => " 0=Idle " }, { col => 3, table => 1, text => " 1=In use by SW " }, { col => 3, table => 1, text => " 2=In use by HW " }, { col => 3, table => 1, text => " 3=Reserved " }, { col => 0, table => 1, text => "DC_I2C_DDC1_HW_DONE (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set on completion of HW transfer. Cleared by writing ", }, { col => 3, table => 1, text => "DC_I2C_HW_DONE_ACK to 1" }, { col => 0, table => 1, text => "DC_I2C_DDC1_HW_REQ (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Hardware requests use of DC_I2C interface (indicates that ", }, { col => 3, table => 1, text => "request is pending - i.e. queued). Cleared when request ", }, { col => 3, table => 1, text => "becomes active or by DC_I2C_ABORT_HW_XFER.", }, { col => 0, table => 1, text => "DC_I2C_DDC1_HW_URG (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Indicates that hardware I2C request is urgent (used by ", }, { col => undef, table => undef, text => "arbitration logic)." }, { col => undef, table => undef, text => "Status fields for DC_I2C engine" }, ], }, { num => 106, text => [ { col => "heading", table => 0, text => "DC_I2C_DDC2_HW_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D44]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_STATUS (R)" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Current HW status of DC_I2C" }, { col => 3, table => 0, text => " 0=Idle " }, { col => 3, table => 0, text => " 1=In use by SW " }, { col => 3, table => 0, text => " 2=In use by HW " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_DONE (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set on completion of HW transfer. Cleared by writing ", }, { col => 3, table => 0, text => "DC_I2C_HW_DONE_ACK to 1" }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_REQ (R)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Hardware requests use of DC_I2C interface (indicates that ", }, { col => 3, table => 0, text => "request is pending - i.e. queued). Cleared when request ", }, { col => 3, table => 0, text => "becomes active or by DC_I2C_ABORT_HW_XFER.", }, { col => 0, table => 0, text => "DC_I2C_DDC2_HW_URG (R)" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that hardware I2C request is urgent (used by ", }, { col => undef, table => undef, text => "arbitration logic)." }, { col => undef, table => undef, text => "Status fields for DC_I2C engine" }, { col => "heading", table => 1, text => "DC_I2C_DDC3_HW_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D48]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DDC3_HW_STATUS (R)" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Current HW status of DC_I2C" }, { col => 3, table => 1, text => " 0=Idle " }, { col => 3, table => 1, text => " 1=In use by SW " }, { col => 3, table => 1, text => " 2=In use by HW " }, { col => 3, table => 1, text => " 3=Reserved " }, { col => 0, table => 1, text => "DC_I2C_DDC3_HW_DONE (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set on completion of HW transfer. Cleared by writing ", }, { col => 3, table => 1, text => "DC_I2C_HW_DONE_ACK to 1" }, { col => 0, table => 1, text => "DC_I2C_DDC3_HW_REQ (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Hardware requests use of DC_I2C interface (indicates that ", }, { col => 3, table => 1, text => "request is pending - i.e. queued). Cleared when request ", }, { col => 3, table => 1, text => "becomes active or by DC_I2C_ABORT_HW_XFER.", }, { col => 0, table => 1, text => "DC_I2C_DDC3_HW_URG (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Indicates that hardware I2C request is urgent (used by ", }, { col => undef, table => undef, text => "arbitration logic)." }, { col => undef, table => undef, text => "Status fields for DC_I2C engine" }, { col => "heading", table => 2, text => "DC_I2C_DDC1_SPEED - RW - 32 bits - [GpuF0MMReg:0x7D4C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_I2C_DDC1_THRESHOLD" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => "Select threshold to use to determine whether value ", }, { col => 3, table => 2, text => "sampled on SDA is a 1 or 0. Specified in terms of the ratio ", }, { col => 3, table => 2, text => "between the number of sampled ones and the total number ", }, { col => 3, table => 2, text => "of times SDA is sampled." }, { col => 3, table => 2, text => " 0=>0 " }, { col => 3, table => 2, text => " 1=1/4 of total samples " }, { col => 3, table => 2, text => " 2=1/2 of total samples " }, { col => 3, table => 2, text => " 3=3/4 of total samples " }, { col => 0, table => 2, text => "DC_I2C_DDC1_PRESCALE" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "prescale = (m * xtal_frequency) / (desired_i2c_speed), ", }, { col => undef, table => undef, text => "where m is multiply factor, default: m = 1", }, { col => undef, table => undef, text => "DDC1 speed setting" }, { col => undef, table => undef, text => "DC_I2C_DDC1_SETUP - RW - 32 bits - [GpuF0MMReg:0x7D50]", }, ], }, { num => 107, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_DDC1_DATA_DRIVE_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select whether SDA pad is pulled up or driven high", }, { col => 3, table => 0, text => "0:Pullup by external resistor" }, { col => 3, table => 0, text => "1:I2C pads drive SDA high" }, { col => 3, table => 0, text => " 0=Pullup by external resistor " }, { col => 3, table => 0, text => " 1=I2C pads drive SDA " }, { col => 0, table => 0, text => "DC_I2C_DDC1_DATA_DRIVE_SEL" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select number of clocks to drive SDA high", }, { col => 3, table => 0, text => "0:Drive for 10 SCLKs" }, { col => 3, table => 0, text => "1:Drive for 20 SCLKs" }, { col => 3, table => 0, text => " 0=Drive for 10MCLKs " }, { col => 3, table => 0, text => " 1=20MCLKS " }, { col => 0, table => 0, text => "DC_I2C_DDC1_CLK_DRIVE_EN" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select whether SCL pad is pulled up or driven high", }, { col => 3, table => 0, text => "0:Pullup by external resistor" }, { col => 3, table => 0, text => "1:I2C pads drive SCL high" }, { col => 3, table => 0, text => " 0=Pullup by external resistor " }, { col => 3, table => 0, text => " 1=I2C pads drive SCL " }, { col => 0, table => 0, text => "DC_I2C_DDC1_INTRA_BYTE_DELAY" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to specify delay between bytes in units of I2C ", }, { col => 3, table => 0, text => "reference." }, { col => 0, table => 0, text => "DC_I2C_DDC1_INTRA_TRANSACTION_" }, { col => 0, table => 0, text => "DELAY" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to specify delay between transactions in units of I2C ", }, { col => 3, table => 0, text => "reference." }, { col => 0, table => 0, text => "DC_I2C_DDC1_TIME_LIMIT" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Time limit, in units of 256 I2C fast reference (TOCLK) ", }, { col => 3, table => 0, text => "pulses, to wait before timeout when clock is stalled by ", }, { col => undef, table => undef, text => "external device." }, { col => undef, table => undef, text => "DDC1 SETUP" }, { col => "heading", table => 1, text => "DC_I2C_DDC2_SPEED - RW - 32 bits - [GpuF0MMReg:0x7D54]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DDC2_THRESHOLD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x2" }, { col => 3, table => 1, text => "Select threshold to use to determine whether value ", }, { col => 3, table => 1, text => "sampled on SDA is a 1 or 0. Specified in terms of the ratio ", }, { col => 3, table => 1, text => "between the number of sampled ones and the total number ", }, { col => 3, table => 1, text => "of times SDA is sampled." }, { col => 3, table => 1, text => " 0=>0 " }, { col => 3, table => 1, text => " 1=1/4 of total samples " }, { col => 3, table => 1, text => " 2=1/2 of total samples " }, { col => 3, table => 1, text => " 3=3/4 of total samples " }, { col => 0, table => 1, text => "DC_I2C_DDC2_PRESCALE" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "prescale = (m * xtal_frequency) / (desired_i2c_speed), ", }, { col => undef, table => undef, text => "where m is multiply factor, default: m = 1", }, { col => undef, table => undef, text => "DDC2 speed setting" }, { col => "heading", table => 2, text => "DC_I2C_DDC2_SETUP - RW - 32 bits - [GpuF0MMReg:0x7D58]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_I2C_DDC2_DATA_DRIVE_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select whether SDA pad is pulled up or driven high", }, { col => 3, table => 2, text => "0:Pullup by external resistor" }, { col => 3, table => 2, text => "1:I2C pads drive SDA high" }, { col => 3, table => 2, text => " 0=Pullup by external resistor " }, { col => 3, table => 2, text => " 1=I2C pads drive SDA " }, { col => 0, table => 2, text => "DC_I2C_DDC2_DATA_DRIVE_SEL" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select number of clocks to drive SDA high", }, { col => 3, table => 2, text => "0:Drive for 10 SCLKs" }, { col => 3, table => 2, text => "1:Drive for 20 SCLKs" }, { col => 3, table => 2, text => " 0=Drive for 10MCLKs " }, { col => 3, table => 2, text => " 1=20MCLKS " }, ], }, { num => 108, text => [ { col => 0, table => 0, text => "DC_I2C_DDC2_CLK_DRIVE_EN" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select whether SCL pad is pulled up or driven high", }, { col => 3, table => 0, text => "0:Pullup by external resistor" }, { col => 3, table => 0, text => "1:I2C pads drive SCL high" }, { col => 3, table => 0, text => " 0=Pullup by external resistor " }, { col => 3, table => 0, text => " 1=I2C pads drive SCL " }, { col => 0, table => 0, text => "DC_I2C_DDC2_INTRA_BYTE_DELAY" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to specify delay between bytes in units of I2C ", }, { col => 3, table => 0, text => "reference." }, { col => 0, table => 0, text => "DC_I2C_DDC2_INTRA_TRANSACTION_" }, { col => 0, table => 0, text => "DELAY" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to specify delay between transactions in units of I2C ", }, { col => 3, table => 0, text => "reference." }, { col => 0, table => 0, text => "DC_I2C_DDC2_TIME_LIMIT" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Time limit, in units of 256 I2C fast reference (TOCLK) ", }, { col => 3, table => 0, text => "pulses, to wait before timeout when clock is stalled by ", }, { col => undef, table => undef, text => "external device." }, { col => undef, table => undef, text => "DDC2 SETUP" }, { col => "heading", table => 1, text => "DC_I2C_DDC3_SPEED - RW - 32 bits - [GpuF0MMReg:0x7D5C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DDC3_THRESHOLD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x2" }, { col => 3, table => 1, text => "Select threshold to use to determine whether value ", }, { col => 3, table => 1, text => "sampled on SDA is a 1 or 0. Specified in terms of the ratio ", }, { col => 3, table => 1, text => "between the number of sampled ones and the total number ", }, { col => 3, table => 1, text => "of times SDA is sampled." }, { col => 3, table => 1, text => " 0=>0 " }, { col => 3, table => 1, text => " 1=1/4 of total samples " }, { col => 3, table => 1, text => " 2=1/2 of total samples " }, { col => 3, table => 1, text => " 3=3/4 of total samples " }, { col => 0, table => 1, text => "DC_I2C_DDC3_PRESCALE" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "prescale = (m * xtal_frequency) / (desired_i2c_speed), ", }, { col => undef, table => undef, text => "where m is multiply factor, default: m = 1", }, { col => undef, table => undef, text => "DDC2 speed setting" }, { col => "heading", table => 2, text => "DC_I2C_DDC3_SETUP - RW - 32 bits - [GpuF0MMReg:0x7D60]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_I2C_DDC3_DATA_DRIVE_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select whether SDA pad is pulled up or driven high", }, { col => 3, table => 2, text => "0:Pullup by external resistor" }, { col => 3, table => 2, text => "1:I2C pads drive SDA high" }, { col => 3, table => 2, text => " 0=Pullup by external resistor " }, { col => 3, table => 2, text => " 1=I2C pads drive SDA " }, { col => 0, table => 2, text => "DC_I2C_DDC3_DATA_DRIVE_SEL" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select number of clocks to drive SDA high", }, { col => 3, table => 2, text => "0:Drive for 10 SCLKs" }, { col => 3, table => 2, text => "1:Drive for 20 SCLKs" }, { col => 3, table => 2, text => " 0=Drive for 10MCLKs " }, { col => 3, table => 2, text => " 1=20MCLKS " }, { col => 0, table => 2, text => "DC_I2C_DDC3_CLK_DRIVE_EN" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select whether SCL pad is pulled up or driven high", }, { col => 3, table => 2, text => "0:Pullup by external resistor" }, { col => 3, table => 2, text => "1:I2C pads drive SCL high" }, { col => 3, table => 2, text => " 0=Pullup by external resistor " }, { col => 3, table => 2, text => " 1=I2C pads drive SCL " }, { col => 0, table => 2, text => "DC_I2C_DDC3_INTRA_BYTE_DELAY" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Use to specify delay between bytes in units of I2C ", }, { col => 3, table => 2, text => "reference." }, { col => 0, table => 2, text => "DC_I2C_DDC3_INTRA_TRANSACTION_" }, { col => 0, table => 2, text => "DELAY" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Use to specify delay between transactions in units of I2C ", }, { col => 3, table => 2, text => "reference." }, { col => 0, table => 2, text => "DC_I2C_DDC3_TIME_LIMIT" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Time limit, in units of 256 I2C fast reference (TOCLK) ", }, { col => 3, table => 2, text => "pulses, to wait before timeout when clock is stalled by ", }, { col => undef, table => undef, text => "external device." }, { col => undef, table => undef, text => "DDC3 SETUP" }, ], }, { num => 109, text => [ { col => "heading", table => 0, text => "DC_I2C_TRANSACTION0 - RW - 32 bits - [GpuF0MMReg:0x7D64]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_RW0" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read/write indicator for first transaction - set to 0 for write, 1 ", }, { col => 3, table => 0, text => "for read. This bit only controls DC_I2C behaviour - the R/W ", }, { col => 3, table => 0, text => "bit in the transaction is programmed into the I2C buffer as ", }, { col => 3, table => 0, text => "the LSB of the address byte." }, { col => 3, table => 0, text => " 0=WRITE " }, { col => 3, table => 0, text => " 1=READ " }, { col => 0, table => 0, text => "DC_I2C_STOP_ON_NACK0" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether the current transfer will stop if a NACK ", }, { col => 3, table => 0, text => "is received during the first transaction (current transaction ", }, { col => 3, table => 0, text => "always stops)." }, { col => 3, table => 0, text => " 0=STOP CURRENT TRANSACTION, GO TO NEXT ", }, { col => 3, table => 0, text => "TRANSACTION " }, { col => 3, table => 0, text => " 1=STOP ALL TRANSACTIONS, SEND STOP BIT ", }, { col => 0, table => 0, text => "DC_I2C_ACK_ON_READ0" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether hardware will send an ACK after the ", }, { col => 3, table => 0, text => "last byte on a read in the first transaction.", }, { col => 3, table => 0, text => " 0=Send NACK " }, { col => 3, table => 0, text => " 1=Send ACK " }, { col => 0, table => 0, text => "DC_I2C_START0" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether a start bit will be sent before the first ", }, { col => 3, table => 0, text => "transaction" }, { col => 3, table => 0, text => " 0=NO START " }, { col => 3, table => 0, text => " 1=START " }, { col => 0, table => 0, text => "DC_I2C_STOP0" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether a stop bit will be sent after the first ", }, { col => 3, table => 0, text => "transaction" }, { col => 3, table => 0, text => " 0=NO STOP " }, { col => 3, table => 0, text => " 1=STOP " }, { col => 0, table => 0, text => "DC_I2C_COUNT0" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Byte count for first transaction (excluding the first byte, ", }, { col => undef, table => undef, text => "which is usually the address)." }, { col => undef, table => undef, text => "Configuration for first transaction", }, { col => undef, table => undef, text => "DC_I2C_TRANSACTION1 - RW - 32 bits - [GpuF0MMReg:0x7D68]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DC_I2C_RW1" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read/write indicator for second transaction - set to 0 for ", }, { col => undef, table => undef, text => "write, 1 for read. This bit only controls DC_I2C behaviour - ", }, { col => undef, table => undef, text => "the R/W bit in the transaction is programmed into the I2C ", }, { col => undef, table => undef, text => "buffer as the LSB of the address byte.", }, { col => undef, table => undef, text => " 0=WRITE " }, { col => undef, table => undef, text => " 1=READ " }, { col => undef, table => undef, text => "DC_I2C_STOP_ON_NACK1" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Determines whether the current transfer will stop if a NACK ", }, { col => undef, table => undef, text => "is received during the second transaction (current ", }, { col => undef, table => undef, text => "transaction always stops)." }, { col => undef, table => undef, text => " 0=STOP CURRENT TRANSACTION, GO TO NEXT ", }, { col => undef, table => undef, text => "TRANSACTION " }, { col => undef, table => undef, text => " 1=STOP ALL TRANSACTIONS, SEND STOP BIT ", }, { col => undef, table => undef, text => "DC_I2C_ACK_ON_READ1" }, { col => undef, table => undef, text => 9 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Determines whether hardware will send an ACK after the ", }, { col => undef, table => undef, text => "last byte on a read in the second transaction.", }, { col => undef, table => undef, text => " 0=Send NACK " }, { col => undef, table => undef, text => " 1=Send ACK " }, { col => undef, table => undef, text => "DC_I2C_START1" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Determines whether a start bit will be sent before the ", }, { col => undef, table => undef, text => "second transaction" }, { col => undef, table => undef, text => " 0=NO START " }, { col => undef, table => undef, text => " 1=START " }, ], }, { num => 110, text => [ { col => 0, table => 0, text => "DC_I2C_STOP1" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether a stop bit will be sent after the second ", }, { col => 3, table => 0, text => "transaction" }, { col => 3, table => 0, text => " 0=NO STOP " }, { col => 3, table => 0, text => " 1=STOP " }, { col => 0, table => 0, text => "DC_I2C_COUNT1" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Byte count for second transaction (excluding the first byte, ", }, { col => undef, table => undef, text => "which is usually the address)." }, { col => undef, table => undef, text => "Configuration for second transaction", }, { col => "heading", table => 1, text => "DC_I2C_TRANSACTION2 - RW - 32 bits - [GpuF0MMReg:0x7D6C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_RW2" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Read/write indicator for third transaction - set to 0 for write, ", }, { col => 3, table => 1, text => "1 for read. This bit only controls DC_I2C behaviour - the ", }, { col => 3, table => 1, text => "R/W bit in the transaction is programmed into the I2C buffer ", }, { col => 3, table => 1, text => "as the LSB of the address byte." }, { col => 3, table => 1, text => " 0=WRITE " }, { col => 3, table => 1, text => " 1=READ " }, { col => 0, table => 1, text => "DC_I2C_STOP_ON_NACK2" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether the current transfer will stop if a NACK ", }, { col => 3, table => 1, text => "is received during the third transaction (current transaction ", }, { col => 3, table => 1, text => "always stops)." }, { col => 3, table => 1, text => " 0=STOP CURRENT TRANSACTION, GO TO NEXT ", }, { col => 3, table => 1, text => "TRANSACTION " }, { col => 3, table => 1, text => " 1=STOP ALL TRANSACTIONS, SEND STOP BIT ", }, { col => 0, table => 1, text => "DC_I2C_ACK_ON_READ2" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether hardware will send an ACK after the ", }, { col => 3, table => 1, text => "last byte on a read in the third transaction.", }, { col => 3, table => 1, text => " 0=Send NACK " }, { col => 3, table => 1, text => " 1=Send ACK " }, { col => 0, table => 1, text => "DC_I2C_START2" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether a start bit will be sent before the third ", }, { col => 3, table => 1, text => "transaction" }, { col => 3, table => 1, text => " 0=NO START " }, { col => 3, table => 1, text => " 1=START " }, { col => 0, table => 1, text => "DC_I2C_STOP2" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether a stop bit will be sent after the third ", }, { col => 3, table => 1, text => "transaction" }, { col => 3, table => 1, text => " 0=NO STOP " }, { col => 3, table => 1, text => " 1=STOP " }, { col => 0, table => 1, text => "DC_I2C_COUNT2" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte count for third transaction (excluding the first byte, ", }, { col => undef, table => undef, text => "which is usually the address)." }, { col => undef, table => undef, text => "Configuration for third transaction", }, { col => "heading", table => 2, text => "DC_I2C_TRANSACTION3 - RW - 32 bits - [GpuF0MMReg:0x7D70]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_I2C_RW3" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read/write indicator for fourth transaction - set to 0 for write, ", }, { col => 3, table => 2, text => "1 for read. This bit only controls DC_I2C behaviour - the ", }, { col => 3, table => 2, text => "R/W bit in the transaction is programmed into the I2C buffer ", }, { col => 3, table => 2, text => "as the LSB of the address byte." }, { col => 3, table => 2, text => " 0=WRITE " }, { col => 3, table => 2, text => " 1=READ " }, { col => 0, table => 2, text => "DC_I2C_STOP_ON_NACK3" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Determines whether the current transfer will stop if a NACK ", }, { col => 3, table => 2, text => "is received during the fourth transaction (current transaction ", }, { col => 3, table => 2, text => "always stops)." }, { col => 3, table => 2, text => " 0=STOP CURRENT TRANSACTION, GO TO NEXT ", }, { col => 3, table => 2, text => "TRANSACTION " }, { col => 3, table => 2, text => " 1=STOP ALL TRANSACTIONS, SEND STOP BIT ", }, ], }, { num => 111, text => [ { col => 0, table => 0, text => "DC_I2C_ACK_ON_READ3" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether hardware will send an ACK after the ", }, { col => 3, table => 0, text => "last byte on a read in the fourth transaction.", }, { col => 3, table => 0, text => " 0=Send NACK " }, { col => 3, table => 0, text => " 1=Send ACK " }, { col => 0, table => 0, text => "DC_I2C_START3" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether a start bit will be sent before the fourth ", }, { col => 3, table => 0, text => "transaction" }, { col => 3, table => 0, text => " 0=NO START " }, { col => 3, table => 0, text => " 1=START " }, { col => 0, table => 0, text => "DC_I2C_STOP3" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether a stop bit will be sent after the fourth ", }, { col => 3, table => 0, text => "transaction" }, { col => 3, table => 0, text => " 0=NO STOP " }, { col => 3, table => 0, text => " 1=STOP " }, { col => 0, table => 0, text => "DC_I2C_COUNT3" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Byte count for fourth transaction (excluding the first byte, ", }, { col => undef, table => undef, text => "which is usually the address)." }, { col => undef, table => undef, text => "Configuration for fourth transaction", }, { col => "heading", table => 1, text => "DC_I2C_DATA - RW - 32 bits - [GpuF0MMReg:0x7D74]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DATA_RW" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select whether buffer access will be a read or write. For ", }, { col => 3, table => 1, text => "writes, address auto-increments on write to DC_I2C_DATA. ", }, { col => 3, table => 1, text => "For reads, address auto-increments on reads to ", }, { col => 3, table => 1, text => "DC_I2C_DATA." }, { col => 3, table => 1, text => " 0=Write " }, { col => 3, table => 1, text => " 1=Read " }, { col => 0, table => 1, text => "DC_I2C_DATA" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Use to fill or read the I2C buffer" }, { col => 0, table => 1, text => "DC_I2C_INDEX" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Use to set index into I2C buffer for next read or current ", }, { col => 3, table => 1, text => "write, or to read index of current read or next write. Writable ", }, { col => 3, table => 1, text => "only when DC_I2C_INDEX_WRITE=1." }, { col => 0, table => 1, text => "DC_I2C_INDEX_WRITE (W)" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "To write index field, set this bit to 1 while writing ", }, { col => undef, table => undef, text => "DC_I2C_DATA." }, { col => undef, table => undef, text => "This register is used to read or write the I2C buffer", }, { col => "heading", table => 2, text => "GENERIC_I2C_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D80]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GENERIC_I2C_GO (W)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Write 1 to start I2C transfer" }, { col => 0, table => 2, text => "GENERIC_I2C_SOFT_RESET" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Write 1 to reset I2C controller" }, { col => 0, table => 2, text => "GENERIC_I2C_SEND_RESET" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to send reset sequence (9 clocks with no data) at ", }, { col => 3, table => 2, text => "start of transfer. This sequence is sent after DC_I2C_GO is ", }, { col => undef, table => undef, text => "written to 1" }, { col => undef, table => undef, text => "generic i2c control register" }, { col => "heading", table => 3, text => "GENERIC_I2C_INTERRUPT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D84]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "GENERIC_I2C_DONE_INT (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "GENERIC_I2C_DONE interrupt status" }, { col => 0, table => 3, text => "GENERIC_I2C_DONE_ACK (W)" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Acknowledge bit for GENERIC_I2C_DONE. Write 1 to ", }, { col => 3, table => 3, text => "clear interrupt." }, { col => 0, table => 3, text => "GENERIC_I2C_DONE_MASK" }, { col => 1, table => 3, text => 2 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Mask bit for GENERIC_I2C_DONE. Set to 1 to enable ", }, { col => 3, table => 3, text => "interrupt." }, ], }, { num => 112, text => [ { col => undef, table => undef, text => "generic i2c interrupt control register", }, { col => "heading", table => 0, text => "GENERIC_I2C_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D88]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "GENERIC_I2C_STATUS (R)" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Status of the i2c internal state code: 0: idle, 1: sending start, ", }, { col => 3, table => 0, text => "2: sending address, 3: transmitting/receiving data, 4: ", }, { col => 3, table => 0, text => "transmitting/receiving ack 5: sending stop, 6:N/A, 7:byte ", }, { col => 3, table => 0, text => "delay, 8: wait for GO command" }, { col => 0, table => 0, text => "GENERIC_I2C_DONE (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates the completion of i2c transfer. Cleared by writing ", }, { col => 3, table => 0, text => "GENERIC_I2C_DONE_ACK or GO" }, { col => 0, table => 0, text => "GENERIC_I2C_ABORTED (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that abort request ccurred during i2c transfer, ", }, { col => 3, table => 0, text => "stopping transfer. Cleared on GO." }, { col => 0, table => 0, text => "GENERIC_I2C_TIMEOUT (R)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that timeout condition occurred during SW ", }, { col => 3, table => 0, text => "transfer, stopping transfer. Cleared on GO.", }, { col => 0, table => 0, text => "GENERIC_I2C_STOPPED_ON_NACK " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that SW transfer was interrpted due to NACK ", }, { col => 3, table => 0, text => "when STOP_ON_NACK=1. Cleared on GO." }, { col => 0, table => 0, text => "GENERIC_I2C_NACK (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Indicates that I2C slave did not issue an acknowledge ", }, { col => undef, table => undef, text => "during the i2c transaction. Cleared on GO.", }, { col => undef, table => undef, text => "generic i2c read only status register", }, { col => "heading", table => 1, text => "GENERIC_I2C_SPEED - RW - 32 bits - [GpuF0MMReg:0x7D8C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GENERIC_I2C_THRESHOLD" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x2" }, { col => 3, table => 1, text => "Select threshold to use to determine whether value ", }, { col => 3, table => 1, text => "sampled on SDA is a 1 or 0 when SCL is hi. 0: begining of ", }, { col => 3, table => 1, text => "SCL(hi), 1: 1/4 of SCL(hi),2: 1/2 of SCL(hi),3: 3/4 of SCL(hi)", }, { col => 3, table => 1, text => " 0=>0 " }, { col => 3, table => 1, text => " 1=1/4 of total samples " }, { col => 3, table => 1, text => " 2=1/2 of total samples " }, { col => 3, table => 1, text => " 3=3/4 of total samples " }, { col => 0, table => 1, text => "GENERIC_I2C_PRESCALE" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "prescale = (m * xtal_frequency) / (4 * desired_i2c_speed), ", }, { col => undef, table => undef, text => "where m is multiply factor, default: m = 1", }, { col => undef, table => undef, text => "Generic i2c bus config" }, { col => undef, table => undef, text => "GENERIC_I2C_SETUP - RW - 32 bits - [GpuF0MMReg:0x7D90]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "GENERIC_I2C_DATA_DRIVE_EN" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select whether SDA pad is pulled up or driven high", }, { col => undef, table => undef, text => "0:Pullup by external resistor" }, { col => undef, table => undef, text => "1:I2C pads drive SDA high" }, { col => undef, table => undef, text => " 0=Pullup by external resistor ", }, { col => undef, table => undef, text => " 1=I2C pads drive SDA " }, { col => undef, table => undef, text => "GENERIC_I2C_DATA_DRIVE_SEL" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select number of clocks to drive SDA high", }, { col => undef, table => undef, text => "0:Drive for 10 SCLKs" }, { col => undef, table => undef, text => "1:Drive for 20 SCLKs" }, { col => undef, table => undef, text => " 0=Drive for 10MCLKs " }, { col => undef, table => undef, text => " 1=20MCLKS " }, ], }, { num => 113, text => [ { col => 0, table => 0, text => "GENERIC_I2C_CLK_DRIVE_EN" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select whether SCL pad is pulled up or driven high", }, { col => 3, table => 0, text => "0:Pullup by external resistor" }, { col => 3, table => 0, text => "1:I2C pads drive SCL high" }, { col => 3, table => 0, text => " 0=Pullup by external resistor " }, { col => 3, table => 0, text => " 1=I2C pads drive SCL " }, { col => 0, table => 0, text => "GENERIC_I2C_INTRA_BYTE_DELAY" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to specify delay between bytes in units of I2C ", }, { col => 3, table => 0, text => "reference." }, { col => 0, table => 0, text => "GENERIC_I2C_TIME_LIMIT" }, { col => 1, table => 0, text => "31:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Time limit, in units of 256 I2C fast reference (TOCLK) ", }, { col => 3, table => 0, text => "pulses, to wait before timeout when clock is stalled by ", }, { col => undef, table => undef, text => "external device." }, { col => undef, table => undef, text => "Generic i2c bus config" }, { col => "heading", table => 1, text => "GENERIC_I2C_TRANSACTION - RW - 32 bits - [GpuF0MMReg:0x7D94]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GENERIC_I2C_RW" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Read/write indicator for second transaction - set to 0 for ", }, { col => 3, table => 1, text => "write, 1 for read. This bit only controls DC_I2C behaviour - ", }, { col => 3, table => 1, text => "the R/W bit in the transaction is programmed into the I2C ", }, { col => 3, table => 1, text => "buffer as the LSB of the address byte." }, { col => 3, table => 1, text => " 0=WRITE " }, { col => 3, table => 1, text => " 1=READ " }, { col => 0, table => 1, text => "GENERIC_I2C_STOP_ON_NACK" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether the current transfer will stop if a NACK ", }, { col => 3, table => 1, text => "is received during the transaction (current transaction ", }, { col => 3, table => 1, text => "always stops)." }, { col => 3, table => 1, text => " 0=STOP CURRENT TRANSACTION, GO TO NEXT ", }, { col => 3, table => 1, text => "TRANSACTION " }, { col => 3, table => 1, text => " 1=STOP ALL TRANSACTIONS, SEND STOP BIT ", }, { col => 0, table => 1, text => "GENERIC_I2C_ACK_ON_READ" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether hardware will send an ACK after the ", }, { col => 3, table => 1, text => "last byte on a read in the second transaction.", }, { col => 3, table => 1, text => " 0=Send NACK " }, { col => 3, table => 1, text => " 1=Send ACK " }, { col => 0, table => 1, text => "GENERIC_I2C_START" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether a start bit will be sent before the ", }, { col => 3, table => 1, text => "second transaction" }, { col => 3, table => 1, text => " 0=NO START " }, { col => 3, table => 1, text => " 1=START " }, { col => 0, table => 1, text => "GENERIC_I2C_STOP" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether a stop bit will be sent after the second ", }, { col => 3, table => 1, text => "transaction" }, { col => 3, table => 1, text => " 0=NO STOP " }, { col => 3, table => 1, text => " 1=STOP " }, { col => 0, table => 1, text => "GENERIC_I2C_COUNT" }, { col => 1, table => 1, text => "19:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte count for the transaction (excluding the first byte, ", }, { col => undef, table => undef, text => "which is usually the address)." }, { col => undef, table => undef, text => "generic i2c transaction setup register", }, { col => undef, table => undef, text => "GENERIC_I2C_DATA - RW - 32 bits - [GpuF0MMReg:0x7D98]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "GENERIC_I2C_DATA_RW" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select whether buffer access will be a read or write. For ", }, { col => undef, table => undef, text => "writes, address auto-increments on write to DC_I2C_DATA. ", }, { col => undef, table => undef, text => "For reads, address auto-increments on reads to ", }, { col => undef, table => undef, text => "GENERIC_I2C_DATA." }, { col => undef, table => undef, text => " 0=Write " }, { col => undef, table => undef, text => " 1=Read " }, { col => undef, table => undef, text => "GENERIC_I2C_DATA" }, { col => undef, table => undef, text => "15:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Use to fill or read the generic I2C buffer", }, ], }, { num => 114, text => [ { col => 0, table => 0, text => "GENERIC_I2C_INDEX" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Use to set index into I2C buffer for next read or current ", }, { col => 3, table => 0, text => "write, or to read index of current read or next write. Writable ", }, { col => 3, table => 0, text => "only when GENERIC_I2C_INDEX_WRITE=1." }, { col => 0, table => 0, text => "GENERIC_I2C_INDEX_WRITE (W)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "To write index field, set this bit to 1 while writing ", }, { col => undef, table => undef, text => "GENERIC_I2C_DATA" }, { col => undef, table => undef, text => "This register is used to read or write the I2C buffer", }, { col => "heading", table => 1, text => "GENERIC_I2C_PIN_SELECTION - RW - 32 bits - [GpuF0MMReg:0x7D9C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GENERIC_I2C_SCL_PIN_SEL" }, { col => 1, table => 1, text => "6:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "GPIO pin selection to use for SCL, if " }, { col => 3, table => 1, text => "GENERIC_I2C_SCL_PIN_SEL == " }, { col => 3, table => 1, text => "GENERIC_I2C_SDA_PIN_SEL => disable pin selectin. ", }, { col => 3, table => 1, text => "Refer to generic_i2c_programming guide for pin selection ", }, { col => 3, table => 1, text => "details" }, { col => 0, table => 1, text => "GENERIC_I2C_SDA_PIN_SEL" }, { col => 1, table => 1, text => "14:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "GPIO pin selection to use for SDA, if " }, { col => 3, table => 1, text => "GENERIC_I2C_SCL_PIN_SEL == " }, { col => 3, table => 1, text => "GENERIC_I2C_SDA_PIN_SEL => disable pin selectin. ", }, { col => 3, table => 1, text => "Refer to generic_i2c_programming guide for pin selection ", }, { col => undef, table => undef, text => "details" }, { col => undef, table => undef, text => "Pin selection register" }, { col => "heading", table => 2, text => "GENERIC_I2C_PIN_DEBUG - RW - 32 bits - [GpuF0MMReg:0x7DA0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GENERIC_I2C_SCL_OUTPUT" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SCL pin output value when GENERIC_I2C_SCL_EN is set", }, { col => 0, table => 2, text => "GENERIC_I2C_SCL_INPUT (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SCL pin input value when SCL pin is not driving, i.e. ", }, { col => 3, table => 2, text => "GENERIC_I2C_SCL_EN = 0" }, { col => 0, table => 2, text => "GENERIC_I2C_SCL_EN" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SCL tri-state output control, set to one when SCL needs to ", }, { col => 3, table => 2, text => "drive" }, { col => 0, table => 2, text => "GENERIC_I2C_SDA_OUTPUT" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SDA pin output value when GENERIC_I2C_SDA_EN is set", }, { col => 0, table => 2, text => "GENERIC_I2C_SDA_INPUT (R)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SDA pin input value when SDA pin is not driving, i.e. ", }, { col => 3, table => 2, text => "GENERIC_I2C_SCL_EN = 0" }, { col => 0, table => 2, text => "GENERIC_I2C_SDA_EN" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SCL tri-state output control, set to one when SCL needs to ", }, { col => undef, table => undef, text => "drive" }, { col => undef, table => undef, text => "Generic i2c pin debug register, allow software to control the selected pins directly", }, { col => "heading", table => 3, text => "DC_I2C_DDC4_HW_STATUS - RW - 32 bits - [GpuF0MMReg:0x7DB0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_I2C_DDC4_HW_STATUS (R)" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Current HW status of DC_I2C" }, { col => 3, table => 3, text => " 0=Idle " }, { col => 3, table => 3, text => " 1=In use by HW " }, { col => 3, table => 3, text => " 2=In use by HW " }, { col => 3, table => 3, text => " 3=Reserved " }, { col => 0, table => 3, text => "DC_I2C_DDC4_HW_DONE (R)" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Set on completion of HW transfer. Cleared by writing ", }, { col => 3, table => 3, text => "DC_I2C_HW_DONE_ACK to 1" }, { col => 0, table => 3, text => "DC_I2C_DDC4_HW_REQ (R)" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Hardware requests use of DC_I2C interface (indicates that ", }, { col => 3, table => 3, text => "request is pending - i.e. queued). Cleared when request ", }, { col => 3, table => 3, text => "becomes active or by DC_I2C_ABORT_HW_XFER.", }, { col => 0, table => 3, text => "DC_I2C_DDC4_HW_URG (R)" }, { col => 1, table => 3, text => 17 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Indicates that hardware I2C request is urgent (used by ", }, { col => 3, table => 3, text => "arbitration logic)." }, ], }, { num => 115, text => [ { col => undef, table => undef, text => "2.5.2" }, { col => undef, table => undef, text => "Video Interface Port Host Port Registers", }, { col => undef, table => undef, text => "Status fields for DC_I2C engine" }, { col => "heading", table => 0, text => "DC_I2C_DDC4_SPEED - RW - 32 bits - [GpuF0MMReg:0x7DB4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_I2C_DDC4_THRESHOLD" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "Select threshold to use to determine whether value ", }, { col => 3, table => 0, text => "sampled on SDA is a 1 or 0. Specified in terms of the ratio ", }, { col => 3, table => 0, text => "between the number of sampled ones and the total number ", }, { col => 3, table => 0, text => "of times SDA is sampled." }, { col => 3, table => 0, text => " 0=>0 " }, { col => 3, table => 0, text => " 1=1/4 of total samples " }, { col => 3, table => 0, text => " 2=1/2 of total samples " }, { col => 3, table => 0, text => " 3=3/4 of total samples " }, { col => 0, table => 0, text => "DC_I2C_DDC4_PRESCALE" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "prescale = (m * xtal_frequency) / (desired_i2c_speed), ", }, { col => undef, table => undef, text => "where m is multiply factor, default: m = 1", }, { col => undef, table => undef, text => "DDC4 speed setting" }, { col => "heading", table => 1, text => "DC_I2C_DDC4_SETUP - RW - 32 bits - [GpuF0MMReg:0x7DBC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_I2C_DDC4_DATA_DRIVE_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select whether SDA pad is pulled up or driven high", }, { col => 3, table => 1, text => "0:Pullup by external resistor" }, { col => 3, table => 1, text => "1:I2C pads drive SDA high" }, { col => 3, table => 1, text => " 0=Pullup by external resistor " }, { col => 3, table => 1, text => " 1=I2C pads drive SDA " }, { col => 0, table => 1, text => "DC_I2C_DDC4_DATA_DRIVE_SEL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select number of clocks to drive SDA high", }, { col => 3, table => 1, text => "0:Drive for 10 SCLKs" }, { col => 3, table => 1, text => "1:Drive for 20 SCLKs" }, { col => 3, table => 1, text => " 0=Drive for 10MCLKs " }, { col => 3, table => 1, text => " 1=20MCLKS " }, { col => 0, table => 1, text => "DC_I2C_DDC4_CLK_DRIVE_EN" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select whether SCL pad is pulled up or driven high", }, { col => 3, table => 1, text => "0:Pullup by external resistor" }, { col => 3, table => 1, text => "1:I2C pads drive SCL high" }, { col => 3, table => 1, text => " 0=Pullup by external resistor " }, { col => 3, table => 1, text => " 1=I2C pads drive SCL " }, { col => 0, table => 1, text => "DC_I2C_DDC4_INTRA_BYTE_DELAY" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Use to specify delay between bytes in units of I2C ", }, { col => 3, table => 1, text => "reference." }, { col => 0, table => 1, text => "DC_I2C_DDC4_INTRA_TRANSACTION_" }, { col => 0, table => 1, text => "DELAY" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Use to specify delay between transactions in units of I2C ", }, { col => 3, table => 1, text => "reference." }, { col => 0, table => 1, text => "DC_I2C_DDC4_TIME_LIMIT" }, { col => 1, table => 1, text => "31:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Time limit, in units of 256 I2C fast reference (TOCLK) ", }, { col => 3, table => 1, text => "pulses, to wait before timeout when clock is stalled by ", }, { col => undef, table => undef, text => "external device." }, { col => undef, table => undef, text => "DDC4 SETUP" }, { col => undef, table => undef, text => "VIPH_REG_ADDR - RW - 32 bits - [GpuF0MMReg:0xC80]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 116, text => [ { col => 0, table => 0, text => "VIPH_REG_AD" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bits (11:0): Slave registers address. Bits(12): 0 = register ", }, { col => 3, table => 0, text => "access, 1= FIFO access. Bits(13): 0= register write, 1 = ", }, { col => undef, table => undef, text => "register read. Bits(15:14): Slave device ID.", }, { col => undef, table => undef, text => "VIP Host register access command and address.", }, { col => "heading", table => 1, text => "VIPH_REG_DATA - RW - 32 bits - [GpuF0MMReg:0xC84]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPH_REG_DT_R (R)" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Read from VIP Host Port register data port", }, { col => 0, table => 1, text => "VIPH_REG_DT_W (W)" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Write to VIP Host Port register data port", }, { col => undef, table => undef, text => "VIP Host Port register data port", }, { col => "heading", table => 2, text => "VIPH_CH0_DATA - RW - 32 bits - [GpuF0MMReg:0xC00]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VIPH_CH0_DT" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => "heading", table => 3, text => "VIPH_CH1_DATA - RW - 32 bits - [GpuF0MMReg:0xC04]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "VIPH_CH1_DT" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => "heading", table => 4, text => "VIPH_CH2_DATA - RW - 32 bits - [GpuF0MMReg:0xC08]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "VIPH_CH2_DT" }, { col => 1, table => 4, text => "31:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => "heading", table => 5, text => "VIPH_CH3_DATA - RW - 32 bits - [GpuF0MMReg:0xC0C]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "VIPH_CH3_DT" }, { col => 1, table => 5, text => "31:0" }, { col => 2, table => 5, text => "0x0" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => undef, table => undef, text => "VIPH0 data interface" }, { col => "heading", table => 6, text => "VIPH_CH0_ADDR - RW - 32 bits - [GpuF0MMReg:0xC10]", }, { col => 0, table => 6, text => "Field Name" }, { col => 1, table => 6, text => "Bits" }, { col => 2, table => 6, text => "Default" }, { col => 3, table => 6, text => "Description" }, ], }, { num => 117, text => [ { col => 0, table => 0, text => "VIPH_CH0_AD" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bit(3:0): FIFO address Bit(4): 0= register access, 1 = FIFO ", }, { col => 3, table => 0, text => "access. Bit(5): 0= register write, 1= register read. Bits(7:6): ", }, { col => undef, table => undef, text => "Slave device ID." }, { col => undef, table => undef, text => "VIPH0 command + address." }, { col => "heading", table => 1, text => "VIPH_CH1_ADDR - RW - 32 bits - [GpuF0MMReg:0xC14]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPH_CH1_AD" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bit(3:0): FIFO address Bit(4): 0= register access, 1 = FIFO ", }, { col => 3, table => 1, text => "access. Bit(5): 0= register write, 1= register read. Bits(7:6): ", }, { col => undef, table => undef, text => "Slave device ID." }, { col => undef, table => undef, text => "VIPH1 command + address." }, { col => "heading", table => 2, text => "VIPH_CH2_ADDR - RW - 32 bits - [GpuF0MMReg:0xC18]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VIPH_CH2_AD" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bit(3:0): FIFO address Bit(4): 0= register access, 1 = FIFO ", }, { col => 3, table => 2, text => "access. Bit(5): 0= register write, 1= register read. Bits(7:6): ", }, { col => undef, table => undef, text => "Slave device ID." }, { col => undef, table => undef, text => "VIPH2 command + address." }, { col => "heading", table => 3, text => "VIPH_CH3_ADDR - RW - 32 bits - [GpuF0MMReg:0xC1C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "VIPH_CH3_AD" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bit(3:0): FIFO address Bit(4): 0= register access, 1 = FIFO ", }, { col => 3, table => 3, text => "access. Bit(5): 0= register write, 1= register read. Bits(7:6): ", }, { col => undef, table => undef, text => "Slave device ID." }, { col => undef, table => undef, text => "VIPH3 command + address." }, { col => "heading", table => 4, text => "VIPH_CH0_SBCNT - RW - 32 bits - [GpuF0MMReg:0xC20]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "VIPH_CH0_SCNT" }, { col => 1, table => 4, text => "19:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Write non-zero byte count will trigger DMA. Maximum 2 jobs ", }, { col => undef, table => undef, text => "can be loaded into the queue any one time.", }, { col => undef, table => undef, text => "Byte count of transfer requested.", }, { col => "heading", table => 5, text => "VIPH_CH1_SBCNT - RW - 32 bits - [GpuF0MMReg:0xC24]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "VIPH_CH1_SCNT" }, { col => 1, table => 5, text => "19:0" }, { col => 2, table => 5, text => "0x0" }, { col => 3, table => 5, text => "Write non-zero byte count will trigger DMA. Maximum 2 jobs ", }, { col => undef, table => undef, text => "can be loaded into the queue any one time.", }, { col => undef, table => undef, text => "Byte count of transfer requested.", }, ], }, { num => 118, text => [ { col => undef, table => undef, text => "VIPH_CH2_SBCNT - RW - 32 bits - [GpuF0MMReg:0xC28]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "VIPH_CH2_SCNT" }, { col => undef, table => undef, text => "19:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Write non-zero byte count will trigger DMA. Maximum 2 jobs ", }, { col => undef, table => undef, text => "can be loaded into the queue any one time.", }, { col => undef, table => undef, text => "Byte count of transfer requested.", }, { col => undef, table => undef, text => "VIPH_CH3_SBCNT - RW - 32 bits - [GpuF0MMReg:0xC2C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "VIPH_CH3_SCNT" }, { col => undef, table => undef, text => "19:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Write non-zero byte count will trigger DMA. Maximum 2 jobs ", }, { col => undef, table => undef, text => "can be loaded into the queue any one time.", }, { col => undef, table => undef, text => "Byte count of transfer requested.", }, { col => "heading", table => 0, text => "VIPH_CH0_ABCNT - RW - 32 bits - [GpuF0MMReg:0xC30]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VIPH_CH0_ACNT (R)" }, { col => 1, table => 0, text => "19:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Keep track of active byte-count remaining.", }, { col => undef, table => undef, text => "Read back of remaining byte count.", }, { col => "heading", table => 1, text => "VIPH_CH1_ABCNT - RW - 32 bits - [GpuF0MMReg:0xC34]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPH_CH1_ACNT (R)" }, { col => 1, table => 1, text => "19:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Keep track of active byte-count remaining.", }, { col => undef, table => undef, text => "Read back of remaining byte count.", }, { col => "heading", table => 2, text => "VIPH_CH2_ABCNT - RW - 32 bits - [GpuF0MMReg:0xC38]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VIPH_CH2_ACNT (R)" }, { col => 1, table => 2, text => "19:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Keep track of active byte-count remaining.", }, { col => undef, table => undef, text => "Read back of remaining byte count.", }, { col => "heading", table => 3, text => "VIPH_CH3_ABCNT - RW - 32 bits - [GpuF0MMReg:0xC3C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "VIPH_CH3_ACNT (R)" }, { col => 1, table => 3, text => "19:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Keep track of active byte-count remaining.", }, { col => undef, table => undef, text => "Read back of remaining byte count.", }, ], }, { num => 119, text => [ { col => "heading", table => 0, text => "VIPH_CONTROL - RW - 32 bits - [GpuF0MMReg:0xC40]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VIPH_CLK_SEL" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIPH clock select, only even divider is permitted. Which ", }, { col => 3, table => 0, text => "means VIPH_CLK_SEL(0) must be set to 1." }, { col => 3, table => 0, text => " 0=reserved " }, { col => 3, table => 0, text => " 1=reserved " }, { col => 3, table => 0, text => " 2=reserved " }, { col => 3, table => 0, text => " 3=xclkby4 " }, { col => 3, table => 0, text => " 4=reserved " }, { col => 3, table => 0, text => " 5=xclkby6 " }, { col => 3, table => 0, text => " 6=... (Only EVEN divider is permitted ", }, { col => 0, table => 0, text => "VIPH_REG_RDY (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0= VIPH is ready for next register access. 1= VIPH is busy ", }, { col => 3, table => 0, text => "for current VIPH register access." }, { col => 0, table => 0, text => "VIPH_MAX_WAIT" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of VIP phases before issuing time out. Set to zero ", }, { col => 3, table => 0, text => "means no time out" }, { col => 0, table => 0, text => "VIPH_DMA_MODE" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0= No DMA. 1= DMA" }, { col => 0, table => 0, text => "VIPH_EN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIP Host port Enable" }, { col => 0, table => 0, text => "VIP_DEVICE_DESKTOP (R)" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0=VIP_DEVICE present, 1=No VIP device attached, valid ", }, { col => 3, table => 0, text => "only with MOBILE_DIS=1 and " }, { col => 3, table => 0, text => "VIP_DEVICE_STRAP_DIS=0" }, { col => 0, table => 0, text => "VIP_DEVICE_MOBILE (R)" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0=VIP_DEVICE present, 1=No VIP device attached, valid ", }, { col => 3, table => 0, text => "only with MOBILE_DIS=0 and " }, { col => 3, table => 0, text => "VIP_DEVICE_STRAP_DIS=0" }, { col => 0, table => 0, text => "VIPH_DV0_WID" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIPH0 bus width" }, { col => 3, table => 0, text => " 0=2-bit vipbus " }, { col => 3, table => 0, text => " 1=4-bit vipbus " }, { col => 0, table => 0, text => "VIPH_DV1_WID" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIPH1 bus width" }, { col => 3, table => 0, text => " 0=2-bit vipbus " }, { col => 3, table => 0, text => " 1=4-bit vipbus " }, { col => 0, table => 0, text => "VIPH_DV2_WID" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIPH2 bus width" }, { col => 3, table => 0, text => " 0=2-bit vipbus " }, { col => 3, table => 0, text => " 1=4-bit vipbus " }, { col => 0, table => 0, text => "VIPH_DV3_WID" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VIPH3 bus width" }, { col => 3, table => 0, text => " 0=2-bit vipbus " }, { col => 3, table => 0, text => " 1=4-bit vipbus " }, { col => 0, table => 0, text => "VIPH_PWR_DOWN (R)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'1' to wake up PCICLK." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=STARTUP PCICLK " }, { col => 0, table => 0, text => "VIPH_PWR_DOWN_AK (W)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clear PWR_DOWN by writing a 1. In order to support ", }, { col => 3, table => 0, text => "PCICLK power down mode, it is important to clear this bit ", }, { col => 3, table => 0, text => "every time there is an interrupt from any part of VIP", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Allow the host bus to go back to power down state ", }, { col => 0, table => 0, text => "VIPH_VIPCLK_DIS" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' will supply VIP clock to slave. '1' will stops VIP clock to ", }, { col => 3, table => 0, text => "save power." }, { col => 3, table => 0, text => " 0= " }, { col => 3, table => 0, text => " 1=turn off VIPCLK for power saving " }, { col => 0, table => 0, text => "VIPH_INT_SEL" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=If VIP host port interrupt using input instead of polling, ", }, { col => 3, table => 0, text => "then AUXWIN pin used as interrupt input. ", }, { col => 3, table => 0, text => " 1=If VIP host port interrupt using input instead of polling, ", }, { col => 3, table => 0, text => "then I2C clock pin used as interrupt input. ", }, { col => 0, table => 0, text => "VIP_DEVICE_STRAP_DIS (R)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0=VIP_DEVICE strap must be checked, 1=VIP_DEVICE ", }, { col => undef, table => undef, text => "strap must be ignored" }, { col => undef, table => undef, text => "VIP Host Port Control" }, ], }, { num => 120, text => [ { col => "heading", table => 0, text => "VIPH_DV_LAT - RW - 32 bits - [GpuF0MMReg:0xC44]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VIPH_TIME_UNIT" }, { col => 1, table => 0, text => "11:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Basic time slice" }, { col => 0, table => 0, text => "VIPH_DV0_LAT" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "How many time slice port 0 gets" }, { col => 0, table => 0, text => "VIPH_DV1_LAT" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "How many time slice port 1 gets" }, { col => 0, table => 0, text => "VIPH_DV2_LAT" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "How many time slice port 2 gets" }, { col => 0, table => 0, text => "VIPH_DV3_LAT" }, { col => 1, table => 0, text => "31:28" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "How many time slice port 3 gets" }, { col => undef, table => undef, text => "Time slice partition" }, { col => "heading", table => 1, text => "VIPH_DMA_CHUNK - RW - 32 bits - [GpuF0MMReg:0xC48]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPH_CH0_CHUNK" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Chunk size between VIP host port and DMA for port 0", }, { col => 0, table => 1, text => "VIPH_CH1_CHUNK" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Chunk size between VIP host port and DMA for port 1", }, { col => 0, table => 1, text => "VIPH_CH2_CHUNK" }, { col => 1, table => 1, text => "7:6" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Chunk size between VIP host port and DMA for port 2", }, { col => 0, table => 1, text => "VIPH_CH3_CHUNK" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Chunk size between VIP host port and DMA for port 3", }, { col => 0, table => 1, text => "VIPH_CH0_ABORT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Abort DMA operation through port 0" }, { col => 0, table => 1, text => "VIPH_CH1_ABORT" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Abort DMA operation through port 1" }, { col => 0, table => 1, text => "VIPH_CH2_ABORT" }, { col => 1, table => 1, text => 18 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Abort DMA operation through port 2" }, { col => 0, table => 1, text => "VIPH_CH3_ABORT" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Abort DMA operation through port 3", }, { col => undef, table => undef, text => "DMA transfer chunk size and abort control", }, { col => "heading", table => 2, text => "VIPH_DV_INT - RW - 32 bits - [GpuF0MMReg:0xC4C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VIPH_DV0_INT_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt polling enable for VIP slave device 0", }, { col => 0, table => 2, text => "VIPH_DV1_INT_EN" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt polling enable for VIP slave device 1", }, { col => 0, table => 2, text => "VIPH_DV2_INT_EN" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt polling enable for VIP slave device 2", }, { col => 0, table => 2, text => "VIPH_DV3_INT_EN" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt polling enable for VIP slave device 3", }, { col => 0, table => 2, text => "VIPH_DV0_INT (R)" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt" }, { col => 0, table => 2, text => "VIPH_DV0_AK (W)" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Clear interrupt with a '1'" }, { col => 0, table => 2, text => "VIPH_DV1_INT (R)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt" }, { col => 0, table => 2, text => "VIPH_DV1_AK (W)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Clear interrupt with a '1'" }, { col => 0, table => 2, text => "VIPH_DV2_INT (R)" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt" }, { col => 0, table => 2, text => "VIPH_DV2_AK (W)" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Clear interrupt with a '1'" }, { col => 0, table => 2, text => "VIPH_DV3_INT (R)" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt" }, { col => 0, table => 2, text => "VIPH_DV3_AK (W)" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Clear interrupt with a '1'" }, { col => undef, table => undef, text => "VIP Host port interrupt control" }, { col => "heading", table => 3, text => "VIPH_TIMEOUT_STAT - RW - 32 bits - [GpuF0MMReg:0xC50]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "VIPH_FIFO0_STAT (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "'1' if port 0 time out or hung." }, { col => 0, table => 3, text => "VIPH_FIFO0_AK (W)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Clear FIFO0_STAT with a '1'" }, { col => 0, table => 3, text => "VIPH_FIFO1_STAT (R)" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "'1' if port 1 time out or hung." }, { col => 0, table => 3, text => "VIPH_FIFO1_AK (W)" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Clear FIFO1_STAT with a '1'" }, { col => 0, table => 3, text => "VIPH_FIFO2_STAT (R)" }, { col => 1, table => 3, text => 2 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "'1' if port 2 time out or hung." }, { col => 0, table => 3, text => "VIPH_FIFO2_AK (W)" }, { col => 1, table => 3, text => 2 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Clear FIFO2_STAT with a '1'" }, { col => 0, table => 3, text => "VIPH_FIFO3_STAT (R)" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "'1' if port 3 time out or hung." }, { col => 0, table => 3, text => "VIPH_FIFO3_AK (W)" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Clear FIFO3_STAT with a '1'" }, { col => 0, table => 3, text => "VIPH_REG_STAT (R)" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "'1' if register port time out or hung." }, { col => 0, table => 3, text => "VIPH_REG_AK (W)" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Clear REG_STAT with a '1'" }, ], }, { num => 121, text => [ { col => undef, table => undef, text => "2.5.3" }, { col => undef, table => undef, text => "Capture Registers" }, { col => 0, table => 0, text => "VIPH_AUTO_INT_STAT (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'1' if auto interrupt polling time out or hung.", }, { col => 0, table => 0, text => "VIPH_AUTO_INT_AK (W)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clear AUTO_INT_STAT with a '1'" }, { col => 0, table => 0, text => "VIPH_FIFO0_MASK" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_FIFO1_MASK" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_FIFO2_MASK" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_FIFO3_MASK" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_REG_MASK" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_AUTO_INT_MASK" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_DV0_INT_MASK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_DV1_INT_MASK" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_DV2_INT_MASK" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_DV3_INT_MASK" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' disable interrupt." }, { col => 0, table => 0, text => "VIPH_INTPIN_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0' means no physical pins used for VIP interrupt. 1= ", }, { col => 3, table => 0, text => "physical pins used." }, { col => 0, table => 0, text => "VIPH_INTPIN_INT (R)" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " '1' if physical pins has interrupt." }, { col => 0, table => 0, text => "VIPH_REGR_DIS" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "'0'= any host read from VIPH_REG_DATA will trigger VIP ", }, { col => 3, table => 0, text => "register cycle. 1= Read from VIPH_REG_DATA will not ", }, { col => 3, table => 0, text => "trigger VIP register cycle." }, { col => 0, table => 0, text => "VIP_RBBMIF_RDWR_TIMEOUT_DIS" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit is unused because VIP doesn't have its own ", }, { col => 3, table => 0, text => "decode." }, { col => 3, table => 0, text => "'0'= enable RBBMIF read/write timeout logic. 1= disable ", }, { col => undef, table => undef, text => "RBBMIF read/write timeout logic.", }, { col => undef, table => undef, text => "VIP Host Port Time Out Status" }, { col => "heading", table => 1, text => "VID_BUFFER_CONTROL - RW - 32 bits - [GpuF0MMReg:0xB00]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP0_BUFFER_WATER_MARK" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x10" }, { col => 3, table => 1, text => "Capture 0 buffer water mark." }, { col => 0, table => 1, text => "FULL_BUFFER_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "1= The shared buffer is dedicated to one capture only.", }, { col => 3, table => 1, text => " 0=DISABLE " }, { col => 3, table => 1, text => " 1=ENABLE " }, { col => 0, table => 1, text => "CAP0_ANC_VBI_QUAD_BUF" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Dual buffer " }, { col => 3, table => 1, text => " 1=Quaduple buffer " }, { col => 0, table => 1, text => "VID_BUFFER_RESET" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reset the buffer pointers." }, { col => 3, table => 1, text => " 0=NOT RESET " }, { col => 3, table => 1, text => " 1=RESET " }, { col => 0, table => 1, text => "CAP_SWAP" }, { col => 1, table => 1, text => "22:21" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Capture Port Swap control." }, { col => 0, table => 1, text => "CAP0_BUFFER_EMPTY (R)" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Capture 0's buffer empty status." }, { col => 3, table => 1, text => " 0=EMPTY " }, { col => 3, table => 1, text => " 1=NOT EMPTY " }, { col => 0, table => 1, text => "CAP_URGENT_EN" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x1" }, { col => undef, table => undef, text => "Enable urgent signal to MH when water mark is reached.", }, { col => undef, table => undef, text => "Video Capture port buffer control.", }, { col => "heading", table => 2, text => "CAP_INT_CNTL - RW - 32 bits - [GpuF0MMReg:0xB08]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP0_BUF0_INT_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture 0 Buffer 0 Interrupt enable." }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "CAP0_BUF0_EVEN_INT_EN" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture 0 Buffer 0 even frame Interrupt enable.", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, ], }, { num => 122, text => [ { col => 0, table => 0, text => "CAP0_BUF1_INT_EN" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 Buffer 1 Interrupt enable." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_BUF1_EVEN_INT_EN" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 Buffer 1 even frame Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_VBI0_INT_EN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 VBI Buffer 0 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_VBI1_INT_EN" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 VBI Buffer 1 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_ONESHOT_INT_EN" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 ONESHOT Buffer Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_ANC0_INT_EN" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 ANC Buffer 0 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_ANC1_INT_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 ANC Buffer 1 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_VBI2_INT_EN" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 VBI Buffer 2 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_VBI3_INT_EN" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 VBI Buffer 3 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_ANC2_INT_EN" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 ANC Buffer 2 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_ANC3_INT_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 ANC Buffer 3 Interrupt enable.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "CAP0_BUF_INT_MUX" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Wait for MH ack before setting capture interrupt.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Video Capture port interrupt control register", }, { col => undef, table => undef, text => "CAP_INT_STATUS - RW - 32 bits - [GpuF0MMReg:0xB0C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "CAP0_BUF0_INT (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read only. Buffer 0 interrupt status.", }, { col => undef, table => undef, text => " 0=No event " }, { col => undef, table => undef, text => " 1=Event has occurred, interrupting if enabled ", }, { col => undef, table => undef, text => "CAP0_BUF0_INT_AK (W)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Buf0 interrupt acknowledgment." }, { col => undef, table => undef, text => " 0=No effect " }, { col => undef, table => undef, text => " 1=Clear status " }, { col => undef, table => undef, text => "CAP0_BUF0_EVEN_INT (R)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read only. Buffer 0 even frame interrupt status.", }, { col => undef, table => undef, text => " 0=No event " }, { col => undef, table => undef, text => " 1=Event has occurred, interrupting if enabled ", }, { col => undef, table => undef, text => "CAP0_BUF0_EVEN_INT_AK (W)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Buf0 even frame buffer interrupt acknowledgment.", }, { col => undef, table => undef, text => " 0=No effect " }, { col => undef, table => undef, text => " 1=Clear status " }, { col => undef, table => undef, text => "CAP0_BUF1_INT (R)" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read only. Buffer 1 interrupt status.", }, { col => undef, table => undef, text => " 0=No event " }, { col => undef, table => undef, text => " 1=Event has occurred, interrupting if enabled ", }, { col => undef, table => undef, text => "CAP0_BUF1_INT_AK (W)" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Buf1 interrupt acknowledgment." }, { col => undef, table => undef, text => " 0=No effect " }, { col => undef, table => undef, text => " 1=Clear status " }, ], }, { num => 123, text => [ { col => 0, table => 0, text => "CAP0_BUF1_EVEN_INT (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. Buffer 1 even frame interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_BUF1_EVEN_INT_AK (W)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Buf1 even frame buffer interrupt acknowledgment.", }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_VBI0_INT (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. VBI buffer 0 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_VBI0_INT_AK (W)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VBI buffer 0 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_VBI1_INT (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. VBI buffer 1 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_VBI1_INT_AK (W)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VBI buffer 1 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_ONESHOT_INT (R)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. ONESHOT buffer interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_ONESHOT_INT_AK (W)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ONESHOT buffer interrupt acknowledgment.", }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_ANC0_INT (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. ANC buffer 0 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_ANC0_INT_AK (W)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ANC buffer 0 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_ANC1_INT (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. ANC buffer 1 nterrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_ANC1_INT_AK (W)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ANC buffer 1 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_VBI2_INT (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. VBI buffer 2 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_VBI2_INT_AK (W)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VBI buffer 2 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_VBI3_INT (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. VBI buffer 3 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_VBI3_INT_AK (W)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VBI buffer 3 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_ANC2_INT (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. ANC buffer 2 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_ANC2_INT_AK (W)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ANC buffer 2 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "CAP0_ANC3_INT (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. ANC buffer 3 interrupt status.", }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 0, text => "CAP0_ANC3_INT_AK (W)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ANC buffer 3 interrupt acknowledgment." }, { col => 3, table => 0, text => " 0=No effect " }, { col => undef, table => undef, text => " 1=Clear status " }, { col => undef, table => undef, text => "Capture port interrupt control." }, ], }, { num => 124, text => [ { col => "heading", table => 0, text => "CAP0_BUF0_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB20]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CAP_BUF0_OFFSET" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture Port 0 Buffer 0 starting address", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture Port 0 Buffer 0 starting address", }, { col => "heading", table => 1, text => "CAP0_BUF1_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB24]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_BUF1_OFFSET" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Capture Port 0 Buffer 1 starting address", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture Port 0 Buffer 1 starting address", }, { col => "heading", table => 2, text => "CAP0_BUF0_EVEN_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB28]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_BUF0_EVEN_OFFSET" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture Port 0 Buffer 0 even frame starting address", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture Port 0 Buffer 0 even frame starting address", }, { col => "heading", table => 3, text => "CAP0_BUF1_EVEN_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB2C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CAP_BUF1_EVEN_OFFSET" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Capture Port 0 Buffer 1 even frame starting address", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture Port 0 Buffer 1 even frame starting address", }, { col => "heading", table => 4, text => "CAP0_BUF_PITCH - RW - 32 bits - [GpuF0MMReg:0xB30]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CAP_BUF_PITCH" }, { col => 1, table => 4, text => "11:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Capture 0 buffer's pitch." }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 buffer's pitch." }, ], }, { num => 125, text => [ { col => "heading", table => 0, text => "CAP0_V_WINDOW - RW - 32 bits - [GpuF0MMReg:0xB34]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CAP_V_START" }, { col => 1, table => 0, text => "11:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Vertical window starting line number." }, { col => 0, table => 0, text => "CAP_V_END" }, { col => 1, table => 0, text => "27:16" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Vertical window end line number.", }, { col => undef, table => undef, text => "Capture 0's Vertical window." }, { col => "heading", table => 1, text => "CAP0_H_WINDOW - RW - 32 bits - [GpuF0MMReg:0xB38]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_H_START" }, { col => 1, table => 1, text => "11:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Horizontal window's start." }, { col => 0, table => 1, text => "CAP_H_WIDTH" }, { col => 1, table => 1, text => "27:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Horizontal window's width." }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0's Horizontal window." }, { col => "heading", table => 2, text => "CAP0_VBI0_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB3C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_VBI0_OFFSET" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture 0 VBI 0 buffer's starting address.", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 VBI 0 buffer's starting address.", }, { col => "heading", table => 3, text => "CAP0_VBI1_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB40]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CAP_VBI1_OFFSET" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Capture 0 VBI 1 buffer's starting address.", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 VBI 1 buffer's starting address.", }, { col => "heading", table => 4, text => "CAP0_VBI_V_WINDOW - RW - 32 bits - [GpuF0MMReg:0xB44]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CAP_VBI_V_START" }, { col => 1, table => 4, text => "11:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Capture 0 VBI's Vertical start." }, { col => 0, table => 4, text => "CAP_VBI_V_END" }, { col => 1, table => 4, text => "27:16" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "Capture 0 VBI's Vertical End." }, { col => undef, table => undef, text => "Capture 0 VBI's vertical window" }, { col => "heading", table => 5, text => "CAP0_VBI_H_WINDOW - RW - 32 bits - [GpuF0MMReg:0xB48]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "CAP_VBI_H_START" }, { col => 1, table => 5, text => "11:0" }, { col => 2, table => 5, text => "0x0" }, { col => 3, table => 5, text => "Capture 0 VBI's Horizontal start." }, ], }, { num => 126, text => [ { col => 0, table => 0, text => "CAP_VBI_H_WIDTH" }, { col => 1, table => 0, text => "27:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 VBI's Horizontal Width." }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 VBI's horizontal window", }, { col => "heading", table => 1, text => "CAP0_PORT_MODE_CNTL - RW - 32 bits - [GpuF0MMReg:0xB4C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_PORT_WIDTH" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Capture 0 port width." }, { col => 3, table => 1, text => " 0=8 bits " }, { col => 3, table => 1, text => " 1=16 bits " }, { col => 0, table => 1, text => "CAP_PORT_BYTE_USED" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "In 8 bit width mode, which byte used." }, { col => 3, table => 1, text => " 0=lower byte used " }, { col => 3, table => 1, text => " 1=upper byte used " }, { col => 0, table => 1, text => "CAP_DDR_MODE" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Capture DDR mode." }, { col => 3, table => 1, text => " 0=DDR mode off " }, { col => 3, table => 1, text => " 1=DDR mode on " }, { col => 0, table => 1, text => "CAP_DDR_SYNC" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Embedded sync words DDR mode." }, { col => 3, table => 1, text => " 0=Sync on rising edge " }, { col => 3, table => 1, text => " 1=Sync on both edges " }, { col => 0, table => 1, text => "MOBILE_DIS" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Mobile/Desktop configuration." }, { col => 3, table => 1, text => " 0=Mobile " }, { col => undef, table => undef, text => " 1=Desktop " }, { col => undef, table => undef, text => "Capture 0 mode control register.", }, { col => "heading", table => 2, text => "CAP0_TRIG_CNTL - RW - 32 bits - [GpuF0MMReg:0xB50]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_TRIGGER_R (R)" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Capture status." }, { col => 3, table => 2, text => " 0=capture complete " }, { col => 3, table => 2, text => " 1=capture pending " }, { col => 3, table => 2, text => " 2=capture in progress " }, { col => 0, table => 2, text => "CAP_TRIGGER_W (W)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Write only. Start capture next frame." }, { col => 3, table => 2, text => " 0=no action " }, { col => 3, table => 2, text => " 1=capture next field/frame " }, { col => 0, table => 2, text => "CAP_EN" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture 0 enable." }, { col => 3, table => 2, text => " 0=disable " }, { col => 3, table => 2, text => " 1=enable " }, { col => 0, table => 2, text => "CAP_VSYNC_CNT (R)" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. VSYNC counter." }, { col => 0, table => 2, text => "CAP_VSYNC_CLR" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Reset the VSYNC counter." }, { col => undef, table => undef, text => "Capture 0 trigger control." }, { col => "heading", table => 3, text => "CAP0_DEBUG - RW - 32 bits - [GpuF0MMReg:0xB54]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CAP_H_STATUS (R)" }, { col => 1, table => 3, text => "11:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Capture 0 Horizontal status." }, { col => 0, table => 3, text => "CAP_V_STATUS (R)" }, { col => 1, table => 3, text => "27:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Capture 0 vertical status." }, { col => 0, table => 3, text => "CAP_V_SYNC (R)" }, { col => 1, table => 3, text => 28 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Capture 0 VSYNC status." }, { col => undef, table => undef, text => "Capture 0 debug status register.", }, ], }, { num => 127, text => [ { col => "heading", table => 0, text => "CAP0_CONFIG - RW - 32 bits - [GpuF0MMReg:0xB58]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CAP_INPUT_MODE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Input mode." }, { col => 3, table => 0, text => " 0=OneShot trigger mode " }, { col => 3, table => 0, text => " 1=Enable continuous capture " }, { col => 0, table => 0, text => "CAP_START_FIELD" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Starting field." }, { col => 3, table => 0, text => " 0=Odd " }, { col => 3, table => 0, text => " 1=Even " }, { col => 0, table => 0, text => "CAP_START_BUF_R (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read only. Current starting buffer." }, { col => 3, table => 0, text => " 0=Buffer 0 " }, { col => 3, table => 0, text => " 1=Buffer 1 " }, { col => 0, table => 0, text => "CAP_START_BUF_W (W)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write only. Control starting buffer." }, { col => 3, table => 0, text => " 0=Buffer 0 " }, { col => 3, table => 0, text => " 1=Buffer 1 " }, { col => 0, table => 0, text => "CAP_BUF_TYPE" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Buffer type." }, { col => 3, table => 0, text => " 0=Field " }, { col => 3, table => 0, text => " 1=Alternating " }, { col => 3, table => 0, text => " 2=Frame " }, { col => 0, table => 0, text => "CAP_ONESHOT_MODE" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ONESHOT mode." }, { col => 3, table => 0, text => " 0=FIELD " }, { col => 3, table => 0, text => " 1=FRAME " }, { col => 0, table => 0, text => "CAP_BUF_MODE" }, { col => 1, table => 0, text => "8:7" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 buffer mode." }, { col => 3, table => 0, text => " 0=Single " }, { col => 3, table => 0, text => " 1=Double " }, { col => 3, table => 0, text => " 2=Triple " }, { col => 0, table => 0, text => "CAP_MIRROR_EN" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Capture 0 mirroring function enable." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Mirror " }, { col => 0, table => 0, text => "CAP_ONESHOT_MIRROR_EN" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ONESHOT buffer mirroring function enable.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Mirror " }, { col => 0, table => 0, text => "CAP_VIDEO_SIGNED_UV" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable conversion to signed value." }, { col => 3, table => 0, text => " 1=Convert to signed " }, { col => 0, table => 0, text => "CAP_ANC_DECODE_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ANC enable." }, { col => 3, table => 0, text => " 0=disable " }, { col => 3, table => 0, text => " 1=enable " }, { col => 0, table => 0, text => "CAP_VBI_EN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VBI enable." }, { col => 3, table => 0, text => " 0=disable " }, { col => 3, table => 0, text => " 1=enable " }, { col => 0, table => 0, text => "CAP_SOFT_PULL_DOWN_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Software pull down enable." }, { col => 3, table => 0, text => " 0=disable " }, { col => 3, table => 0, text => " 1=enable " }, { col => 0, table => 0, text => "CAP_VIP_EXTEND_FLAG_EN" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Extended flag enable." }, { col => 3, table => 0, text => " 0=DISABLE " }, { col => 3, table => 0, text => " 1=ENABLE " }, { col => 0, table => 0, text => "CAP_FAKE_FIELD_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Fake field enable." }, { col => 3, table => 0, text => " 0=DISABLE " }, { col => 3, table => 0, text => " 1=ENABLE " }, { col => 0, table => 0, text => "CAP_FIELD_START_LINE_DIFF" }, { col => 1, table => 0, text => "18:17" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Odd, Even frame line number differences.", }, { col => 3, table => 0, text => " 0=EQUAL " }, { col => 3, table => 0, text => " 1=ODD_ONE_MORE_LINE " }, { col => 3, table => 0, text => " 2=EVEN_ONE_MORE_LINE " }, { col => 0, table => 0, text => "CAP_HORZ_DOWN" }, { col => 1, table => 0, text => "20:19" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Horizontal decimation." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=x2 " }, { col => 3, table => 0, text => " 2=x4 " }, { col => 0, table => 0, text => "CAP_VERT_DOWN" }, { col => 1, table => 0, text => "22:21" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Vertical decimation." }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=x2 " }, { col => 3, table => 0, text => " 2=x4 " }, ], }, { num => 128, text => [ { col => undef, table => undef, text => "CAP_STREAM_FORMAT" }, { col => undef, table => undef, text => "25:23" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Video stream format." }, { col => undef, table => undef, text => " 0=Brooktree " }, { col => undef, table => undef, text => " 1=CCIR 656 " }, { col => undef, table => undef, text => " 2=ZV " }, { col => undef, table => undef, text => " 3=16bit VIP " }, { col => undef, table => undef, text => " 4=TRANSPORT STREAM " }, { col => undef, table => undef, text => "CAP_HDWNS_DEC" }, { col => undef, table => undef, text => 26 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Horizontal downscaler or decimator.", }, { col => undef, table => undef, text => " 0=downscaler " }, { col => undef, table => undef, text => " 1=decimator " }, { col => undef, table => undef, text => "CAP_IMAGE_FLIP_EN" }, { col => undef, table => undef, text => 27 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=Flip " }, { col => undef, table => undef, text => "CAP_ONESHOT_IMAGE_FLIP_EN" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=Flip " }, { col => undef, table => undef, text => "CAP_VIDEO_IN_FORMAT" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Input format." }, { col => undef, table => undef, text => " 0=YVYU422 " }, { col => undef, table => undef, text => " 1=VYUY422 " }, { col => undef, table => undef, text => "VBI_HORZ_DOWN" }, { col => undef, table => undef, text => "31:30" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=x2 " }, { col => undef, table => undef, text => " 2=x4 " }, { col => undef, table => undef, text => "Capture 0 configuration register.", }, { col => "heading", table => 1, text => "CAP0_ANC0_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB5C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_ANC0_OFFSET" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Starting address" }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 ANC 0 starting address.", }, { col => "heading", table => 2, text => "CAP0_ANC1_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB60]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_ANC1_OFFSET" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Starting address" }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 ANC 1 starting address.", }, { col => "heading", table => 3, text => "CAP0_ANC_H_WINDOW - RW - 32 bits - [GpuF0MMReg:0xB64]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CAP_ANC_WIDTH" }, { col => 1, table => 3, text => "11:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Window width." }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 ANC horizontal window.", }, { col => "heading", table => 4, text => "CAP0_VIDEO_SYNC_TEST - RW - 32 bits - [GpuF0MMReg:0xB68]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 129, text => [ { col => 0, table => 0, text => "CAP_TEST_VID_SOF" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Start of field." }, { col => 0, table => 0, text => "CAP_TEST_VID_EOF" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End of field." }, { col => 0, table => 0, text => "CAP_TEST_VID_EOL" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End of line." }, { col => 0, table => 0, text => "CAP_TEST_VID_FIELD" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Odd/Even field." }, { col => 3, table => 0, text => " 0=Even Field " }, { col => 3, table => 0, text => " 1=Odd Field " }, { col => 0, table => 0, text => "CAP_TEST_SYNC_EN" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Test sync enable." }, { col => 3, table => 0, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=Test Mode " }, { col => undef, table => undef, text => "Capture port 0 sync test." }, { col => "heading", table => 1, text => "CAP0_ONESHOT_BUF_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB6C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP_ONESHOT_BUF_OFFSET" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "ONESHOT buffer starting address." }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "ONESHOT buffer starting address.", }, { col => "heading", table => 2, text => "CAP0_BUF_STATUS - RW - 32 bits - [GpuF0MMReg:0xB70]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_PRE_VID_BUF (R)" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Previous capture buffer." }, { col => 0, table => 2, text => "CAP_CUR_VID_BUF (R)" }, { col => 1, table => 2, text => "3:2" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Current Capture buffer." }, { col => 0, table => 2, text => "CAP_PRE_FIELD (R)" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Previous field." }, { col => 0, table => 2, text => "CAP_CUR_FIELD (R)" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Current field." }, { col => 0, table => 2, text => "CAP_PRE_VBI_BUF (R)" }, { col => 1, table => 2, text => "7:6" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Previous VBI buffer." }, { col => 0, table => 2, text => "CAP_CUR_VBI_BUF (R)" }, { col => 1, table => 2, text => "9:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Current VBI buffer." }, { col => 0, table => 2, text => "CAP_VBI_BUF_STATUS (R)" }, { col => 1, table => 2, text => 10 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. VBI busy status." }, { col => 3, table => 2, text => " 0=done " }, { col => 3, table => 2, text => " 1=busy " }, { col => 0, table => 2, text => "CAP_PRE_ANC_BUF (R)" }, { col => 1, table => 2, text => "12:11" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Previous ANC buffer." }, { col => 0, table => 2, text => "CAP_CUR_ANC_BUF (R)" }, { col => 1, table => 2, text => "14:13" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Current ANC buffer." }, { col => 0, table => 2, text => "CAP_ANC_BUF_STATUS (R)" }, { col => 1, table => 2, text => 15 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Buffer busy status." }, { col => 3, table => 2, text => " 0=done " }, { col => 3, table => 2, text => " 1=busy " }, { col => 0, table => 2, text => "CAP_ANC_PRE_BUF_CNT (R)" }, { col => 1, table => 2, text => "27:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Buffer count." }, { col => 0, table => 2, text => "CAP_VIP_INC (R)" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Interlaced or not." }, { col => 3, table => 2, text => " 0=INTERLACED " }, { col => 3, table => 2, text => " 1=NON_INTERLACED " }, { col => 0, table => 2, text => "CAP_VIP_PRE_REPEAT_FIELD (R)" }, { col => 1, table => 2, text => 29 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Previous buffer is new/repeat field.", }, { col => 3, table => 2, text => " 0=new_field " }, { col => 3, table => 2, text => " 1=repeated_field " }, { col => 0, table => 2, text => "CAP_CAP_BUF_STATUS (R)" }, { col => 1, table => 2, text => 30 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read only. Capture buffer busy status." }, { col => 3, table => 2, text => " 0=done " }, { col => 3, table => 2, text => " 1=busy " }, { col => 0, table => 2, text => "CAP_VIP_STATUS_STROBE (R)" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0Read only. Status strobe changes polarity when there is a ", }, { col => undef, table => undef, text => "buffer change." }, { col => undef, table => undef, text => "Capture 0 buffer status." }, { col => undef, table => undef, text => "CAP0_ANC_BUF01_BLOCK_CNT - RW - 32 bits - [GpuF0MMReg:0xB74]", }, ], }, { num => 130, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CAP0_ANC_BUF0_BLOCK_CNT (R)" }, { col => 1, table => 0, text => "11:0" }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "CAP0_ANC_BUF1_BLOCK_CNT (R)" }, { col => 1, table => 0, text => "27:16" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "CAP0_ANC_BUF23_BLOCK_CNT - RW - 32 bits - [GpuF0MMReg:0xB7C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CAP0_ANC_BUF2_BLOCK_CNT (R)" }, { col => 1, table => 1, text => "11:0" }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "CAP0_ANC_BUF3_BLOCK_CNT (R)" }, { col => 1, table => 1, text => "27:16" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "CAP0_VBI2_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB80]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CAP_VBI2_OFFSET" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture 0 VBI 2 buffer's starting address.", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 VBI 2 buffer's starting address.", }, { col => "heading", table => 3, text => "CAP0_VBI3_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB84]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "CAP_VBI3_OFFSET" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Capture 0 VBI 3 buffer's starting address.", }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 VBI 3 buffer's starting address.", }, { col => "heading", table => 4, text => "CAP0_ANC2_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB88]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "CAP_ANC2_OFFSET" }, { col => 1, table => 4, text => "31:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Starting address" }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 ANC 2 starting address.", }, { col => "heading", table => 5, text => "CAP0_ANC3_OFFSET - RW - 32 bits - [GpuF0MMReg:0xB8C]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "CAP_ANC3_OFFSET" }, { col => 1, table => 5, text => "31:0" }, { col => 2, table => 5, text => "0x0" }, { col => 3, table => 5, text => "Starting address" }, { col => undef, table => undef, text => "NOTE: Bits 0:1 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Capture 0 ANC 3 starting address.", }, ], }, { num => 131, text => [ { col => undef, table => undef, text => "2.5.4" }, { col => undef, table => undef, text => "VIP Host Port DMA Registers" }, { col => undef, table => undef, text => "DMA_VIPH0_COMMAND - R - 32 bits - [GpuF0MMReg:0xA00]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "BYTE_COUNT" }, { col => undef, table => undef, text => "20:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Byte Count of transfer size." }, { col => undef, table => undef, text => "SWAP_CONTROL" }, { col => undef, table => undef, text => "25:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Endian's swap control." }, { col => undef, table => undef, text => " 0=No Swapping " }, { col => undef, table => undef, text => " 1=[15:0]=[31:16], [31:16]=[15:0] ", }, { col => undef, table => undef, text => " 2=[7:0]=[31:24], [15:8]=[23:16], [23:16]=[15:8], ", }, { col => undef, table => undef, text => "[31:24]=[7:0] " }, { col => undef, table => undef, text => " 3=Undefined " }, { col => undef, table => undef, text => "TRANSFER_SOURCE" }, { col => undef, table => undef, text => 26 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Address space of source data." }, { col => undef, table => undef, text => " 0=Transfer from memory " }, { col => undef, table => undef, text => " 1=Transfer from VIPH " }, { col => undef, table => undef, text => "TRANSFER_DEST" }, { col => undef, table => undef, text => 27 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Address space of destination data.", }, { col => undef, table => undef, text => " 0=Transfer to memory " }, { col => undef, table => undef, text => " 1=Transfer to VIPH " }, { col => undef, table => undef, text => "SOURCE_OFFSET_HOLD" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Hold the source address without increase.", }, { col => undef, table => undef, text => " 0=Increment " }, { col => undef, table => undef, text => " 1=Hold " }, { col => undef, table => undef, text => "DEST_OFFSET_HOLD" }, { col => undef, table => undef, text => 29 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Hold the destination address without increase.", }, { col => undef, table => undef, text => " 0=Increment " }, { col => undef, table => undef, text => " 1=Hold " }, { col => undef, table => undef, text => "INTERRUPT_DIS" }, { col => undef, table => undef, text => 30 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "End of DMA command table interrupt control.", }, { col => undef, table => undef, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=Disable the end of list interrupt ", }, { col => undef, table => undef, text => "END_OF_LIST_STATUS" }, { col => undef, table => undef, text => 31 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Status bit show the last command of the DMA table.", }, { col => undef, table => undef, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=End of Descriptor List " }, { col => undef, table => undef, text => "VIPH channel0 DMA command read back.", }, { col => "heading", table => 0, text => "DMA_VIPH1_COMMAND - R - 32 bits - [GpuF0MMReg:0xA04]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "BYTE_COUNT" }, { col => 1, table => 0, text => "20:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Byte Count of transfer size." }, { col => 0, table => 0, text => "SWAP_CONTROL" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Endian's swap control." }, { col => 3, table => 0, text => " 0=No Swapping " }, { col => 3, table => 0, text => " 1=[15:0]=[31:16], [31:16]=[15:0] " }, { col => 3, table => 0, text => " 2=[7:0]=[31:24], [15:8]=[23:16], [23:16]=[15:8], ", }, { col => 3, table => 0, text => "[31:24]=[7:0] " }, { col => 3, table => 0, text => " 3=Undefined " }, { col => 0, table => 0, text => "TRANSFER_SOURCE" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Address space of source data." }, { col => 3, table => 0, text => " 0=Transfer from memory " }, { col => 3, table => 0, text => " 1=Transfer from VIPH " }, { col => 0, table => 0, text => "TRANSFER_DEST" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Address space of destination data." }, { col => 3, table => 0, text => " 0=Transfer to memory " }, { col => 3, table => 0, text => " 1=Transfer to VIPH " }, { col => 0, table => 0, text => "SOURCE_OFFSET_HOLD" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Hold the source address without increase.", }, { col => 3, table => 0, text => " 0=Increment " }, { col => 3, table => 0, text => " 1=Hold " }, ], }, { num => 132, text => [ { col => 0, table => 0, text => "DEST_OFFSET_HOLD" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Hold the destination address without increase.", }, { col => 3, table => 0, text => " 0=Increment " }, { col => 3, table => 0, text => " 1=Hold " }, { col => 0, table => 0, text => "INTERRUPT_DIS" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End of DMA command table interrupt control.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable the end of list interrupt " }, { col => 0, table => 0, text => "END_OF_LIST_STATUS" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Status bit show the last command of the DMA table.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=End of Descriptor List " }, { col => undef, table => undef, text => "VIPH channel1 DMA command read back.", }, { col => "heading", table => 1, text => "DMA_VIPH2_COMMAND - R - 32 bits - [GpuF0MMReg:0xA08]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "BYTE_COUNT" }, { col => 1, table => 1, text => "20:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte Count of transfer size." }, { col => 0, table => 1, text => "SWAP_CONTROL" }, { col => 1, table => 1, text => "25:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Endian's swap control." }, { col => 3, table => 1, text => " 0=No Swapping " }, { col => 3, table => 1, text => " 1=[15:0]=[31:16], [31:16]=[15:0] " }, { col => 3, table => 1, text => " 2=[7:0]=[31:24], [15:8]=[23:16], [23:16]=[15:8], ", }, { col => 3, table => 1, text => "[31:24]=[7:0] " }, { col => 3, table => 1, text => " 3=Undefined " }, { col => 0, table => 1, text => "TRANSFER_SOURCE" }, { col => 1, table => 1, text => 26 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Address space of source data." }, { col => 3, table => 1, text => " 0=Transfer from memory " }, { col => 3, table => 1, text => " 1=Transfer from VIPH " }, { col => 0, table => 1, text => "TRANSFER_DEST" }, { col => 1, table => 1, text => 27 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Address space of destination data." }, { col => 3, table => 1, text => " 0=Transfer to memory " }, { col => 3, table => 1, text => " 1=Transfer to VIPH " }, { col => 0, table => 1, text => "SOURCE_OFFSET_HOLD" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Hold the source address without increase.", }, { col => 3, table => 1, text => " 0=Increment " }, { col => 3, table => 1, text => " 1=Hold " }, { col => 0, table => 1, text => "DEST_OFFSET_HOLD" }, { col => 1, table => 1, text => 29 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Hold the destination address without increase.", }, { col => 3, table => 1, text => " 0=Increment " }, { col => 3, table => 1, text => " 1=Hold " }, { col => 0, table => 1, text => "INTERRUPT_DIS" }, { col => 1, table => 1, text => 30 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "End of DMA command table interrupt control.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Disable the end of list interrupt " }, { col => 0, table => 1, text => "END_OF_LIST_STATUS" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Status bit show the last command of the DMA table.", }, { col => 3, table => 1, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=End of Descriptor List " }, { col => undef, table => undef, text => "VIPH channel2 DMA command read back.", }, { col => "heading", table => 2, text => "DMA_VIPH3_COMMAND - R - 32 bits - [GpuF0MMReg:0xA0C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "BYTE_COUNT" }, { col => 1, table => 2, text => "20:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Byte Count of transfer size." }, { col => 0, table => 2, text => "SWAP_CONTROL" }, { col => 1, table => 2, text => "25:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Endian's swap control." }, { col => 3, table => 2, text => " 0=No Swapping " }, { col => 3, table => 2, text => " 1=[15:0]=[31:16], [31:16]=[15:0] " }, { col => 3, table => 2, text => " 2=[7:0]=[31:24], [15:8]=[23:16], [23:16]=[15:8], ", }, { col => 3, table => 2, text => "[31:24]=[7:0] " }, { col => 3, table => 2, text => " 3=Undefined " }, { col => 0, table => 2, text => "TRANSFER_SOURCE" }, { col => 1, table => 2, text => 26 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Address space of source data." }, { col => 3, table => 2, text => " 0=Transfer from memory " }, { col => 3, table => 2, text => " 1=Transfer from VIPH " }, ], }, { num => 133, text => [ { col => 0, table => 0, text => "TRANSFER_DEST" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Address space of destination data." }, { col => 3, table => 0, text => " 0=Transfer to memory " }, { col => 3, table => 0, text => " 1=Transfer to VIPH " }, { col => 0, table => 0, text => "SOURCE_OFFSET_HOLD" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Hold the source address without increase.", }, { col => 3, table => 0, text => " 0=Increment " }, { col => 3, table => 0, text => " 1=Hold " }, { col => 0, table => 0, text => "DEST_OFFSET_HOLD" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Hold the destination address without increase.", }, { col => 3, table => 0, text => " 0=Increment " }, { col => 3, table => 0, text => " 1=Hold " }, { col => 0, table => 0, text => "INTERRUPT_DIS" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End of DMA command table interrupt control.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Disable the end of list interrupt " }, { col => 0, table => 0, text => "END_OF_LIST_STATUS" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Status bit show the last command of the DMA table.", }, { col => 3, table => 0, text => " 0=Normal " }, { col => undef, table => undef, text => " 1=End of Descriptor List " }, { col => undef, table => undef, text => "VIPH channel3 DMA command read back.", }, { col => "heading", table => 1, text => "DMA_VIPH_STATUS - R - 32 bits - [GpuF0MMReg:0xA10]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DMA_VIPH0_AVAIL" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "VIPH DMA channel 0 available job queue number.", }, { col => 0, table => 1, text => "DMA_VIPH1_AVAIL" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "VIPH DMA channel 1 available job queue number.", }, { col => 0, table => 1, text => "DMA_VIPH2_AVAIL" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "VIPH DMA channel 2 available job queue number.", }, { col => 0, table => 1, text => "DMA_VIPH3_AVAIL" }, { col => 1, table => 1, text => "15:12" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "VIPH DMA channel 3 available job queue number.", }, { col => 0, table => 1, text => "DMA_VIPH0_CURRENT" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 0 current active job queue number", }, { col => 0, table => 1, text => "DMA_VIPH1_CURRENT" }, { col => 1, table => 1, text => "19:18" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 1 current active job queue number", }, { col => 0, table => 1, text => "DMA_VIPH2_CURRENT" }, { col => 1, table => 1, text => "21:20" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 2 current active job queue number", }, { col => 0, table => 1, text => "DMA_VIPH3_CURRENT" }, { col => 1, table => 1, text => "23:22" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 3 current active job queue number", }, { col => 0, table => 1, text => "DMA_VIPH0_ACTIVE" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 0 active status." }, { col => 3, table => 1, text => " 0=All VIP0 queue transfers are all done ", }, { col => 3, table => 1, text => " 1=A VIP0 queue transfer is active " }, { col => 0, table => 1, text => "DMA_VIPH1_ACTIVE" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 1 active status." }, { col => 3, table => 1, text => " 0=All VIP1 queue transfers are all done ", }, { col => 3, table => 1, text => " 1=A VIP1 queue transfer is active " }, { col => 0, table => 1, text => "DMA_VIPH2_ACTIVE" }, { col => 1, table => 1, text => 26 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 2 active status." }, { col => 3, table => 1, text => " 0=All VIP2 queue transfers are all done ", }, { col => 3, table => 1, text => " 1=A VIP2 queue transfer is active " }, { col => 0, table => 1, text => "DMA_VIPH3_ACTIVE" }, { col => 1, table => 1, text => 27 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA channel 3 active status." }, { col => 3, table => 1, text => " 0=All VIP3 queue transfers are all done ", }, { col => 3, table => 1, text => " 1=A VIP3 queue transfer is active " }, { col => 0, table => 1, text => "VIP_RBBM_H0DMA_IDLE" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VIP DMA channel 0 is busy " }, { col => 3, table => 1, text => " 1=VIP DMA channel 0 is idle " }, { col => 0, table => 1, text => "VIP_RBBM_H1DMA_IDLE" }, { col => 1, table => 1, text => 29 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VIP DMA channel 1 is busy " }, { col => 3, table => 1, text => " 1=VIP DMA channel 1 is idle " }, { col => 0, table => 1, text => "VIP_RBBM_H2DMA_IDLE" }, { col => 1, table => 1, text => 30 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VIP DMA channel 2 is busy " }, { col => 3, table => 1, text => " 1=VIP DMA channel 2 is idle " }, { col => 0, table => 1, text => "VIP_RBBM_H3DMA_IDLE" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=VIP DMA channel 3 is busy " }, { col => undef, table => undef, text => " 1=VIP DMA channel 3 is idle " }, { col => undef, table => undef, text => "VIPH DMA channels status register.", }, { col => "heading", table => 2, text => "DMA_VIPH_MISC_CNTL - RW - 32 bits - [GpuF0MMReg:0xA14]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DMA_VIPH_READ_TIMER" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0xf" }, { col => 0, table => 2, text => "DMA_VIPH_READ_TIMEOUT_TO_PRIO" }, { col => 0, table => 2, text => "RITY_EN" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, ], }, { num => 134, text => [ { col => 0, table => 0, text => "DMA_VIPH_READ_TIMEOUT_STATUS " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Timeout " }, { col => 0, table => 0, text => "DMA_VIPH_URGENT_EN" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable urgent to MH if read times out ", }, { col => "heading", table => 1, text => "DMA_VIPH_CHUNK_0 - RW - 32 bits - [GpuF0MMReg:0xA18]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DMA_VIPH3_TABLE_SWAP" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 3 Endian swap control." }, { col => 3, table => 1, text => " 0=No swap " }, { col => 3, table => 1, text => " 1=8bit swap " }, { col => 3, table => 1, text => " 2=16bit swap " }, { col => 3, table => 1, text => " 3=reserved " }, { col => 0, table => 1, text => "DMA_VIPH2_TABLE_SWAP" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 2 Endian swap control." }, { col => 3, table => 1, text => " 0=No swap " }, { col => 3, table => 1, text => " 1=8bit swap " }, { col => 3, table => 1, text => " 2=16bit swap " }, { col => 3, table => 1, text => " 3=reserved " }, { col => 0, table => 1, text => "DMA_VIPH1_TABLE_SWAP" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 1 Endian swap control." }, { col => 3, table => 1, text => " 0=No swap " }, { col => 3, table => 1, text => " 1=8bit swap " }, { col => 3, table => 1, text => " 2=16bit swap " }, { col => 3, table => 1, text => " 3=reserved " }, { col => 0, table => 1, text => "DMA_VIPH0_TABLE_SWAP" }, { col => 1, table => 1, text => "7:6" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 0 Endian swap control." }, { col => 3, table => 1, text => " 0=No swap " }, { col => 3, table => 1, text => " 1=8bit swap " }, { col => 3, table => 1, text => " 2=16bit swap " }, { col => 3, table => 1, text => " 3=reserved " }, { col => 0, table => 1, text => "DMA_VIPH3_NOCHUNK" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 3 disregard chunk size" }, { col => 3, table => 1, text => " 0=Use chunk value " }, { col => 3, table => 1, text => " 1=Use infinity for the chunk value " }, { col => 0, table => 1, text => "DMA_VIPH2_NOCHUNK" }, { col => 1, table => 1, text => 29 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 2 disregard chunk size" }, { col => 3, table => 1, text => " 0=Use chunk value " }, { col => 3, table => 1, text => " 1=Use infinity for the chunk value " }, { col => 0, table => 1, text => "DMA_VIPH1_NOCHUNK" }, { col => 1, table => 1, text => 30 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 1 disregard chunk size" }, { col => 3, table => 1, text => " 0=Use chunk value " }, { col => 3, table => 1, text => " 1=Use infinity for the chunk value " }, { col => 0, table => 1, text => "DMA_VIPH0_NOCHUNK" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VIPH DMA Channel 0 disregard chunk size" }, { col => 3, table => 1, text => " 0=Use chunk value " }, { col => undef, table => undef, text => " 1=Use infinity for the chunk value ", }, { col => undef, table => undef, text => "VIP Host Port DMA Chunk control register.", }, { col => "heading", table => 2, text => "DMA_VIPH_CHUNK_1_VAL - RW - 32 bits - [GpuF0MMReg:0xA1C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DMA_VIP0_CHUNK" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xf" }, { col => 3, table => 2, text => "VIP Host Port DMA channel 0 Chunk size" }, { col => 0, table => 2, text => "DMA_VIP1_CHUNK" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0xf" }, { col => 3, table => 2, text => "VIP Host Port DMA channel 1 Chunk size" }, { col => 0, table => 2, text => "DMA_VIP2_CHUNK" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0xf" }, { col => 3, table => 2, text => "VIP Host Port DMA channel 2 Chunk size" }, { col => 0, table => 2, text => "DMA_VIP3_CHUNK" }, { col => 1, table => 2, text => "31:24" }, { col => 2, table => 2, text => "0xf" }, { col => undef, table => undef, text => "VIP Host Port DMA channel 3 Chunk size", }, { col => undef, table => undef, text => "VIP Host Port DMA Chunk size" }, ], }, { num => 135, text => [ { col => "heading", table => 0, text => "DMA_VIP0_TABLE_ADDR - W - 32 bits - [GpuF0MMReg:0xA20]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DMA_VIPH_TABLE_ADDR" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "This points to first entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 0 DMA table starting address", }, { col => "heading", table => 1, text => "DMA_VIP1_TABLE_ADDR - W - 32 bits - [GpuF0MMReg:0xA30]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DMA_VIPH_TABLE_ADDR" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "This points to first entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 1 DMA table starting address", }, { col => "heading", table => 2, text => "DMA_VIP2_TABLE_ADDR - W - 32 bits - [GpuF0MMReg:0xA40]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DMA_VIPH_TABLE_ADDR" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "This points to first entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 2 DMA table starting address", }, { col => "heading", table => 3, text => "DMA_VIP3_TABLE_ADDR - W - 32 bits - [GpuF0MMReg:0xA50]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DMA_VIPH_TABLE_ADDR" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "This points to first entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 3 DMA table starting address", }, { col => "heading", table => 4, text => "DMA_VIPH0_ACTIVE - R - 32 bits - [GpuF0MMReg:0xA24]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DMA_VIPH_TABLE_ADDR_ACT" }, { col => 1, table => 4, text => "31:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "This points to the current active entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 0 DMA Current table address", }, { col => undef, table => undef, text => "DMA_VIPH1_ACTIVE - R - 32 bits - [GpuF0MMReg:0xA34]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DMA_VIPH_TABLE_ADDR_ACT" }, { col => undef, table => undef, text => "31:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This points to the current active entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 1 DMA Current table address", }, { col => undef, table => undef, text => "DMA_VIPH2_ACTIVE - R - 32 bits - [GpuF0MMReg:0xA44]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 136, text => [ { col => 0, table => 0, text => "DMA_VIPH_TABLE_ADDR_ACT" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "This points to the current active entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 2 DMA Current table address", }, { col => "heading", table => 1, text => "DMA_VIPH3_ACTIVE - R - 32 bits - [GpuF0MMReg:0xA54]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DMA_VIPH_TABLE_ADDR_ACT" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "This points to the current active entry in the DMA table.", }, { col => undef, table => undef, text => "VIP Port 3 DMA Current table address", }, { col => "heading", table => 2, text => "DMA_VIPH_ABORT - RW - 32 bits - [GpuF0MMReg:0xA88]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DMA_VIPH0_ABORT_EN" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable abort action" }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Enable queue abort " }, { col => 0, table => 2, text => "DMA_VIPH1_ABORT_EN" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable abort action" }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Enable queue abort " }, { col => 0, table => 2, text => "DMA_VIPH2_ABORT_EN" }, { col => 1, table => 2, text => 11 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable abort action" }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Enable queue abort " }, { col => 0, table => 2, text => "DMA_VIPH3_ABORT_EN" }, { col => 1, table => 2, text => 15 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable abort action" }, { col => 3, table => 2, text => " 0=Normal " }, { col => 3, table => 2, text => " 1=Enable queue abort " }, { col => 0, table => 2, text => "DMA_VIPH0_RESET" }, { col => 1, table => 2, text => 20 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Soft reset. Reset the DMA and job queue.", }, { col => 0, table => 2, text => "DMA_VIPH1_RESET" }, { col => 1, table => 2, text => 21 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Soft reset. Reset the DMA and job queue.", }, { col => 0, table => 2, text => "DMA_VIPH2_RESET" }, { col => 1, table => 2, text => 22 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Soft reset. Reset the DMA and job queue.", }, { col => 0, table => 2, text => "DMA_VIPH3_RESET" }, { col => 1, table => 2, text => 23 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Soft reset. Reset the DMA and job queue.", }, { col => undef, table => undef, text => "VIP Host Port DMA abort control registers", }, ], }, { num => 137, text => [ { col => undef, table => undef, text => "2.5.5" }, { col => undef, table => undef, text => "General Purpose I/O Data and Control Registers", }, { col => "heading", table => 0, text => "GPIOPAD_STRENGTH - RW - 32 bits - [GpuF0MMReg:0x1794]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "GPIO_STRENGTH_SN" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x9" }, { col => 3, table => 0, text => "For NMOS of GPIOs." }, { col => 3, table => 0, text => " 0=For NMOS of GPIOs. " }, { col => 0, table => 0, text => "GPIO_STRENGTH_SP" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => "For PMOS of GPIOs." }, { col => undef, table => undef, text => " 0=For PMOS of GPIOs. " }, { col => undef, table => undef, text => "Pad strength for GPIOs" }, { col => "heading", table => 1, text => "GPIOPAD_MASK - RW - 32 bits - [GpuF0MMReg:0x1798]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GPIO_MASK" }, { col => 1, table => 1, text => "28:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "GPIO pads mask. Allows software to control the ", }, { col => 3, table => 1, text => "GPIO pad. POSSIBLE VALUES: 1 ", }, { col => 3, table => 1, text => "- Only software can control GPIO pad. 0 - ", }, { col => undef, table => undef, text => "Allows chip components to control GPIO pad.", }, { col => undef, table => undef, text => "GPIO pads mask register" }, { col => "heading", table => 2, text => "GPIOPAD_A - RW - 32 bits - [GpuF0MMReg:0x179C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GPIO_A" }, { col => 1, table => 2, text => "28:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "GPIO pads output. The value to be outputted to the pads if ", }, { col => undef, table => undef, text => "GPIO_EN is '1'." }, { col => undef, table => undef, text => "GPIO pads output register" }, { col => "heading", table => 3, text => "GPIOPAD_EN - RW - 32 bits - [GpuF0MMReg:0x17A0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "GPIO_EN" }, { col => 1, table => 3, text => "28:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "GPIO pads output enable. If 1, GPIO pad is in output ", }, { col => undef, table => undef, text => "mode. If 0, GPIO pad accepts inputs from pads.", }, { col => undef, table => undef, text => "GPIO pads output enable register", }, { col => "heading", table => 4, text => "GPIOPAD_Y - RW - 32 bits - [GpuF0MMReg:0x17A4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "GPIO_Y (R)" }, { col => 1, table => 4, text => "28:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "GPIO pads input (or the values on the GPIO pads).", }, { col => undef, table => undef, text => "GPIO pad input read back" }, ], }, { num => 138, text => [ { col => undef, table => undef, text => "2.5.6" }, { col => undef, table => undef, text => "VIP Miscellaneous Registers" }, { col => "heading", table => 0, text => "GPIOPAD_EXTERN_TRIG_CNTL - RW - 32 bits - [GpuF0MMReg:0x17C4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "EXTERN_TRIG_SEL" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Selects whether one of the GPIOs, or a signal from display ", }, { col => 3, table => 0, text => "is used for detecting an external trigger event:", }, { col => 3, table => 0, text => " 0= GPIO_0 " }, { col => 3, table => 0, text => " 1= GPIO_1 " }, { col => 3, table => 0, text => " 2= GPIO_2 " }, { col => 3, table => 0, text => " 3= GPIO_3 " }, { col => 3, table => 0, text => " 4= GPIO_4 " }, { col => 3, table => 0, text => " 5= GPIO_5 " }, { col => 3, table => 0, text => " 6= GPIO_6 " }, { col => 3, table => 0, text => " 7= GPIO_7 " }, { col => 3, table => 0, text => " 8= GPIO_8 " }, { col => 3, table => 0, text => " 9= GPIO_9 " }, { col => 3, table => 0, text => " 10= GPIO_10 " }, { col => 3, table => 0, text => " 11= GPIO_11 " }, { col => 3, table => 0, text => " 12= GPIO_12 " }, { col => 3, table => 0, text => " 13= GPIO_13 " }, { col => 3, table => 0, text => " 14= GPIO_14 " }, { col => 3, table => 0, text => " 15= GPIO_15 " }, { col => 3, table => 0, text => " 16= GPIO_16 " }, { col => 3, table => 0, text => " 17= GPIO_17 " }, { col => 3, table => 0, text => " 18= GPIO_18 " }, { col => 3, table => 0, text => " 19= GPIO_19 " }, { col => 3, table => 0, text => " 20= GPIO_20 " }, { col => 3, table => 0, text => " 21= Display pin " }, { col => 3, table => 0, text => " 22= Disable external trigger source event for both GPIO ", }, { col => 3, table => 0, text => "pad and Display pin " }, { col => 0, table => 0, text => "EXTERN_TRIG_CLR (W)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " Clearing External Trigger logic:" }, { col => 3, table => 0, text => " 0= Write 0 has no affect. " }, { col => 3, table => 0, text => " 1= Write 1 sets EXTERN_TRIG_READ to 0. ", }, { col => 0, table => 0, text => "EXTERN_TRIG_READ (R)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Checks the status of an external trigger event:", }, { col => 3, table => 0, text => " 0= No external trigger event occurred OR an external ", }, { col => 3, table => 0, text => "trigger event that has been acknowledged by writing to ", }, { col => 3, table => 0, text => "EXTERN_TRIG_CLR with a '1'. " }, { col => 3, table => 0, text => " 1= An external trigger event has occurred and is waiting ", }, { col => undef, table => undef, text => "to be acknowledged. " }, { col => undef, table => undef, text => "External Trigger register" }, { col => undef, table => undef, text => "VIPPAD_MASK - RW - 32 bits - [GpuF0MMReg:0xAC0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "VIPPAD_MASK_SCL" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: GPIO override for SCL. Mobile: GPIO override for ", }, { col => undef, table => undef, text => "GPIO[19]." }, { col => undef, table => undef, text => " 0=Pin not enabled for GPIO " }, { col => undef, table => undef, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => undef, table => undef, text => "VIPPAD_MASK_SDA" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: GPIO override for SDA. Mobile: GPIO override for ", }, { col => undef, table => undef, text => "GPIO[18]." }, { col => undef, table => undef, text => " 0=Pin not enabled for GPIO " }, { col => undef, table => undef, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => undef, table => undef, text => "VIPPAD_MASK_VHAD" }, { col => undef, table => undef, text => "3:2" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: GPIO override for VHAD[1:0]. Mobile: GPIO ", }, { col => undef, table => undef, text => "override for GPIO[23:22]." }, { col => undef, table => undef, text => " 0=Pin not enabled for GPIO " }, { col => undef, table => undef, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, ], }, { num => 139, text => [ { col => 0, table => 0, text => "VIPPAD_MASK_VPHCTL" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for VPHCTL. Mobile: GPIO ", }, { col => 3, table => 0, text => "override for GPIO[21]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => 3, table => 0, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => 0, table => 0, text => "VIPPAD_MASK_VIPCLK" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for VIPCLK. Mobile: GPIO override ", }, { col => 3, table => 0, text => "for GPIO[20]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => 3, table => 0, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => 0, table => 0, text => "VIPPAD_MASK_VID" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for VID[7:0]. Mobile: GPIO override ", }, { col => 3, table => 0, text => "for GPIO[34:27]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => 3, table => 0, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => 0, table => 0, text => "VIPPAD_MASK_VPCLK0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for VPCLK0. Mobile: GPIO ", }, { col => 3, table => 0, text => "override for GPIO[24]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => 3, table => 0, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => 0, table => 0, text => "VIPPAD_MASK_DVALID" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for DVALID. Mobile: GPIO override ", }, { col => 3, table => 0, text => "for GPIO[26]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => 3, table => 0, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => 0, table => 0, text => "VIPPAD_MASK_PSYNC" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: GPIO override for PSYNC. Mobile: GPIO override ", }, { col => 3, table => 0, text => "for GPIO[25]." }, { col => 3, table => 0, text => " 0=Pin not enabled for GPIO " }, { col => undef, table => undef, text => " 1=Pin enabled for GPIO. Normal function overridden. ", }, { col => undef, table => undef, text => "Desktop: Multimedia Interface GPIO Mask Control. Mobile: Additional GPIO Interface Mask Control", }, { col => "heading", table => 1, text => "VIPPAD_A - RW - 32 bits - [GpuF0MMReg:0xAC4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPPAD_A_SCL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Output for SCL. Mobile: Output for GPIO[19].", }, { col => 3, table => 1, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 3, table => 1, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 0, table => 1, text => "VIPPAD_A_SDA" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Output for SDA. Mobile: Output for GPIO[18].", }, { col => 3, table => 1, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 3, table => 1, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 0, table => 1, text => "VIPPAD_A_VHAD" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Output for VHAD[1:0]. Mobile: Output for ", }, { col => 3, table => 1, text => "GPIO[23:22]." }, { col => 3, table => 1, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 3, table => 1, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 0, table => 1, text => "VIPPAD_A_VPHCTL" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Output for VPHCTL. Mobile: Output for GPIO[21].", }, { col => 3, table => 1, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 3, table => 1, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 0, table => 1, text => "VIPPAD_A_VIPCLK" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Output for VIPCLK. Mobile: Output for GPIO[20].", }, { col => 3, table => 1, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, { col => 3, table => 1, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 1, text => "enabled. " }, ], }, { num => 140, text => [ { col => 0, table => 0, text => "VIPPAD_A_VID" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: Output for VID[7:0]. Mobile: Output for ", }, { col => 3, table => 0, text => "GPIO[34:27]." }, { col => 3, table => 0, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 3, table => 0, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 0, table => 0, text => "VIPPAD_A_VPCLK0" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: Output for VPCLK0. Mobile: Output for GPIO[24].", }, { col => 3, table => 0, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 3, table => 0, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 0, table => 0, text => "VIPPAD_A_DVALID" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: Output for DVALID. Mobile: Output for GPIO[26].", }, { col => 3, table => 0, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 3, table => 0, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 0, table => 0, text => "VIPPAD_A_PSYNC" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: Output for PSYNC. Mobile: Output for GPIO[25].", }, { col => 3, table => 0, text => " 0=GPIO output is low for this pin, if mask and output are ", }, { col => 3, table => 0, text => "enabled. " }, { col => 3, table => 0, text => " 1=GPIO output is high for this pin, if mask and output are ", }, { col => undef, table => undef, text => "enabled. " }, { col => undef, table => undef, text => "Desktop: Multimedia Interface GPIO Output Control; Mobile: Additional GPIO Interface Output Control", }, { col => undef, table => undef, text => "VIPPAD_EN - RW - 32 bits - [GpuF0MMReg:0xAC8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "VIPPAD_EN_SCL" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for SCL. Mobile: Output enable for ", }, { col => undef, table => undef, text => "GPIO[19]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_SDA" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for SDA. Mobile: Output enable for ", }, { col => undef, table => undef, text => "GPIO[18]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_VHAD" }, { col => undef, table => undef, text => "3:2" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for VHAD[1:0]. Mobile: Output ", }, { col => undef, table => undef, text => "enable for GPIO[23:22]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_VPHCTL" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for VPHCTL. Mobile: Output enable ", }, { col => undef, table => undef, text => "for GPIO[21]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_VIPCLK" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for VIPCLK. Mobile: Output enable ", }, { col => undef, table => undef, text => "for GPIO[20]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_VID" }, { col => undef, table => undef, text => "15:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for VID[7:0]. Mobile: Output enable ", }, { col => undef, table => undef, text => "for GPIO[34:27]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_VPCLK0" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for VPCLK0. Mobile: Output enable ", }, { col => undef, table => undef, text => "for GPIO[24]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "VIPPAD_EN_DVALID" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Desktop: Output enable for DVALID. Mobile: Output enable ", }, { col => undef, table => undef, text => "for GPIO[26]." }, { col => undef, table => undef, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, ], }, { num => 141, text => [ { col => 0, table => 0, text => "VIPPAD_EN_PSYNC" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desktop: Output enable for PSYNC. Mobile: Output enable ", }, { col => 3, table => 0, text => "for GPIO[25]." }, { col => 3, table => 0, text => " 0=GPIO output is disabled for this pin. ", }, { col => undef, table => undef, text => " 1=GPIO output is enabled for this pin. ", }, { col => undef, table => undef, text => "Desktop: Multimedia Interface GPIO Output Enable Control; Mobile: Additional GPIO Interface Output Enable Control", }, { col => "heading", table => 1, text => "VIPPAD_Y - R - 32 bits - [GpuF0MMReg:0xACC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VIPPAD_Y_SCL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of SCL. Mobile: Input readback of ", }, { col => 3, table => 1, text => "GPIO[19]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_SDA" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of SDA. Mobile: Input readback of ", }, { col => 3, table => 1, text => "GPIO[18]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_VHAD" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of VHAD[1:0]. Mobile: Input ", }, { col => 3, table => 1, text => "readback of GPIO[23:22]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_VPHCTL" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of VPHCTL. Mobile: Input ", }, { col => 3, table => 1, text => "readback of GPIO[21]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_VIPCLK" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of VIPCLK. Mobile: Input readback ", }, { col => 3, table => 1, text => "of GPIO[20]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_VID" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of VID. Mobile: Input readback of ", }, { col => 3, table => 1, text => "GPIO[34:27]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_VPCLK0" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of VPCLK0. Mobile: Input ", }, { col => 3, table => 1, text => "readback of GPIO[24]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_DVALID" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of DVALID. Mobile: Input readback ", }, { col => 3, table => 1, text => "of GPIO[26]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => 3, table => 1, text => " 1=This pin was high at time of read. ", }, { col => 0, table => 1, text => "VIPPAD_Y_PSYNC" }, { col => 1, table => 1, text => 18 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Desktop: Input readback of PSYNC. Mobile: Input readback ", }, { col => 3, table => 1, text => "of GPIO[25]." }, { col => 3, table => 1, text => " 0=This pin was low at time of read. " }, { col => undef, table => undef, text => " 1=This pin was high at time of read. ", }, { col => undef, table => undef, text => "Desktop: Multimedia Interface GPIO Input Readback; Mobile: Additional GPIO Interface Input Readback", }, { col => undef, table => undef, text => "VIPPAD_STRENGTH - RW - 32 bits - [GpuF0MMReg:0xAD0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "I2C_STRENGTH_SN" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x7" }, { col => undef, table => undef, text => "Desktop: NMOS of SCL and SDA. Mobile: NMOS of ", }, { col => undef, table => undef, text => "GPIO[19:18]." }, { col => undef, table => undef, text => "I2C_STRENGTH_SP" }, { col => undef, table => undef, text => "7:4" }, { col => undef, table => undef, text => "0x4" }, { col => undef, table => undef, text => "Desktop: PMOS of SCL and SDA. Mobile: PMOS of ", }, { col => undef, table => undef, text => "GPIO[19:18]." }, ], }, { num => 142, text => [ { col => 0, table => 0, text => "VIPHDAT_STRENGTH_SN" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Desktop: NMOS of VHAD[1:0] and VPHCTL. Mobile: ", }, { col => 3, table => 0, text => "NMOS of GPIO[23:21]." }, { col => 0, table => 0, text => "VIPHDAT_STRENGTH_SP" }, { col => 1, table => 0, text => "15:12" }, { col => 2, table => 0, text => "0x4" }, { col => 3, table => 0, text => "Desktop: PMOS of VHAD[1:0] and VPHCTL. Mobile: PMOS ", }, { col => 3, table => 0, text => "of GPIO[23:21]." }, { col => 0, table => 0, text => "VIPHCLK_STRENGTH_SN" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Desktop: NMOS of VIPCLK. Mobile: NMOS of GPIO[20].", }, { col => 0, table => 0, text => "VIPHCLK_STRENGTH_SP" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x4" }, { col => 3, table => 0, text => "Desktop: PMOS of VIPCLK. Mobile: PMOS of GPIO[20].", }, { col => 0, table => 0, text => "VIDCAP_STRENGTH_SN" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Desktop: NMOS of VID, VPCLK0, PSYNC, and DVALID. ", }, { col => 3, table => 0, text => "Mobile: NMOS of GPIO[34:24]." }, { col => 0, table => 0, text => "VIDCAP_STRENGTH_SP" }, { col => 1, table => 0, text => "31:28" }, { col => 2, table => 0, text => "0x4" }, { col => 3, table => 0, text => "Desktop: PMOS of VID, VPCLK0, PSYNC, and DVALID. ", }, { col => undef, table => undef, text => "Mobile: PMOS of GPIO[34:24]." }, { col => undef, table => undef, text => "Desktop: Multimedia Interface GPIO Output Driver Strength; Mobile: Additional GPIO Interface Output Driver Strength", }, { col => "heading", table => 1, text => "EXTERN_TRIG_CNTL - RW - 32 bits - [GpuF0MMReg:0xE54]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "EXTERN_TRIG_CLR (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "none" }, { col => 3, table => 1, text => "External Trigger Clear:" }, { col => 3, table => 1, text => "Write 0 has no affect." }, { col => 3, table => 1, text => "Write 1 sets the external trigger to 0." }, { col => 0, table => 1, text => "EXTERN_TRIG_READ (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "none" }, { col => 3, table => 1, text => "External Trigger Status:" }, { col => 3, table => 1, text => "0 - Indicates WAIT condition is active." }, { col => undef, table => undef, text => "1 - Indicates WAIT condition is not active.", }, { col => undef, table => undef, text => "External Trigger Control" }, { col => "heading", table => 2, text => "ROM_CNTL - RW - 32 bits - [GpuF0MMReg:0x1600]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SCK_OVERWRITE" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Overwirte the default SCK clock source." }, { col => 3, table => 2, text => " 0=SCK sourced from sclk. " }, { col => 3, table => 2, text => " 1=SCK sourced from crystal clock. " }, { col => 0, table => 2, text => "CLOCK_GATING_EN" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "ROM read controller dynamic clock gating enable.", }, { col => 3, table => 2, text => " 0=Software disable the dynamic clock going to the read ", }, { col => 3, table => 2, text => "controller " }, { col => 3, table => 2, text => " 1=Software enable the dynamic clock going to the read ", }, { col => 3, table => 2, text => "controller " }, { col => 0, table => 2, text => "CSB_ACTIVE_TO_SCK_SETUP_TIME" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "CSb active to SCK setup time. Programmable delay in ", }, { col => 3, table => 2, text => "number of SCK cycles." }, { col => 0, table => 2, text => "CSB_ACTIVE_TO_SCK_HOLD_TIME" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "CSb active to SCK hold time. Programmable delay in ", }, { col => 3, table => 2, text => "number of SCK cycles. Actual hold time is (this delay + one ", }, { col => 3, table => 2, text => "SCK cycle)." }, { col => 0, table => 2, text => "SCK_PRESCALE_REFCLK" }, { col => 1, table => 2, text => "27:24" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Programmable SCK divider when clock source is PCIE ", }, { col => 3, table => 2, text => "REFCLK." }, { col => 0, table => 2, text => "SCK_PRESCALE_CRYSTAL_CLK" }, { col => 1, table => 2, text => "31:28" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Programmable SCK divider when clock source is on-board ", }, { col => undef, table => undef, text => "crystal clock." }, { col => undef, table => undef, text => "ROM controller control registers.", }, { col => "heading", table => 3, text => "ROM_STATUS - R - 32 bits - [GpuF0MMReg:0x1608]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ROM_BUSY" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "The ROM SPI interface is busy doing transaction.", }, { col => undef, table => undef, text => "ROM controller status registers.", }, ], }, { num => 143, text => [ { col => "heading", table => 0, text => "ROM_INDEX - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0xA8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ROM_INDEX" }, { col => 1, table => 0, text => "23:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Address in the ROM aperture space. The ROM device ", }, { col => 3, table => 0, text => "physical address is calculated based on the ROM_START ", }, { col => 3, table => 0, text => "register, plus this ROM_INDEX field. The ROM controller ", }, { col => undef, table => undef, text => "will read 4 bytes starting from this address.", }, { col => undef, table => undef, text => "Address for indirect read access to ROM.", }, { col => "heading", table => 1, text => "ROM_DATA - R - 32 bits - [GpuF0MMReg,GpuIOReg:0xAC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ROM_DATA" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Four bytes of data from indirect read access to ROM.", }, { col => undef, table => undef, text => "Data from indirect read access to ROM.", }, { col => "heading", table => 2, text => "ROM_START - RW - 32 bits - [GpuF0MMReg:0x1614]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ROM_START" }, { col => 1, table => 2, text => "23:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "ROM device starting address that points to the starting of ", }, { col => 3, table => 2, text => "the ROM aperture. This is used by software to read the ", }, { col => 3, table => 2, text => "whole ROM device via ROM aperture when the device size ", }, { col => undef, table => undef, text => "is larger than the aperture size.", }, { col => undef, table => undef, text => "ROM device starting address that points to the starting of the ROM aperture. Default to 0x0.", }, ], }, { num => 144, text => [ { col => undef, table => undef, text => "2.6" }, { col => undef, table => undef, text => "Video Graphics Array (VGA) Registers", }, { col => undef, table => undef, text => "2.6.1" }, { col => undef, table => undef, text => "VGA Control/Status Registers" }, { col => "heading", table => 0, text => "GENMO_WT - W - 8 bits - [GpuF0MMReg,VGA_IO:0x3C2]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "GENMO_MONO_ADDRESS_B" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Monochrome emulation, regs at 0x3Bx ", }, { col => 3, table => 0, text => " 1=Color/Graphic emulation, regs at 0x3Dx ", }, { col => 0, table => 0, text => "VGA_RAM_EN" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "VGA_CKSEL" }, { col => 1, table => 0, text => "3:2" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=25.1744MHz (640 Pels) " }, { col => 3, table => 0, text => " 1=28.3212MHz (720 Pels) " }, { col => 3, table => 0, text => " 2=Reserved " }, { col => 3, table => 0, text => " 3=Reserved " }, { col => 0, table => 0, text => "ODD_EVEN_MD_PGSEL" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Selects odd (high) memory locations ", }, { col => 3, table => 0, text => " 1=Selects even (low) memory locations ", }, { col => 0, table => 0, text => "VGA_HSYNC_POL" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "VGA_VSYNC_POL" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "GENMO_RD - R - 8 bits - [GpuF0MMReg,VGA_IO:0x3CC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GENMO_MONO_ADDRESS_B" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Monochrome emulation, regs at 0x3Bx ", }, { col => 3, table => 1, text => " 1=Color/Graphic emulation, regs at 0x3Dx ", }, { col => 0, table => 1, text => "VGA_RAM_EN" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "VGA_CKSEL" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=25.1744MHz (640 Pels) " }, { col => 3, table => 1, text => " 1=28.3212MHz (720 Pels) " }, { col => 3, table => 1, text => " 2=Reserved " }, { col => 3, table => 1, text => " 3=Reserved " }, { col => 0, table => 1, text => "ODD_EVEN_MD_PGSEL" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Selects odd (high) memory locations ", }, { col => 3, table => 1, text => " 1=Selects even (low) memory locations ", }, { col => 0, table => 1, text => "VGA_HSYNC_POL" }, { col => 1, table => 1, text => "60x0" }, { col => 0, table => 1, text => "VGA_VSYNC_POL" }, { col => 1, table => 1, text => "70x0" }, { col => "heading", table => 2, text => "GENENB - R - 8 bits - [GpuF0MMReg,VGA_IO:0x3C3]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "BLK_IO_BASE" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, ], }, { num => 145, text => [ { col => "heading", table => 0, text => "GENFC_WT - W - 8 bits - [GpuF0MMReg:0x3BA] [GpuF0MMReg:0x3DA] [VGA_IO:0x3BA] [VGA_IO:0x3DA]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VSYNC_SEL_W" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Vertical sync select (write)." }, { col => 3, table => 0, text => " 0=Normal vertical sync " }, { col => 3, table => 0, text => " 1=Sync is 'vertical sync' ORed with 'vertical display ", }, { col => undef, table => undef, text => "enable' " }, { col => undef, table => undef, text => "Feature Control Register (Read)" }, { col => "heading", table => 1, text => "GENFC_RD - R - 8 bits - [GpuF0MMReg,VGA_IO:0x3CA]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VSYNC_SEL_R" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Veritcal sync select (read)." }, { col => 3, table => 1, text => " 0=Normal vertical sync " }, { col => 3, table => 1, text => " 1=Sync is 'vertical sync' ORed with 'vertical display ", }, { col => undef, table => undef, text => "enable' " }, { col => undef, table => undef, text => "Feature Control Regsiter (Read)" }, { col => "heading", table => 2, text => "GENS0 - R - 8 bits - [GpuF0MMReg,VGA_IO:0x3C2]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SENSE_SWITCH" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "DAC comparator read back. Used for monitor detection. ", }, { col => 3, table => 2, text => "Mirror of DAC_CMP_OUTPUT\@DAC_CNTL. See ", }, { col => 3, table => 2, text => "description there." }, { col => 0, table => 2, text => "CRT_INTR" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "CRT Interrupt:" }, { col => 3, table => 2, text => " 0=Vertical retrace interrupt is cleared ", }, { col => undef, table => undef, text => " 1=Vertical retrace interrupt is pending ", }, { col => undef, table => undef, text => "Input Status 0 Register" }, { col => "heading", table => 3, text => "GENS1 - R - 8 bits - [GpuF0MMReg:0x3BA] [GpuF0MMReg:0x3DA] [VGA_IO:0x3BA] [VGA_IO:0x3DA]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "NO_DISPLAY" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Display enable." }, { col => 3, table => 3, text => " 0=Enable " }, { col => 3, table => 3, text => " 1=Disable " }, { col => 0, table => 3, text => "VGA_VSTATUS" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Vertical Retrace Status." }, { col => 3, table => 3, text => " 0=Vertical retrace not active " }, { col => 3, table => 3, text => " 1=Vertical retrace active " }, { col => 0, table => 3, text => "PIXEL_READ_BACK" }, { col => 1, table => 3, text => "5:4" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Diagnostic bits 0, 1 respectively. " }, { col => 3, table => 3, text => "These two bits are connected to two of the eight colour ", }, { col => 3, table => 3, text => "outputs (P7:P0) of the attribute controller. Connections are ", }, { col => 3, table => 3, text => "controlled by ATTR12(5,4) as follows:" }, { col => 3, table => 3, text => " 0=P2,P0 " }, { col => 3, table => 3, text => " 1=P5,P4 " }, { col => 3, table => 3, text => " 2=P3,P1 " }, { col => undef, table => undef, text => " 3=P7,P6 " }, { col => undef, table => undef, text => "Input Status 1 Register" }, ], }, { num => 146, text => [ { col => undef, table => undef, text => "2.6.2" }, { col => undef, table => undef, text => "VGA DAC Control Registers" }, { col => "heading", table => 0, text => "DAC_DATA - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C9]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DAC_DATA" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "VGA Palette (DAC) Data. Use DAC_R_INDEX and ", }, { col => 3, table => 0, text => "DAC_W_INDEX to set read or write mode, and entry to ", }, { col => 3, table => 0, text => "access." }, { col => 3, table => 0, text => "Access order is Red, Green, Blue, and then auto-increment ", }, { col => 3, table => 0, text => "occurs to next entry." }, { col => undef, table => undef, text => "DAC_8BIT_EN controls whether 6 or 8 bit access.", }, { col => undef, table => undef, text => "VGA Palette (DAC) Data" }, { col => "heading", table => 1, text => "DAC_MASK - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C6]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DAC_MASK" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Masks off usage of individual palette index bits before pixel ", }, { col => 3, table => 1, text => "index is looked-up in the palette." }, { col => 3, table => 1, text => "0 = do not use this bit of the index" }, { col => 3, table => 1, text => "1 = use this bit of the index" }, { col => 3, table => 1, text => "Only has an effect in VGA emulation modes ", }, { col => 3, table => 1, text => "(CRTC_EXT_DISP_EN=0), not for VESA modes or ", }, { col => undef, table => undef, text => "extended display modes." }, { col => undef, table => undef, text => "Palette index mask for VGA emulation modes.", }, { col => "heading", table => 2, text => "DAC_R_INDEX - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C7]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DAC_R_INDEX" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Write: Sets the index for a palette (DAC) read operation. ", }, { col => 3, table => 2, text => "Index auto-increments after every third read of DAC_DATA.", }, { col => 3, table => 2, text => "Read: Indicates if palette in read or write mode.", }, { col => 3, table => 2, text => "0 = Palette in write mode (DAC_W_INDEX last written).", }, { col => 3, table => 2, text => "3 = Palette in read mode (DAC_R_INDEX last written).", }, { col => undef, table => undef, text => "Aslo see DAC_W_INDEX." }, { col => undef, table => undef, text => "Palette (DAC) Read Index" }, { col => "heading", table => 3, text => "DAC_W_INDEX - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DAC_W_INDEX" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Sets the index for a palette (DAC) write operation. Index ", }, { col => 3, table => 3, text => "auto-increments after every third write of DAC_DATA. Aslo ", }, { col => undef, table => undef, text => "see DAC_R_INDEX." }, { col => undef, table => undef, text => "Palette (DAC) Write Index" }, ], }, { num => 147, text => [ { col => undef, table => undef, text => "2.6.3" }, { col => undef, table => undef, text => "VGA Sequencer Registers" }, { col => "heading", table => 0, text => "SEQ8_IDX - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "SEQ_IDX" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "SEQ8_DATA - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C5]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEQ_DATA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "SEQ00 - RW - 8 bits - VGASEQIND:0x0", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEQ_RST0B" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Synchronous reset bit 0:" }, { col => 3, table => 2, text => " 0=Follows SEQ_RST1B " }, { col => 3, table => 2, text => " 1=Sequencer runs unless SEQ_RST1B=0 " }, { col => 0, table => 2, text => "SEQ_RST1B" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Synchronous reset bit 1:" }, { col => 3, table => 2, text => " 0=Disable character clock, display requests, and H/V ", }, { col => 3, table => 2, text => "syncs " }, { col => undef, table => undef, text => " 1=Sequencer runs unless SEQ_RST0B=0 ", }, { col => undef, table => undef, text => "Reset Register" }, { col => undef, table => undef, text => "SEQ01 - RW - 8 bits - VGASEQIND:0x1", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "SEQ_DOT8" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "8/9 Dot Clocks (Modes 1, 2, 3, and 7 use 9-dot characters. ", }, { col => undef, table => undef, text => "To change bit 0, GENVS(0) must be logical 0).", }, { col => undef, table => undef, text => " 0=9 dot char clock. Modes 0, 1, 2, 3 & 7 ", }, { col => undef, table => undef, text => " 1=8 dot char clock. " }, { col => undef, table => undef, text => "SEQ_SHIFT2" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Shift load bits." }, { col => undef, table => undef, text => " 0=Load video serializer every clock, if SEQ_SHIFT4=0 ", }, { col => undef, table => undef, text => " 1=Load video serializer every other clock, if ", }, { col => undef, table => undef, text => "SEQ_SHIFT4=0 " }, { col => undef, table => undef, text => "SEQ_PCLKBY2" }, { col => undef, table => undef, text => 3 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Dot Clock (typically, 320 and 360 horizontal modes use ", }, { col => undef, table => undef, text => "divide-by-2 to provide 40 column displays. To change this ", }, { col => undef, table => undef, text => "bit SEQ00[0:0] must be first set to zero.)).", }, { col => undef, table => undef, text => " 0=Dot clock is normal " }, { col => undef, table => undef, text => " 1=Dot clock is divided by 2 " }, { col => undef, table => undef, text => "SEQ_SHIFT4" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Shift load bits." }, { col => undef, table => undef, text => " 0=SEQ_SHIFT2 determines serializer loading ", }, { col => undef, table => undef, text => " 1=Load video serializer every fourth clock. Ignore ", }, { col => undef, table => undef, text => "SEQ_SHIFT2 " }, ], }, { num => 148, text => [ { col => undef, table => undef, text => "2.6.4" }, { col => undef, table => undef, text => "VGA CRT Registers" }, { col => 0, table => 0, text => "SEQ_MAXBW" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Screen off:" }, { col => 3, table => 0, text => " 0=Normal. Screen on " }, { col => 3, table => 0, text => " 1=Sreen off and blanked. CPU has uninterrupted access ", }, { col => undef, table => undef, text => "to frame buffer " }, { col => undef, table => undef, text => "Clock Mode Register" }, { col => "heading", table => 1, text => "SEQ02 - RW - 8 bits - VGASEQIND:0x2", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "SEQ_MAP0_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable write to memory map 0 " }, { col => 3, table => 1, text => " 1=Enable write to memory map 0 " }, { col => 0, table => 1, text => "SEQ_MAP1_EN" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable write to memory map 1 " }, { col => 3, table => 1, text => " 1=Enable write to memory map 1 " }, { col => 0, table => 1, text => "SEQ_MAP2_EN" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable write to memory map 2 " }, { col => 3, table => 1, text => " 1=Enable write to memory map 2 " }, { col => 0, table => 1, text => "SEQ_MAP3_EN" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable write to memory map 3 " }, { col => 3, table => 1, text => " 1=Enable write to memory map 3 " }, { col => "heading", table => 2, text => "SEQ03 - RW - 8 bits - VGASEQIND:0x3", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "SEQ_FONT_B1" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Character Map Select B Bit 1" }, { col => 0, table => 2, text => "SEQ_FONT_B2" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Character Map Select B Bit 2" }, { col => 0, table => 2, text => "SEQ_FONT_A1" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Character Map Select A Bit 1" }, { col => 0, table => 2, text => "SEQ_FONT_A2" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Character Map Select A Bit 2" }, { col => 0, table => 2, text => "SEQ_FONT_B0" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Character Map Select B Bit 0" }, { col => 0, table => 2, text => "SEQ_FONT_A0" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Character Map Select A Bit 0" }, { col => undef, table => undef, text => "Character Map Select Register" }, { col => "heading", table => 3, text => "SEQ04 - RW - 8 bits - VGASEQIND:0x4", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "SEQ_256K" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=64KB memory present. Has no effect since 256KB ", }, { col => 3, table => 3, text => "always available " }, { col => 3, table => 3, text => " 1=256KB memory present " }, { col => 0, table => 3, text => "SEQ_ODDEVEN" }, { col => 1, table => 3, text => 2 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Even CPU address (A0=0) accesses maps 0 and 2. ", }, { col => 3, table => 3, text => "Odd address accesses maps 1 and 3 " }, { col => 3, table => 3, text => " 1=Enables sequential access to maps for odd/even ", }, { col => 3, table => 3, text => "modes. SEQ02 (Map Mask) selects which maps are used ", }, { col => 0, table => 3, text => "SEQ_CHAIN" }, { col => 1, table => 3, text => 3 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Enables sequential access to maps. SEQ02 (Map ", }, { col => 3, table => 3, text => "Mask) selects which maps are used " }, { col => 3, table => 3, text => " 1=For 256 color modes. Map select by CPU address bits ", }, { col => 3, table => 3, text => "A1:A0 " }, ], }, { num => 149, text => [ { col => "heading", table => 0, text => "CRTC8_IDX - RW - 8 bits - [GpuF0MMReg:0x3B4] [GpuF0MMReg:0x3D4] [VGA_IO:0x3B4] [VGA_IO:0x3D4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VCRTC_IDX" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "CRTC8_DATA - RW - 8 bits - [GpuF0MMReg:0x3B5] [GpuF0MMReg:0x3D5] [VGA_IO:0x3B5] ", }, { col => "heading", table => 1, text => "[VGA_IO:0x3D5]" }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VCRTC_DATA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "CRT00 - RW - 8 bits - VGACRTIND:0x0", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "H_TOTAL" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "These bits define the active horizontal display in a scan line, ", }, { col => 3, table => 2, text => "including the retrace period. The value is five less than the ", }, { col => undef, table => undef, text => "total number of displayed characters in a scan line.", }, { col => undef, table => undef, text => "Horizontal Total Register" }, { col => "heading", table => 3, text => "CRT01 - RW - 8 bits - VGACRTIND:0x1", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "H_DISP_END" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "These bits define the active horizontal dispaly in a scan line. ", }, { col => 3, table => 3, text => "The value is one less than the total number of displayed ", }, { col => undef, table => undef, text => "characters in a scan line." }, { col => undef, table => undef, text => "Horizontal Display Enable End Register", }, { col => "heading", table => 4, text => "CRT02 - RW - 8 bits - VGACRTIND:0x2", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "H_BLANK_START" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "These bits define the horizontal character count that ", }, { col => 3, table => 4, text => "represents the character coune in the active display area ", }, { col => 3, table => 4, text => "plus the right borger. In other words, the count is from the ", }, { col => 3, table => 4, text => "start of active display to the start of triggering of the H ", }, { col => undef, table => undef, text => "blanking pulse." }, { col => undef, table => undef, text => "Start Horizontal Blanking Register", }, { col => "heading", table => 5, text => "CRT03 - RW - 8 bits - VGACRTIND:0x3", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, ], }, { num => 150, text => [ { col => 0, table => 0, text => "H_BLANK_END" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "H blanking bits 4-0 respectively. These are the five ", }, { col => 3, table => 0, text => "low-order bits (of six bits in total) of horizontal character ", }, { col => 3, table => 0, text => "count for triggering the end of the horizontal blanking pulse.", }, { col => 0, table => 0, text => "H_DE_SKEW" }, { col => 1, table => 0, text => "6:5" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Display-enable skew:" }, { col => 3, table => 0, text => " 0=0Skew " }, { col => 3, table => 0, text => " 1=1Skew " }, { col => 3, table => 0, text => " 2=2Skew " }, { col => 3, table => 0, text => " 3=3Skew " }, { col => 0, table => 0, text => "CR10CR11_R_DIS_B" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Comptibility Read:" }, { col => 3, table => 0, text => " 0=WrtOnlyToCRT10-11 " }, { col => undef, table => undef, text => " 1=WrtRdToCRT10-11 " }, { col => undef, table => undef, text => "End Horizontal Blanking Register", }, { col => undef, table => undef, text => "CRT04 - RW - 8 bits - VGACRTIND:0x4", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "H_SYNC_START" }, { col => undef, table => undef, text => "7:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "These bits define the horizontal character count at which ", }, { col => undef, table => undef, text => "the horizontal retrace pulse becomes active.", }, { col => undef, table => undef, text => "Start Horizontal Retrace Register", }, { col => "heading", table => 1, text => "CRT05 - RW - 8 bits - VGACRTIND:0x5", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "H_SYNC_END" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "H Retrace Bits (these are the 5-bit result from the sum of ", }, { col => 3, table => 1, text => "CRT0 plus the width of the horizontal retrace pulse, in ", }, { col => 3, table => 1, text => "character clock units)." }, { col => 0, table => 1, text => "H_SYNC_SKEW" }, { col => 1, table => 1, text => "6:5" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "H Retrace Delay bits (these two bits skew the horizontal ", }, { col => 3, table => 1, text => "retrace pulse)." }, { col => 0, table => 1, text => "H_BLANK_END_B5" }, { col => 1, table => 1, text => 7 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "H blocking end bit 5 (this is the bit of the 6-bit character ", }, { col => 3, table => 1, text => "count for the H blanking end pulse). The other five ", }, { col => undef, table => undef, text => "low-order bits are CRT03[4:0]." }, { col => undef, table => undef, text => "End Horizontal Retrace Register" }, { col => "heading", table => 2, text => "CRT06 - RW - 8 bits - VGACRTIND:0x6", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "V_TOTAL" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "These are the eight low-order bits of the 10-bit vertical total ", }, { col => 3, table => 2, text => "register. The 2 high-order bits are CRT07[5:0] in the CRTC ", }, { col => 3, table => 2, text => "overflow register. The value of this register represents the ", }, { col => 3, table => 2, text => "total number of H raster scans plus vertical retrace (active ", }, { col => undef, table => undef, text => "display, blanking), minus two scan lines.", }, { col => undef, table => undef, text => "Vertical Total Register" }, { col => "heading", table => 3, text => "CRT07 - RW - 8 bits - VGACRTIND:0x7", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "V_TOTAL_B8" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "V Total Bit 8 (CRT06). Bit 8 of 10 bit vertical count for V ", }, { col => 3, table => 3, text => "Total. For functional description see CRT06 register.", }, ], }, { num => 151, text => [ { col => 0, table => 0, text => "V_DISP_END_B8" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End V Display Bit 8 (CRT12). Bit 8 of 10-bit vertical count ", }, { col => 3, table => 0, text => "for V Display enable. For functional desription see CRT12 ", }, { col => 3, table => 0, text => "register." }, { col => 0, table => 0, text => "V_SYNC_START_B8" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Start V Retrace Bit 8 (CRT10). Bit 8 of 10-bit veritcal count ", }, { col => 3, table => 0, text => "for V Retrace start. For functional description see CRT10 ", }, { col => 3, table => 0, text => "register." }, { col => 0, table => 0, text => "V_BLANK_START_B8" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Start V Blanking Bit 8 (CRT15). Bit 8 of the 10-bit vertical ", }, { col => 3, table => 0, text => "count for V Blanking start. For functional description see ", }, { col => 3, table => 0, text => "CRT15 register." }, { col => 0, table => 0, text => "LINE_CMP_B8" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Line compare bit 8 (CRT18). Bit 8 of the 10-bit vertical ", }, { col => 3, table => 0, text => "count for line compare. For functional description see ", }, { col => 3, table => 0, text => "CRT18 register." }, { col => 0, table => 0, text => "V_TOTAL_B9" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "V Total Bit 9 (CRT06). Bit 9 of 10-bit vertical count for V ", }, { col => 3, table => 0, text => "Total. For functional description see CRT06 register.", }, { col => 0, table => 0, text => "V_DISP_END_B9" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "End V Display Bit 9 (CRT12). Bit 9 of 10-bit vertical count ", }, { col => 3, table => 0, text => "for V Display enable end (for functional description see ", }, { col => 3, table => 0, text => "CRT12 register)." }, { col => 0, table => 0, text => "V_SYNC_START_B9" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Start V Retrace Bit (CRT10). Bit 9 of 10-bit vertical count ", }, { col => 3, table => 0, text => "for V Retrace start. For functional description see CRT10 ", }, { col => undef, table => undef, text => "register." }, { col => undef, table => undef, text => "CRTC Overflow Register" }, { col => "heading", table => 1, text => "CRT08 - RW - 8 bits - VGACRTIND:0x8", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ROW_SCAN_START" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Preset row scan bit 4:0. This register is used for ", }, { col => 3, table => 1, text => "software-controlled vertical scrolling in text or graphics ", }, { col => 3, table => 1, text => "modes. The value specifies the first line to be scanned after ", }, { col => 3, table => 1, text => "a V retrace (in the next frame). Each H Retrace pulse ", }, { col => 3, table => 1, text => "increments the counter by 1, up to the maximum scan line ", }, { col => 3, table => 1, text => "value programmed by CRT09, then the counter is cleared.", }, { col => 0, table => 1, text => "BYTE_PAN" }, { col => 1, table => 1, text => "6:5" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Byte panning control bits 1 and 0 (respectively). Bits 6 and ", }, { col => 3, table => 1, text => "5 extend the capability of byte panning (shifting) by up to ", }, { col => 3, table => 1, text => "three characters (for description H_PEL Panning register ", }, { col => undef, table => undef, text => "ATTR13)." }, { col => undef, table => undef, text => "Preset Row Scan Register" }, { col => "heading", table => 2, text => "CRT09 - RW - 8 bits - VGACRTIND:0x9", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MAX_ROW_SCAN" }, { col => 1, table => 2, text => "4:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Maximum scan line bits. These bits define a value that is ", }, { col => 3, table => 2, text => "the actual number of scan line per character minus 1.", }, { col => 0, table => 2, text => "V_BLANK_START_B9" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Start V Blanking bit 9 (CRT15). Bit 9 of 10-bit veritcal count ", }, { col => 3, table => 2, text => "for line compare. For functional description see CRT18 ", }, { col => 3, table => 2, text => "register." }, { col => 0, table => 2, text => "LINE_CMP_B9" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Line Compare Bit 9 (CRT18). Bit 9 of 10-bit vertical count ", }, { col => 3, table => 2, text => "for line compare. For functional description see CRT18 ", }, { col => 3, table => 2, text => "register." }, { col => 0, table => 2, text => "DOUBLE_CHAR_HEIGHT" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "200/400 line scan. NOTE H/V display and blanking timings ", }, { col => 3, table => 2, text => "etc. (in CRT00-CRT06 registers) are not affected.", }, { col => 3, table => 2, text => " 0=200LineScan " }, { col => undef, table => undef, text => " 1=400LineScan " }, { col => undef, table => undef, text => "Maximum Scan Line Register" }, ], }, { num => 152, text => [ { col => "heading", table => 0, text => "CRT0A - RW - 8 bits - VGACRTIND:0xA", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "CURSOR_START" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Cursor start bits 4:0 (respectively). These bits define a ", }, { col => 3, table => 0, text => "value that is the starting scan line (on a character row) for ", }, { col => 3, table => 0, text => "the line cursor. The 5-bit value is equal to the actual ", }, { col => 3, table => 0, text => "number minus one. This value is used together with the ", }, { col => 3, table => 0, text => "Cursor End Bits CRT0B[4:0] to determine the height of the ", }, { col => 3, table => 0, text => "cursor. The cursor height in VGA does not wrap around (as ", }, { col => 3, table => 0, text => "in EGA) and is actually absent when the 'end' value is less ", }, { col => 3, table => 0, text => "than the 'start' value. In EGA when the 'end' value is less, ", }, { col => 3, table => 0, text => "the cursor is a full block cursor the same height as the ", }, { col => 3, table => 0, text => "character cell." }, { col => 0, table => 0, text => "CURSOR_DISABLE" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Cursor on/off." }, { col => 3, table => 0, text => " 0=on " }, { col => undef, table => undef, text => " 1=off " }, { col => undef, table => undef, text => "Cursor Start Register" }, { col => "heading", table => 1, text => "CRT0B - RW - 8 bits - VGACRTIND:0xB", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CURSOR_END" }, { col => 1, table => 1, text => "4:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Cursor End Bits 4-0, respectively.- These bits define the ", }, { col => 3, table => 1, text => "ending scan row (on a character line) for the line cursor. In ", }, { col => 3, table => 1, text => "EGA, this 5-bit value is equal to the actual number of lines ", }, { col => 3, table => 1, text => "plus one.- The cursor height in VGA does not wrap around ", }, { col => 3, table => 1, text => "(as in EGA) and is actually absent when the 'end' value is ", }, { col => 3, table => 1, text => "less than the 'start' value. In EGA when the 'end' value is ", }, { col => 3, table => 1, text => "less, the cursor is a full block cursor the same height as the ", }, { col => 3, table => 1, text => "character cell." }, { col => 0, table => 1, text => "CURSOR_SKEW" }, { col => 1, table => 1, text => "6:5" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Cursor Skew Bits 1 and 0, respectively.- These bits define ", }, { col => 3, table => 1, text => "the number of characters the cursor is to be shifted to the ", }, { col => 3, table => 1, text => "right (skewed) from the character pointed at by the cursor ", }, { col => 3, table => 1, text => "location (registers CRT0E and CRT0F), in VGA mode. ", }, { col => undef, table => undef, text => "Skew values when in EGA mode are enclosed in brackets.", }, { col => undef, table => undef, text => "Cursor End Register" }, { col => "heading", table => 2, text => "CRT0C - RW - 8 bits - VGACRTIND:0xC", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DISP_START" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "SA bits 15:8-These are the eight high-order bits of the 16-bit ", }, { col => 3, table => 2, text => "display buffer start location. The low order bits are ", }, { col => 3, table => 2, text => "contained in CRT0D.-In split screen mode, CRT0C = ", }, { col => 3, table => 2, text => "CRT0D point to the starting location of screen A (top half.) ", }, { col => undef, table => undef, text => "The starting address for screen B is always zero.", }, { col => undef, table => undef, text => "Start Address (High Byte) Register", }, { col => undef, table => undef, text => "CRT0D - RW - 8 bits - VGACRTIND:0xD", }, ], }, { num => 153, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DISP_START" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "SA bits 7:0- These are the eight low-order bits of the 16-bit ", }, { col => 3, table => 0, text => "display buffer start location. The high-order bits are ", }, { col => 3, table => 0, text => "contained in CRT0C. - In split creen mode, CRT0C + ", }, { col => 3, table => 0, text => "CRT0D points to the starting location of screen A (top half.) ", }, { col => undef, table => undef, text => "The starting address for screen B is always zero.", }, { col => undef, table => undef, text => "Start Address (Low Byte) Register", }, { col => "heading", table => 1, text => "CRT0E - RW - 8 bits - VGACRTIND:0xE", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CURSOR_LOC_HI" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "CA bits 15:8- These are the eight high-order bits of the 16 ", }, { col => 3, table => 1, text => "bit cursor start address. The low-order CA bits are ", }, { col => 3, table => 1, text => "contained in CRT0F. This address is relative to the start of ", }, { col => 3, table => 1, text => "physical display memory address pointed to by CRT0C + ", }, { col => 3, table => 1, text => "CRT0D. In other words, if CRT0C + CRT0D is changed, ", }, { col => undef, table => undef, text => "the cursor still pints to the same character as before.", }, { col => undef, table => undef, text => "Cursor Location (High Byte) Register", }, { col => "heading", table => 2, text => "CRT0F - RW - 8 bits - VGACRTIND:0xF", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "CURSOR_LOC_LO" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "CA bits 7:0- These are the eight low-order bits of the 16 bit ", }, { col => 3, table => 2, text => "cursor start address. The high-order CA bits are contained ", }, { col => 3, table => 2, text => "in CRT0E. This address is relative to the start of physical ", }, { col => 3, table => 2, text => "display memory address pointed to by CRT0C + CRT0D. In ", }, { col => 3, table => 2, text => "other words, if CRT0C + T0D is changed, the cursor still ", }, { col => undef, table => undef, text => "points to the same character as before", }, { col => undef, table => undef, text => "Cursor Location (Low Byte) Register", }, { col => "heading", table => 3, text => "CRT10 - RW - 8 bits - VGACRTIND:0x10", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "V_SYNC_START" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Bits CRT10[7:0] are the eight low-order bits of the 10-bit ", }, { col => 3, table => 3, text => "vertical retrace start count. The two high-order bits are ", }, { col => 3, table => 3, text => "CRTt07[2:7], located in the CRTC overflow register.- These ", }, { col => 3, table => 3, text => "bits define the horizontal scan count that triggers the V ", }, { col => undef, table => undef, text => "retrace pulse." }, { col => undef, table => undef, text => "Start Vertical Retrace Register" }, { col => "heading", table => 4, text => "CRT11 - RW - 8 bits - VGACRTIND:0x11", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "V_SYNC_END" }, { col => 1, table => 4, text => "3:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "V Retrace End Bits 3-0- Bits CRT11[0:3] define the ", }, { col => 3, table => 4, text => "horizontal scan count that triggers the end of the V Retrace ", }, { col => 3, table => 4, text => "pulse." }, ], }, { num => 154, text => [ { col => 0, table => 0, text => "V_INTR_CLR" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "V Retrace Interrupt Set:" }, { col => 3, table => 0, text => " 0=VRetraceIntCleared " }, { col => 3, table => 0, text => " 1=Not Cleared " }, { col => 0, table => 0, text => "V_INTR_EN" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "V Retrace Interrupt Disabled:" }, { col => 3, table => 0, text => " 0=VRetraceIntEna " }, { col => 3, table => 0, text => " 1=Disable " }, { col => 0, table => 0, text => "SEL5_REFRESH_CYC" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=3 DRAM Refresh/Horz Line " }, { col => 3, table => 0, text => " 1=5 DRAM Refresh/Horz Line " }, { col => 0, table => 0, text => "C0T7_WR_ONLY" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write Protect (CRT00-CRT06). All register bits except ", }, { col => 3, table => 0, text => "CRTO7[4] are write protected." }, { col => 3, table => 0, text => " 0=EnaWrtToCRT00-07 " }, { col => undef, table => undef, text => " 1=C0T7B4WrtOnly " }, { col => undef, table => undef, text => "End Vertical Retrace Register" }, { col => "heading", table => 1, text => "CRT12 - RW - 8 bits - VGACRTIND:0x12", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "V_DISP_END" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "These are the eight low-order bits of the 10-bit register ", }, { col => 3, table => 1, text => "containing the horizontal scan count indicating where the ", }, { col => 3, table => 1, text => "active display on the screen should end. The high-order ", }, { col => undef, table => undef, text => "bits are CRT07 [1:6] in the CRT overflow register.", }, { col => undef, table => undef, text => "Vertical Display Enable End Register", }, { col => "heading", table => 2, text => "CRT13 - RW - 8 bits - VGACRTIND:0x13", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DISP_PITCH" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "- These bits define an offset value, equal to the logical line ", }, { col => 3, table => 2, text => "width of the screen (from the first character of the current ", }, { col => 3, table => 2, text => "line to the first character of the next line).- Memory ", }, { col => 3, table => 2, text => "organization is dependent on the video mode. Bit CRT17[6] ", }, { col => 3, table => 2, text => "selects byte or word mode. Bit CRT14[6], which overrides ", }, { col => 3, table => 2, text => "the byte/word mode setting, selects Double-Word mode ", }, { col => 3, table => 2, text => "when it is logical one.- The first character of the next line is ", }, { col => 3, table => 2, text => "specified by the start address (CRT0C + CRT0D) plus the ", }, { col => 3, table => 2, text => "offset. The offset for byte mode is 2x CRT13; for word ", }, { col => undef, table => undef, text => "mode, 4x; for double word mode 8x.", }, { col => undef, table => undef, text => "Offset Register" }, { col => "heading", table => 3, text => "CRT14 - RW - 8 bits - VGACRTIND:0x14", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "UNDRLN_LOC" }, { col => 1, table => 3, text => "4:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "ADDR_CNT_BY4" }, { col => 1, table => 3, text => 5 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Char. Clock " }, { col => 3, table => 3, text => " 1=CountBy4 " }, { col => 0, table => 3, text => "DOUBLE_WORD" }, { col => 1, table => 3, text => 6 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Disable " }, { col => 3, table => 3, text => " 1=DoubleWordMdEna " }, ], }, { num => 155, text => [ { col => "heading", table => 0, text => "CRT15 - RW - 8 bits - VGACRTIND:0x15", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "V_BLANK_START" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "These are the eight low-order bits of the 10-bit vertical ", }, { col => 3, table => 0, text => "blanking start register. Bit 9 is CRT09[5]; bit 8 is CRT07[3]- ", }, { col => 3, table => 0, text => "The 10 bits specify the starting location of the vertical ", }, { col => 3, table => 0, text => "blaning pulse, in units of horizontal scan lines. The value is ", }, { col => undef, table => undef, text => "equal to the actual number of displayed lines minus one.", }, { col => undef, table => undef, text => "Start Vertical Blanking Register", }, { col => "heading", table => 1, text => "CRT16 - RW - 8 bits - VGACRTIND:0x16", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "V_BLANK_END" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "These bits define the point at which to trigger the end of the ", }, { col => 3, table => 1, text => "vertical blanking pulse. The location is specified in units of ", }, { col => 3, table => 1, text => "horizontal scan lines.- The value to be storeed in this ", }, { col => 3, table => 1, text => "register is the seven low-order bits of the sum of 'pulse ", }, { col => 3, table => 1, text => "width count' plus the content of Start Vertical Blanking ", }, { col => undef, table => undef, text => "register (CRT15) minus one." }, { col => undef, table => undef, text => "End Vertical Blanking Register" }, { col => "heading", table => 2, text => "CRT17 - RW - 8 bits - VGACRTIND:0x17", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "RA0_AS_A13B" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "RA1_AS_A14B" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "VCOUNT_BY2" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "ADDR_CNT_BY2" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "WRAP_A15TOA0" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 0, table => 2, text => "BYTE_MODE" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=WordMode " }, { col => 3, table => 2, text => " 1=ByteMode " }, { col => 0, table => 2, text => "CRTC_SYNC_EN" }, { col => 1, table => 2, text => 7 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable HVSync " }, { col => 3, table => 2, text => " 1=EnaHVSync " }, { col => undef, table => undef, text => "CRT18 - RW - 8 bits - VGACRTIND:0x18", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "LINE_CMP" }, { col => undef, table => undef, text => "7:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "- These bits are the eight low-order of the 10-bit line ", }, { col => undef, table => undef, text => "compare register. Bit 8 is CRT07[4], bit 9 is CRT09[6]. The ", }, { col => undef, table => undef, text => "value of this register is used to disable scrolling on a portion ", }, { col => undef, table => undef, text => "of the display screen, as when split screen is active. When ", }, { col => undef, table => undef, text => "the vertical counter reaches this value, the memory address ", }, { col => undef, table => undef, text => "and row scan counters are cleared.- The screen area above ", }, { col => undef, table => undef, text => "the line specified by the register is commonly called screen ", }, { col => undef, table => undef, text => "A. The screen below is screen B. Screen B cannot be ", }, { col => undef, table => undef, text => "scrolled, but it can panned only together with screen A, ", }, { col => undef, table => undef, text => "controlled by the PEL panning compatibility bit ATTR10[5]. ", }, { col => undef, table => undef, text => "(For a description of this control bit see ATTR10[5].)", }, { col => undef, table => undef, text => "Line Compare Register" }, ], }, { num => 156, text => [ { col => undef, table => undef, text => "2.6.5" }, { col => undef, table => undef, text => "VGA Graphics Registers" }, { col => "heading", table => 0, text => "CRT1E - R - 8 bits - VGACRTIND:0x1E", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "GRPH_DEC_RD1" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "CRT1F - R - 8 bits - VGACRTIND:0x1F", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GRPH_DEC_RD0" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "CRT22 - R - 8 bits - VGACRTIND:0x22", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GRPH_LATCH_DATA" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "GRPH8_IDX - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3CE]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "GRPH_IDX" }, { col => 1, table => 3, text => "3:0" }, { col => 2, table => 3, text => "0x0" }, { col => "heading", table => 4, text => "GRPH8_DATA - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3CF]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "GRPH_DATA" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "GRA00 - RW - 8 bits - VGAGRPHIND:0x0", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "GRPH_SET_RESET0" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "GRPH_SET_RESET1" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, ], }, { num => 157, text => [ { col => 0, table => 0, text => "GRPH_SET_RESET2" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 0, table => 0, text => "GRPH_SET_RESET3" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "GRA01 - RW - 8 bits - VGAGRPHIND:0x1", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GRPH_SET_RESET_ENA0" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "GRPH_SET_RESET_ENA1" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "GRPH_SET_RESET_ENA2" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 0, table => 1, text => "GRPH_SET_RESET_ENA3" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => "heading", table => 2, text => "GRA02 - RW - 8 bits - VGAGRPHIND:0x2", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GRPH_CCOMP" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => "heading", table => 3, text => "GRA03 - RW - 8 bits - VGAGRPHIND:0x3", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "GRPH_ROTATE" }, { col => 1, table => 3, text => "2:0" }, { col => 2, table => 3, text => "0x0" }, { col => 0, table => 3, text => "GRPH_FN_SEL" }, { col => 1, table => 3, text => "4:3" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=Replace " }, { col => 3, table => 3, text => " 1=AND " }, { col => 3, table => 3, text => " 2=OR " }, { col => 3, table => 3, text => " 3=XOR " }, { col => "heading", table => 4, text => "GRA04 - RW - 8 bits - VGAGRPHIND:0x4", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "GRPH_RMAP" }, { col => 1, table => 4, text => "1:0" }, { col => 2, table => 4, text => "0x0" }, { col => "heading", table => 5, text => "GRA05 - RW - 8 bits - VGAGRPHIND:0x5", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "GRPH_WRITE_MODE" }, { col => 1, table => 5, text => "1:0" }, { col => 2, table => 5, text => "0x0" }, { col => 3, table => 5, text => " 0=Write mode 0 " }, { col => 3, table => 5, text => " 1=Write mode 1 " }, { col => 3, table => 5, text => " 2=Write mode 2 " }, { col => 3, table => 5, text => " 3=Write mode 3 " }, { col => 0, table => 5, text => "GRPH_READ1" }, { col => 1, table => 5, text => 3 }, { col => 2, table => 5, text => "0x0" }, { col => 3, table => 5, text => " 0=Read mode 0, byte oriented " }, { col => 3, table => 5, text => " 1=Read mode 1, pixel oriented " }, ], }, { num => 158, text => [ { col => undef, table => undef, text => "2.6.6" }, { col => undef, table => undef, text => "VGA Attribute Registers" }, { col => 0, table => 0, text => "CGA_ODDEVEN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable Odd/Even Addressing " }, { col => 3, table => 0, text => " 1=Enable Odd/Even Addressing " }, { col => 0, table => 0, text => "GRPH_OES" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Linear shift mode " }, { col => 3, table => 0, text => " 1=Tiled shift mode " }, { col => 0, table => 0, text => "GRPH_PACK" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Use shift register mode as per GRPH_OES ", }, { col => 3, table => 0, text => " 1=256 color mode, read as packed pixels, ignore ", }, { col => 3, table => 0, text => "GRPH_OES " }, { col => "heading", table => 1, text => "GRA06 - RW - 8 bits - VGAGRPHIND:0x6", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GRPH_GRAPHICS" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Alpha Numeric Mode " }, { col => 3, table => 1, text => " 1=Graphics Mode " }, { col => 0, table => 1, text => "GRPH_ODDEVEN" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Chain Odd maps to Even " }, { col => 0, table => 1, text => "GRPH_ADRSEL" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=A0000-128K " }, { col => 3, table => 1, text => " 1=A0000-64K " }, { col => 3, table => 1, text => " 2=B0000-32K " }, { col => 3, table => 1, text => " 3=B8000-32K " }, { col => "heading", table => 2, text => "GRA07 - RW - 8 bits - VGAGRPHIND:0x7", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "GRPH_XCARE0" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore map 0 " }, { col => 3, table => 2, text => " 1=Use map 0 for read mode 1 " }, { col => 0, table => 2, text => "GRPH_XCARE1" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore map 1 " }, { col => 3, table => 2, text => " 1=Use map 1 for read mode 1 " }, { col => 0, table => 2, text => "GRPH_XCARE2" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore map 2 " }, { col => 3, table => 2, text => " 1=Use map 2 for read mode 1 " }, { col => 0, table => 2, text => "GRPH_XCARE3" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Ignore map 3 " }, { col => 3, table => 2, text => " 1=Use map 3 for read mode 1 " }, { col => "heading", table => 3, text => "GRA08 - RW - 8 bits - VGAGRPHIND:0x8", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "GRPH_BMSK" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "ATTRX - RW - 8 bits - [GpuF0MMReg,VGA_IO:0x3C0]", }, ], }, { num => 159, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_IDX" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "ATTR Index. This index points to one of the internal ", }, { col => 3, table => 0, text => "registers of the attribute controller (ATTR) at addresses ", }, { col => 3, table => 0, text => "0x3C1/0x3C0, for the next ATTR read/write operation. ", }, { col => 3, table => 0, text => "Since both the index and data registers are at the same I/O, ", }, { col => 3, table => 0, text => "a pointer to the registers is necessary. This pointer cna be ", }, { col => 3, table => 0, text => "initialized to point to the index register by a read of GENS1.", }, { col => 0, table => 0, text => "ATTR_PAL_RW_ENB" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Palette Address Source. After loading the colour palette, ", }, { col => 3, table => 0, text => "this bit should be set to logical 1." }, { col => 3, table => 0, text => " 0=Processor to load " }, { col => undef, table => undef, text => " 1=Memory data to access " }, { col => undef, table => undef, text => "Attribute Index Register" }, { col => "heading", table => 1, text => "ATTRDW - W - 8 bits - [GpuF0MMReg,VGA_IO:0x3C0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_DATA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Attribute Data Write" }, { col => undef, table => undef, text => "Attribute Data Write Register" }, { col => "heading", table => 2, text => "ATTRDR - R - 8 bits - [GpuF0MMReg,VGA_IO:0x3C1]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ATTR_DATA" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Attribute Data Read" }, { col => undef, table => undef, text => "Attribute Data Read Register" }, { col => "heading", table => 3, text => "ATTR00 - RW - 8 bits - VGAATTRIND:0x0", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ATTR_PAL" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 3, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 3, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 0" }, { col => "heading", table => 4, text => "ATTR01 - RW - 8 bits - VGAATTRIND:0x1", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "ATTR_PAL" }, { col => 1, table => 4, text => "5:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 4, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 4, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 1" }, ], }, { num => 160, text => [ { col => "heading", table => 0, text => "ATTR02 - RW - 8 bits - VGAATTRIND:0x2", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_PAL" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 0, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 0, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 2" }, { col => "heading", table => 1, text => "ATTR03 - RW - 8 bits - VGAATTRIND:0x3", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_PAL" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 1, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 1, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 3" }, { col => "heading", table => 2, text => "ATTR04 - RW - 8 bits - VGAATTRIND:0x4", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ATTR_PAL" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 2, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 2, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 4" }, { col => "heading", table => 3, text => "ATTR05 - RW - 8 bits - VGAATTRIND:0x5", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ATTR_PAL" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 3, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 3, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 5" }, { col => "heading", table => 4, text => "ATTR06 - RW - 8 bits - VGAATTRIND:0x6", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "ATTR_PAL" }, { col => 1, table => 4, text => "5:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 4, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 4, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 6" }, ], }, { num => 161, text => [ { col => "heading", table => 0, text => "ATTR07 - RW - 8 bits - VGAATTRIND:0x7", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_PAL" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 0, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 0, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 7" }, { col => "heading", table => 1, text => "ATTR08 - RW - 8 bits - VGAATTRIND:0x8", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_PAL" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 1, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 1, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 8" }, { col => "heading", table => 2, text => "ATTR09 - RW - 8 bits - VGAATTRIND:0x9", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ATTR_PAL" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 2, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 2, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register 9" }, { col => "heading", table => 3, text => "ATTR0A - RW - 8 bits - VGAATTRIND:0xA", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ATTR_PAL" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 3, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 3, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Ah (10)" }, { col => "heading", table => 4, text => "ATTR0B - RW - 8 bits - VGAATTRIND:0xB", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "ATTR_PAL" }, { col => 1, table => 4, text => "5:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 4, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 4, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Bh (11)" }, ], }, { num => 162, text => [ { col => "heading", table => 0, text => "ATTR0C - RW - 8 bits - VGAATTRIND:0xC", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_PAL" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 0, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 0, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Ch (12)" }, { col => "heading", table => 1, text => "ATTR0D - RW - 8 bits - VGAATTRIND:0xD", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_PAL" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 1, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 1, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Dh (13)" }, { col => "heading", table => 2, text => "ATTR0E - RW - 8 bits - VGAATTRIND:0xE", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "ATTR_PAL" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 2, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 2, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Eh (14)" }, { col => "heading", table => 3, text => "ATTR0F - RW - 8 bits - VGAATTRIND:0xF", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "ATTR_PAL" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Colour Bits 5:0 map the text attribute or graphics colour ", }, { col => 3, table => 3, text => "input value to a display colour on the screen. Colour is ", }, { col => 3, table => 3, text => "disabled for those bits that are set to logical 0; enabled for ", }, { col => undef, table => undef, text => "those bits set to logical 1." }, { col => undef, table => undef, text => "Palette Register Fh (15)" }, { col => "heading", table => 4, text => "ATTR10 - RW - 8 bits - VGAATTRIND:0x10", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "ATTR_GRPH_MODE" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Graphics/Alphanumeric Mode." }, { col => 3, table => 4, text => " 0=Alphanumeric Mode " }, { col => 3, table => 4, text => " 1=Graphic Mode " }, ], }, { num => 163, text => [ { col => undef, table => undef, text => "ATTR_MONO_EN" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Monochrome/Colour Attributes Select:", }, { col => undef, table => undef, text => " 0=Color Disp " }, { col => undef, table => undef, text => " 1=Monochrome Disp " }, { col => undef, table => undef, text => "ATTR_LGRPH_EN" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Line Graphics Enable. Must be 0 for character fonts that do ", }, { col => undef, table => undef, text => "not use line graphics character codes for graphics. Zero will ", }, { col => undef, table => undef, text => "force the 9th dot to the background colour. One will allow ", }, { col => undef, table => undef, text => "the 8th bit of the line graphics characters to be stretched to ", }, { col => undef, table => undef, text => "the 9th dot." }, { col => undef, table => undef, text => " 0=Disable line graphics 8th dot stretch ", }, { col => undef, table => undef, text => " 1=Enable line graphics 8th dot stretch ", }, { col => undef, table => undef, text => "ATTR_BLINK_EN" }, { col => undef, table => undef, text => 3 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Blink Enable/Background Intensity:", }, { col => undef, table => undef, text => "Selects whether bit 7 of the attribute controls intensity or ", }, { col => undef, table => undef, text => "blinking." }, { col => undef, table => undef, text => " 0=Intensity control " }, { col => undef, table => undef, text => " 1=Blink control " }, { col => undef, table => undef, text => "ATTR_PANTOPONLY" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PEL Panning Compatibility:" }, { col => undef, table => undef, text => " 0=Pan both halves of the screen ", }, { col => undef, table => undef, text => " 1=Pan only the top half screen ", }, { col => undef, table => undef, text => "ATTR_PCLKBY2" }, { col => undef, table => undef, text => 6 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "PEL Clock Select:" }, { col => undef, table => undef, text => " 0=Shift register clocked every dot clock ", }, { col => undef, table => undef, text => " 1=For mode 13 (256 colour), 8 bits packed to form a pixel ", }, { col => undef, table => undef, text => "ATTR_CSEL_EN" }, { col => undef, table => undef, text => 7 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Alternate Colour Source:" }, { col => undef, table => undef, text => " 0=Select ATTR00-0F bit 5:4 as P5 and P4 ", }, { col => undef, table => undef, text => " 1=Select ATTR14 bit 1:0 as P5 and P4 ", }, { col => undef, table => undef, text => "Mode Control Register" }, { col => "heading", table => 0, text => "ATTR11 - RW - 8 bits - VGAATTRIND:0x11", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_OVSC" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Overscan Colour" }, { col => undef, table => undef, text => "Overscan Colour Register" }, { col => "heading", table => 1, text => "ATTR12 - RW - 8 bits - VGAATTRIND:0x12", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_MAP_EN" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable Colour Map bits." }, { col => 3, table => 1, text => "0 = Disables data from respective map from being used for ", }, { col => 3, table => 1, text => "video output." }, { col => 3, table => 1, text => "1 = Enables data from respective map for use in video ", }, { col => 3, table => 1, text => "output." }, { col => 0, table => 1, text => "ATTR_VSMUX" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Video Status Mux bits 1:0. These are control bits for the ", }, { col => 3, table => 1, text => "multiplexer on colour bits P0-P7. The bit selection is also ", }, { col => 3, table => 1, text => "indicated at GENS1[5:4]:" }, { col => 3, table => 1, text => "00 = P2, P0" }, { col => 3, table => 1, text => "01 = P5, P4" }, { col => 3, table => 1, text => "10 = P3, P1" }, { col => undef, table => undef, text => "11 = P7, P6" }, { col => undef, table => undef, text => "Colour Map Enable Register" }, ], }, { num => 164, text => [ { col => undef, table => undef, text => "2.6.7" }, { col => undef, table => undef, text => "VGA Miscellaneous Registers" }, { col => "heading", table => 0, text => "ATTR13 - RW - 8 bits - VGAATTRIND:0x13", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "ATTR_PPAN" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Shift Count Bits 3:0. The shift count value (0-8) indicates ", }, { col => 3, table => 0, text => "how many pixle positions to shift left." }, { col => 3, table => 0, text => "Shift in respective modes" }, { col => 3, table => 0, text => "Count" }, { col => 3, table => 0, text => "0+,1+,2+,13" }, { col => 3, table => 0, text => "All other" }, { col => 3, table => 0, text => "Value" }, { col => 3, table => 0, text => "3+,7,7+" }, { col => 3, table => 0, text => "01" }, { col => 3, table => 0, text => "00" }, { col => 3, table => 0, text => 12 }, { col => 3, table => 0, text => "- 1" }, { col => 3, table => 0, text => 23 }, { col => 3, table => 0, text => 12 }, { col => 3, table => 0, text => 34 }, { col => 3, table => 0, text => "- 3" }, { col => 3, table => 0, text => 45 }, { col => 3, table => 0, text => 24 }, { col => 3, table => 0, text => 56 }, { col => 3, table => 0, text => "- 5" }, { col => 3, table => 0, text => 67 }, { col => 3, table => 0, text => 36 }, { col => 3, table => 0, text => 78 }, { col => 3, table => 0, text => "- 7" }, { col => 3, table => 0, text => 80 }, { col => undef, table => undef, text => "- -" }, { col => undef, table => undef, text => "Horizontal PEL Panning Register" }, { col => "heading", table => 1, text => "ATTR14 - RW - 8 bits - VGAATTRIND:0x14", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "ATTR_CSEL1" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Colour bits P5 and P4, respectively. These are the colour ", }, { col => 3, table => 1, text => "output bits (instead of bits 5 and 4 of the internal palette ", }, { col => 3, table => 1, text => "registers ATTR00-0F) when alternate colour source, bit ", }, { col => 3, table => 1, text => "ATTR10[7] is logical 1." }, { col => 0, table => 1, text => "ATTR_CSEL2" }, { col => 1, table => 1, text => "3:2" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Colour bits P7 and P6, respectively. These two bits are the ", }, { col => 3, table => 1, text => "two high-order bits of the 8-bit colour, used for rapid colour ", }, { col => 3, table => 1, text => "set switching (addressing different parts of the DAC colour ", }, { col => 3, table => 1, text => "lookup table). The lower order bits are in registers ", }, { col => undef, table => undef, text => "ATTR00-0F." }, { col => undef, table => undef, text => "Colour Select Register" }, { col => "heading", table => 2, text => "VGA_RENDER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x300]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_BLINK_RATE" }, { col => 1, table => 2, text => "4:0" }, { col => 2, table => 2, text => "0xf" }, { col => 3, table => 2, text => "One less than the number of frames that the cursor remains ", }, { col => 3, table => 2, text => "OFF = one less than the number of frames that the cursor ", }, { col => 3, table => 2, text => "remains ON = one less than half the cursor blink period = ", }, { col => 3, table => 2, text => "one less than a quarter of the character blink period. ", }, { col => 3, table => 2, text => " If register set to 0 test mode will happen, blink counter is ", }, { col => 3, table => 2, text => "reset and VGA_BLINK_MODE is followed, " }, { col => 3, table => 2, text => " if set to 1, as an exception, cursor blink will be ON one ", }, { col => 3, table => 2, text => "frame, OFF one frame, " }, { col => 3, table => 2, text => " if set to 2, cursor blink will be ON three frames, OFF three ", }, { col => 3, table => 2, text => "frames, etc" }, ], }, { num => 165, text => [ { col => 0, table => 0, text => "VGA_BLINK_MODE" }, { col => 1, table => 0, text => "6:5" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether the blinking sequence starts with ", }, { col => 3, table => 0, text => "blinking characters and cursor visible or invisible. If ", }, { col => 3, table => 0, text => "VGA_BLINK_RATE = 0 the frame remains static at the start ", }, { col => 3, table => 0, text => "of the sequence." }, { col => 3, table => 0, text => " 0=Blinking sequence starts with blinking characters visible ", }, { col => 3, table => 0, text => "and cursor visible " }, { col => 3, table => 0, text => " 1=Blinking sequence starts with blinking characters visible ", }, { col => 3, table => 0, text => "and cursor invisible " }, { col => 3, table => 0, text => " 2=Blinking sequence starts with blinking characters ", }, { col => 3, table => 0, text => "invisible and cursor visible " }, { col => 3, table => 0, text => " 3=Blinking sequence starts with blinking characters ", }, { col => 3, table => 0, text => "invisible and cursor invisible " }, { col => 0, table => 0, text => "VGA_CURSOR_BLINK_INVERT" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines if the blinking characters toggle when the ", }, { col => 3, table => 0, text => "cursor toggles from invisible to visible (default) or when the ", }, { col => 3, table => 0, text => "cursor toggles from visible to invisible", }, { col => 3, table => 0, text => " 0=Sequence is (regardless of where it starts) : blinking ", }, { col => 3, table => 0, text => "chars visible and cursor visible, blinking chars visible and ", }, { col => 3, table => 0, text => "cursor invisible, blinking chars invisible and cursor visible, ", }, { col => 3, table => 0, text => "blinking chars invisible and cursor invisible, blinking chars ", }, { col => 3, table => 0, text => "visible and cursor visible, ... etc . The starting point in the ", }, { col => 3, table => 0, text => "sequence is determined by VGA_BLINK_MODE ", }, { col => 3, table => 0, text => " 1=Sequence is (regardless of where it starts) : blinking ", }, { col => 3, table => 0, text => "chars visible and cursor visible, blinking chars invisible and ", }, { col => 3, table => 0, text => "cursor invisible, blinking chars invisible and cursor visible, ", }, { col => 3, table => 0, text => "blinking chars visible and cursor invisible, blinking chars ", }, { col => 3, table => 0, text => "visible and cursor visible, ... etc. The starting point in the ", }, { col => 3, table => 0, text => "sequence is determined by VGA_BLINK_MODE ", }, { col => 0, table => 0, text => "VGA_EXTD_ADDR_COUNT_ENABLE" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines if the render will allow reading beyond 256K", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable Extended Address Counter beyond 256K ", }, { col => 0, table => 0, text => "VGA_VSTATUS_CNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "controls the main state machine of the VGA render", }, { col => 3, table => 0, text => " 0=VGA render disable (no VGA engine trigger enabled) ", }, { col => 3, table => 0, text => " 1=Use CRTC1 vblank to trigger VGA engine ", }, { col => 3, table => 0, text => " 2=Use CRTC2 vblank to trigger VGA engine ", }, { col => 3, table => 0, text => " 3=Use both CRTC1 and CRTC2 vblank to trigger VGA ", }, { col => 3, table => 0, text => "engine " }, { col => 0, table => 0, text => "VGA_LOCK_8DOT" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines if 9 dot text characters will be allowed or not", }, { col => 3, table => 0, text => " 0=respect SEQ_DOT8 value " }, { col => 3, table => 0, text => " 1=Force SEQ_DOT8 =1, VGA_CKSEL = 0 for ", }, { col => 3, table => 0, text => "functionality " }, { col => 0, table => 0, text => "VGAREG_LINECMP_COMPATIBILITY_S" }, { col => 0, table => 0, text => "EL" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects point at which line compare is activated", }, { col => 3, table => 0, text => " 0=line==line_cmp(default). As per VGA specification ", }, { col => undef, table => undef, text => " 1=line>line_cmp. As per legacy ATI VGA controllers ", }, { col => undef, table => undef, text => "VGA Render control Register" }, { col => "heading", table => 1, text => "VGA_SEQUENCER_RESET_CONTROL - RW - 32 bits - [GpuF0MMReg:0x304]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1_BLANK_DISPLAY_WHEN_SEQUEN" }, { col => 0, table => 1, text => "CER_RESET" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "controls wheter to blank the display 1 in a sequencer reset", }, { col => 3, table => 1, text => " 0=Reseting Sequencer (SEQ00:SEQ_RST) has no effect ", }, { col => 3, table => 1, text => "on Display Controller 1 " }, { col => 3, table => 1, text => " 1=Reseting Sequencer (SEQ00:SEQ_RST) blanks the ", }, { col => 3, table => 1, text => "output of Display Controller 1 " }, { col => 0, table => 1, text => "D2_BLANK_DISPLAY_WHEN_SEQUEN" }, { col => 0, table => 1, text => "CER_RESET" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "controls wheter to blank the display 1 in a sequencer reset", }, { col => 3, table => 1, text => " 0=Reseting Sequencer (SEQ00:SEQ_RST) has no effect ", }, { col => 3, table => 1, text => "on Display Controller 2 " }, { col => 3, table => 1, text => " 1=Reseting Sequencer (SEQ00:SEQ_RST) blanks the ", }, { col => 3, table => 1, text => "output of Display Controller 2 " }, ], }, { num => 166, text => [ { col => 0, table => 0, text => "D1_DISABLE_SYNCS_AND_DE_WHEN" }, { col => 0, table => 0, text => "_SEQUENCER_RESET" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "controls wheter to disable syncs for display 1 in a ", }, { col => 3, table => 0, text => "sequencer reset" }, { col => 3, table => 0, text => " 0=Reseting Sequencer (SEQ00:SEQ_RST) has no effect ", }, { col => 3, table => 0, text => "on Display Controller 1 " }, { col => 3, table => 0, text => " 1=Reseting Sequencer (SEQ00:SEQ_RST) disables ", }, { col => 3, table => 0, text => "HSync, VSync, and DE on Display Controller 2 ", }, { col => 0, table => 0, text => "D2_DISABLE_SYNCS_AND_DE_WHEN" }, { col => 0, table => 0, text => "_SEQUENCER_RESET" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "controls wheter to disable syncs for display 2 in a ", }, { col => 3, table => 0, text => "sequencer reset" }, { col => 3, table => 0, text => " 0=Reseting Sequencer (SEQ00:SEQ_RST) has no effect ", }, { col => 3, table => 0, text => "on Display Controller 2 " }, { col => 3, table => 0, text => " 1=Reseting Sequencer (SEQ00:SEQ_RST) disables ", }, { col => 3, table => 0, text => "HSync, VSync, and DE on Display Controller 2 ", }, { col => 0, table => 0, text => "VGA_MODE_AUTO_TRIGGER_ENABLE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "enables the auto-trigger of the VGA mode in a VGA register ", }, { col => 3, table => 0, text => "write" }, { col => 3, table => 0, text => " 0=disable the auto-trigger mode " }, { col => 3, table => 0, text => " 1=enable the auto-trigger mode " }, { col => 0, table => 0, text => "VGA_MODE_AUTO_TRIGGER_REGIST" }, { col => 0, table => 0, text => "ER_SELECT" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "selects which register write to use for VGA mode ", }, { col => 3, table => 0, text => "auto-trigger" }, { col => 3, table => 0, text => " 0=GENFC_WT is used for auto-trigger " }, { col => 3, table => 0, text => " 1=CRTC_DATA is used for auto-trigger, see ", }, { col => 3, table => 0, text => "VGA_MODE_ENABLE_AUTO_TRIGGER_INDEX_SELEC", }, { col => 3, table => 0, text => "T " }, { col => 0, table => 0, text => "VGA_MODE_AUTO_TRIGGER_INDEX_" }, { col => 0, table => 0, text => "SELECT" }, { col => 1, table => 0, text => "23:18" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Selects which CRTC register write will trigger VGA mode", }, { col => undef, table => undef, text => "VGA sequencer reset control Register", }, { col => "heading", table => 1, text => "VGA_MODE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x308]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_ATI_LINEAR" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Sets linear mode for VESA modes" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "VGA_LUT_PALETTE_UPDATE_MODE" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines how VGA DAC palette updates affect the LUT ", }, { col => 3, table => 1, text => "palette" }, { col => 3, table => 1, text => " 0=VGA DAC palette writes do not update LUT palette ", }, { col => 3, table => 1, text => " 1=VGA DAC palette writes updata LUTA palette ", }, { col => 3, table => 1, text => " 2=VGA DAC palette writes update LUTB palette ", }, { col => 3, table => 1, text => " 3=reserved " }, { col => 0, table => 1, text => "VGA_128K_APERTURE_PAGING" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls wether the B0000 to BFFFF aperture will wrap on ", }, { col => 3, table => 1, text => "top of the A0000 to AFFFF aperture" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "VGA_TEXT_132_COLUMNS_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls 132 column text" }, { col => 3, table => 1, text => " 0=inActive " }, { col => undef, table => undef, text => " 1=Active " }, { col => undef, table => undef, text => "VGA mode control register" }, { col => "heading", table => 2, text => "VGA_SURFACE_PITCH_SELECT - RW - 32 bits - [GpuF0MMReg:0x30C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_SURFACE_PITCH_SELECT" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => "Selects the pitch of the display buffer" }, { col => 3, table => 2, text => " 0=768 pixels " }, { col => 3, table => 2, text => " 1=1024 pixels " }, { col => 3, table => 2, text => " 2=1280 pixels " }, { col => 3, table => 2, text => " 3=1408 pixels " }, ], }, { num => 167, text => [ { col => 0, table => 0, text => "VGA_SURFACE_HEIGHT_SELECT" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects the height of the display buffer", }, { col => 3, table => 0, text => " 0=768 lines " }, { col => 3, table => 0, text => " 1=1024 lines " }, { col => 3, table => 0, text => " 2=1280 lines " }, { col => undef, table => undef, text => " 3=1408 lines " }, { col => undef, table => undef, text => "display buffer pitch Register" }, { col => "heading", table => 1, text => "VGA_MEMORY_BASE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x310]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_MEMORY_BASE_ADDRESS" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Base address of the 32 Meg area that the VGAHDP and ", }, { col => 3, table => 1, text => "VGARENDER access" }, { col => undef, table => undef, text => "NOTE: Bits 0:24 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "VGA Base address Register" }, { col => "heading", table => 2, text => "VGA_DISPBUF1_SURFACE_ADDR - RW - 32 bits - [GpuF0MMReg:0x318]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_DISPBUF1_SURFACE_ADDR" }, { col => 1, table => 2, text => "24:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Base address of display 1 buffer within the 32 Meg defined ", }, { col => 3, table => 2, text => "by VGA_MEMORY_BASE_ADDRESS" }, { col => undef, table => undef, text => "NOTE: Bits 0:19 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "display 1 buffer base address" }, { col => "heading", table => 3, text => "VGA_DISPBUF2_SURFACE_ADDR - RW - 32 bits - [GpuF0MMReg:0x320]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "VGA_DISPBUF2_SURFACE_ADDR" }, { col => 1, table => 3, text => "24:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Base address of display 2 buffer within the 32 Meg defined ", }, { col => 3, table => 3, text => "by VGA_MEMORY_BASE_ADDRESS" }, { col => undef, table => undef, text => "NOTE: Bits 0:19 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "display 2 buffer base address" }, { col => "heading", table => 4, text => "VGA_HDP_CONTROL - RW - 32 bits - [GpuF0MMReg:0x328]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "VGA_MEM_PAGE_SELECT_EN" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Enables write and read paging" }, { col => 3, table => 4, text => " 0=Don't use VGA_MEM_WRITE_PAGE_ADDR and ", }, { col => 3, table => 4, text => "VGA_MEM_READ_PAGE_ADDR registers " }, { col => 3, table => 4, text => " 1=Use VGA_MEM_WRITE_PAGE_ADDR and " }, { col => 3, table => 4, text => "VGA_MEM_READPAGE_ADDR registers " }, { col => 0, table => 4, text => "VGA_MEMORY_DISABLE" }, { col => 1, table => 4, text => 4 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Disables the VGA memory: required by Longhorn", }, { col => 3, table => 4, text => " 0=Do not disable " }, { col => 3, table => 4, text => " 1=ignore writes and return zero for the reads without ", }, { col => 3, table => 4, text => "affecting the read latch " }, ], }, { num => 168, text => [ { col => 0, table => 0, text => "VGA_RBBM_LOCK_DISABLE" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disables the lock that holds register writes while the ", }, { col => 3, table => 0, text => "memory pipe is full" }, { col => 3, table => 0, text => " 0=The RBBM write requests will be held untile the data ", }, { col => 3, table => 0, text => "pipe is idle. " }, { col => 3, table => 0, text => " 1=The RBBM write requests will not be held. ", }, { col => 0, table => 0, text => "VGA_SOFT_RESET" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Does soft reset for VGA, does not reset the registers", }, { col => 3, table => 0, text => " 0=VGA running in normal operating mode ", }, { col => 3, table => 0, text => " 1=Soft Reset to VGA " }, { col => 0, table => 0, text => "VGA_TEST_RESET_CONTROL" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Not used" }, { col => undef, table => undef, text => "VGAHDP control register" }, { col => "heading", table => 1, text => "VGA_CACHE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x32C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_WRITE_THROUGH_CACHE_DIS" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Disables the snooping of memory writes into the read buffer", }, { col => 3, table => 1, text => " 0=Writes that hit the read cache will update it ", }, { col => 3, table => 1, text => " 1=Writes will invalidate the read cache ", }, { col => 0, table => 1, text => "VGA_READ_CACHE_DISABLE" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Disables the read buffer" }, { col => 3, table => 1, text => " 0=reads taken from cache, if possible. ", }, { col => 3, table => 1, text => " 1=reads always sent to memory. " }, { col => 0, table => 1, text => "VGA_READ_BUFFER_INVALIDATE" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Everytime this bit is written with a '1' the VGA read buffer ", }, { col => 3, table => 1, text => "invalidates for coherency purposes" }, { col => 0, table => 1, text => "VGA_DCCIF_W256ONLY" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls whether the write requests from VGADCC to MH ", }, { col => 3, table => 1, text => "will be always 256 bits or optimized for 128 or 256 bit", }, { col => 3, table => 1, text => " 0=Optimized for 128 or 256 bits " }, { col => 3, table => 1, text => " 1=Always 256 bits " }, { col => 0, table => 1, text => "VGA_DCCIF_WC_TIMEOUT" }, { col => 1, table => 1, text => "29:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DCCIF write combiner timeout. If there is write inactivity, ", }, { col => 3, table => 1, text => "this field defines the number of SCLKs to wait before ", }, { col => undef, table => undef, text => "flushing write combiner. Minimun value is 9.", }, { col => undef, table => undef, text => "VGAHDP caching and VGADCCIF write combining control register", }, { col => "heading", table => 2, text => "D1VGA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x330]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1VGA_MODE_ENABLE" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls whether display 1 serves the VGA or not", }, { col => 3, table => 2, text => " 0=VGA display 1 disabled " }, { col => 3, table => 2, text => " 1=VGA display 1 enabled " }, { col => 0, table => 2, text => "D1VGA_TIMING_SELECT" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls whether display 1 uses the VGA or extended ", }, { col => 3, table => 2, text => "timing parameters" }, { col => 3, table => 2, text => " 0=display 1 uses extended timing " }, { col => 3, table => 2, text => " 1=display 1 uses VGA timing " }, { col => 0, table => 2, text => "D1VGA_SYNC_POLARITY_SELECT" }, { col => 1, table => 2, text => 9 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls whether display 1 uses the VGA or extended sync ", }, { col => 3, table => 2, text => "polarities" }, { col => 3, table => 2, text => " 0=display 1 uses extended sync polarity ", }, { col => 3, table => 2, text => " 1=display 1 uses VGA sync polarity " }, { col => 0, table => 2, text => "D1VGA_OVERSCAN_TIMING_SELECT" }, { col => 1, table => 2, text => 10 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Controls whether display 1 uses the VGA or extended ", }, { col => 3, table => 2, text => "overscan timing. Only followed if " }, { col => 3, table => 2, text => "D1VGA_TIMING_SELECT=1" }, { col => 3, table => 2, text => " 0=display 1 uses extended overscan timing ", }, { col => 3, table => 2, text => " 1=display 1 uses VGA overscan timing ", }, { col => 0, table => 2, text => "D1VGA_OVERSCAN_COLOR_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls whether display 1 uses the VGA or extended ", }, { col => 3, table => 2, text => "overscan color" }, { col => 3, table => 2, text => " 0=display 1 uses CRTC register for overscan color ", }, { col => 3, table => 2, text => " 1=display 1 uses VGA register for overscan color ", }, ], }, { num => 169, text => [ { col => 0, table => 0, text => "D1VGA_ROTATE" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls rotation, only looked at if " }, { col => 3, table => 0, text => "D1VGA_TIMING_SELECT =0" }, { col => 3, table => 0, text => " 0=no rotation, displays do not interchange ", }, { col => 3, table => 0, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 0, text => "parameters " }, { col => 3, table => 0, text => " 1=rotation 90 degrees, displays do interchange ", }, { col => 3, table => 0, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 0, text => "parameters " }, { col => 3, table => 0, text => " 2=rotation 180 degrees, displays do not interchange ", }, { col => 3, table => 0, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 0, text => "parameters " }, { col => 3, table => 0, text => " 3=rotation 270 degrees, displays do interchange ", }, { col => 3, table => 0, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => undef, table => undef, text => "parameters " }, { col => undef, table => undef, text => "VGA-Display1 interface control register", }, { col => "heading", table => 1, text => "D2VGA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x338]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2VGA_MODE_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls whether display 2 serves the VGA or not", }, { col => 3, table => 1, text => " 0=VGA display 2 disabled " }, { col => 3, table => 1, text => " 1=VGA display 2 enabled " }, { col => 0, table => 1, text => "D2VGA_TIMING_SELECT" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls whether display 2 uses the VGA or extended ", }, { col => 3, table => 1, text => "timing parameters" }, { col => 3, table => 1, text => " 0=display 2 uses extended timing " }, { col => 3, table => 1, text => " 1=display 2 uses VGA timing " }, { col => 0, table => 1, text => "D2VGA_SYNC_POLARITY_SELECT" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls whether display 2 uses the VGA or extended sync ", }, { col => 3, table => 1, text => "polarities" }, { col => 3, table => 1, text => " 0=display 2 uses extended sync polarity ", }, { col => 3, table => 1, text => " 1=display 2 uses VGA sync polarity " }, { col => 0, table => 1, text => "D2VGA_OVERSCAN_TIMING_SELECT" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Controls whether display 2 uses the VGA or extended ", }, { col => 3, table => 1, text => "overscan timing. Only followed if " }, { col => 3, table => 1, text => "D2VGA_TIMING_SELECT=1" }, { col => 3, table => 1, text => " 0=display 2 uses extended overscan timing ", }, { col => 3, table => 1, text => " 1=display 2 uses VGA overscan timing ", }, { col => 0, table => 1, text => "D2VGA_OVERSCAN_COLOR_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls whether display 2 uses the VGA or extended ", }, { col => 3, table => 1, text => "overscan color" }, { col => 3, table => 1, text => " 0=display 2 uses CRTC register for overscan color ", }, { col => 3, table => 1, text => " 1=display 2 uses VGA register for overscan color ", }, { col => 0, table => 1, text => "D2VGA_ROTATE" }, { col => 1, table => 1, text => "25:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls rotation, only looked at if " }, { col => 3, table => 1, text => "D2VGA_TIMING_SELECT=0" }, { col => 3, table => 1, text => " 0=no rotation, displays do not interchange ", }, { col => 3, table => 1, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 1, text => "parameters " }, { col => 3, table => 1, text => " 1=rotation 90 degrees, displays do interchange ", }, { col => 3, table => 1, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 1, text => "parameters " }, { col => 3, table => 1, text => " 2=rotation 180 degrees, displays do not interchange ", }, { col => 3, table => 1, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => 3, table => 1, text => "parameters " }, { col => 3, table => 1, text => " 3=rotation 270 degrees, displays do interchange ", }, { col => 3, table => 1, text => "VGA_DISP_h_disp_width and VGA_DISP_v_disp_height ", }, { col => undef, table => undef, text => "parameters " }, { col => undef, table => undef, text => "VGA-Display2 interface control register", }, ], }, { num => 170, text => [ { col => "heading", table => 0, text => "VGA_HW_DEBUG - RW - 32 bits - [GpuF0MMReg:0x33C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VGA_HW_DEBUG" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => "heading", table => 1, text => "VGA_STATUS - RW - 32 bits - [GpuF0MMReg:0x340]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_MEM_ACCESS_STATUS (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Memory access status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 1, text => "VGA_REG_ACCESS_STATUS (R)" }, { col => 1, table => 1, text => "10x0" }, { col => 3, table => 1, text => "Register access status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 1, text => "VGA_DISPLAY_SWITCH_STATUS (R)" }, { col => 1, table => 1, text => "20x0" }, { col => 3, table => 1, text => "Display switch status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred, interrupting if enabled ", }, { col => 0, table => 1, text => "VGA_MODE_AUTO_TRIGGER_STATUS " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA mode auto trigger status" }, { col => 3, table => 1, text => " 0=No event " }, { col => undef, table => undef, text => " 1=Event has occurred, interrupting if enabled ", }, { col => undef, table => undef, text => "VGA status register" }, { col => "heading", table => 2, text => "VGA_INTERRUPT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x344]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_MEM_ACCESS_INT_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the interrupt for the Memory access status", }, { col => 3, table => 2, text => " 0=Disable the interrupt which is set when VGA memory is ", }, { col => 3, table => 2, text => "written or read " }, { col => 3, table => 2, text => " 1=Enable the interrupt which is set when VGA memory is ", }, { col => 3, table => 2, text => "written or read " }, { col => 0, table => 2, text => "VGA_REG_ACCESS_INT_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the interrupt for the register access status", }, { col => 3, table => 2, text => " 0=Disable the interrupt which is set when the standard ", }, { col => 3, table => 2, text => "VGA registers are written or read " }, { col => 3, table => 2, text => " 1=Enable the interrupt which is set when the standard ", }, { col => 3, table => 2, text => "VGA registers are written or read " }, { col => 0, table => 2, text => "VGA_DISPLAY_SWITCH_INT_MASK" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the interrupt for the Display switch status", }, { col => 3, table => 2, text => " 0=Disable the interrupt which is set when the VGA render ", }, { col => 3, table => 2, text => "switches display buffers " }, { col => 3, table => 2, text => " 1=Enable the interrupt which is set when the VGA render ", }, { col => 3, table => 2, text => "switches display buffers " }, { col => 0, table => 2, text => "VGA_MODE_AUTO_TRIGGER_INT_MA" }, { col => 0, table => 2, text => "SK" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the interrupt for VGA mode auto trigger", }, { col => 3, table => 2, text => " 0=Disable the interrupt which is set when VGA mode is ", }, { col => 3, table => 2, text => "auto-triggered " }, { col => 3, table => 2, text => " 1=Enable the interrupt which is set when VGA mode is ", }, { col => undef, table => undef, text => "auto-triggered " }, { col => undef, table => undef, text => "VGA interrupt mask register" }, { col => "heading", table => 3, text => "VGA_STATUS_CLEAR - RW - 32 bits - [GpuF0MMReg:0x348]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 171, text => [ { col => 0, table => 0, text => "VGA_MEM_ACCESS_INT_CLEAR (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0Clears the Memory access interrupt" }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "VGA_REG_ACCESS_INT_CLEAR (W)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the register access interrupt" }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "VGA_DISPLAY_SWITCH_INT_CLEAR " }, { col => 0, table => 0, text => "(W)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the display switch interrupt" }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear status " }, { col => 0, table => 0, text => "VGA_MODE_AUTO_TRIGGER_INT_CLE" }, { col => 0, table => 0, text => "AR (W)" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the VGA mode auto trigger interrupt", }, { col => 3, table => 0, text => " 0=No effect " }, { col => undef, table => undef, text => " 1=Clear status " }, { col => undef, table => undef, text => "VGA interrupt clear register" }, { col => "heading", table => 1, text => "VGA_INTERRUPT_STATUS - RW - 32 bits - [GpuF0MMReg:0x34C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_MEM_ACCESS_INT_STATUS (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Memory access interrupt status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred " }, { col => 0, table => 1, text => "VGA_REG_ACCESS_INT_STATUS (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Register access interrupt status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred " }, { col => 0, table => 1, text => "VGA_DISPLAY_SWITCH_INT_STATUS " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Display switch interrupt status" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Event has occurred " }, { col => 0, table => 1, text => "VGA_MODE_AUTO_TRIGGER_INT_STA" }, { col => 0, table => 1, text => "TUS (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VGA mode auto trigger interrupt status" }, { col => 3, table => 1, text => " 0=No event " }, { col => undef, table => undef, text => " 1=Event has occurred " }, { col => undef, table => undef, text => "VGA Interrupt status register" }, { col => "heading", table => 2, text => "VGA_MAIN_CONTROL - RW - 32 bits - [GpuF0MMReg:0x350]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_CRTC_TIMEOUT" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls whether and in what conditions the vga crtc ", }, { col => 3, table => 2, text => "calculations will be forced to start if the VBLANK from ", }, { col => 3, table => 2, text => "display takes too long to come" }, { col => 3, table => 2, text => " 0=VGACRTC times out and is restarted after 1/50 sec ", }, { col => 3, table => 2, text => "without VBLANK " }, { col => 3, table => 2, text => " 1=VGACRTC times out and is restarted after 1/10 sec ", }, { col => 3, table => 2, text => "without VBLANK " }, { col => 3, table => 2, text => " 2=reserved " }, { col => 3, table => 2, text => " 3=VGACRTC does not timeout " }, { col => 0, table => 2, text => "VGA_RENDER_TIMEOUT_COUNT" }, { col => 1, table => 2, text => "4:3" }, { col => 2, table => 2, text => "0x3" }, { col => 3, table => 2, text => "Controls whether and in how many display frames the vga ", }, { col => 3, table => 2, text => "render will be forced to finish or timeout", }, { col => 3, table => 2, text => " 0=No timeout " }, { col => 3, table => 2, text => " 1=2 frame " }, { col => 3, table => 2, text => " 2=3 frames " }, { col => 3, table => 2, text => " 3=4 frames " }, ], }, { num => 173, text => [ { col => 0, table => 0, text => "VGA_MAIN_TEST_VSTATUS_NO_DISP" }, { col => 0, table => 0, text => "LAY_CRTC_TIMEOUT" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For testing purposes, makes the virtual vertical retrace, the ", }, { col => 3, table => 0, text => "crtc timeout and the virtual no display horizontal pulses ", }, { col => 3, table => 0, text => "faster by using the engine clock frequency instead of 1MHz ", }, { col => 3, table => 0, text => "reference" }, { col => 3, table => 0, text => " 0=VGACRTC timeout is as indicated by ", }, { col => 3, table => 0, text => "VGA_CRTC_TIMEOUT, virtual vertical retrace duration is ", }, { col => 3, table => 0, text => "as indicated by " }, { col => 3, table => 0, text => "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION, " }, { col => 3, table => 0, text => "virtual no display horizontal pulses are 31.25 KHz if ", }, { col => 3, table => 0, text => "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT is ", }, { col => 3, table => 0, text => "zero " }, { col => 3, table => 0, text => " 1=VGACRTC timeout is one 400th of what is indicated by ", }, { col => 3, table => 0, text => "VGA_CRTC_TIMEOUT, virtual vertical retrace duration one ", }, { col => 3, table => 0, text => "400th of what is indicated by " }, { col => 3, table => 0, text => "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION, " }, { col => 3, table => 0, text => "virtual no display horizontal pulses are 400*31.25 KHz if ", }, { col => 3, table => 0, text => "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT is ", }, { col => undef, table => undef, text => "zero " }, { col => undef, table => undef, text => "VGA Main control" }, { col => "heading", table => 1, text => "VGA_TEST_CONTROL - RW - 32 bits - [GpuF0MMReg:0x354]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_TEST_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls wether the vga render looks at vertical blank ", }, { col => 3, table => 1, text => "signals from the displays to start rendering or will start ", }, { col => 3, table => 1, text => "through a register write" }, { col => 3, table => 1, text => " 0=Render responds to status signals from DISP1, DISP2 ", }, { col => 3, table => 1, text => " 1=Render responds to VGA_TEST_RENDER_START ", }, { col => 0, table => 1, text => "VGA_TEST_RENDER_START" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Starts the vga render" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Every time this is written with a high, if ", }, { col => 3, table => 1, text => "VGA_TEST_ENABLE is set, VGA Rendering starts ", }, { col => 0, table => 1, text => "VGA_TEST_RENDER_DONE (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Signals when the vga render is done rendering", }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=If VGA_TEST_ENABLE is set, VGA Rendering is done ", }, { col => 0, table => 1, text => "VGA_TEST_RENDER_DISPBUF_SELEC" }, { col => 0, table => 1, text => "T" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selects to which display buffer the render will render in test ", }, { col => 3, table => 1, text => "mode (VGA_TEST_ENABLE=1)" }, { col => 3, table => 1, text => " 0=VGA Render will write into DISPBUF1 starting at ", }, { col => 3, table => 1, text => "VGA_DISPBUF1_SURFACE_ADDR " }, { col => 3, table => 1, text => " 1=VGA Render will write into DISPBUF2 starting at ", }, { col => undef, table => undef, text => "VGA_DISPBUF2_SURFACE_ADDR " }, { col => undef, table => undef, text => "VGA test control register" }, { col => "heading", table => 2, text => "VGA_DEBUG_READBACK_INDEX - RW - 32 bits - [GpuF0MMReg:0x358]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_DEBUG_READBACK_INDEX" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Index for the VGA debug readback", }, { col => undef, table => undef, text => " VGA debug readback index register", }, ], }, { num => 174, text => [ { col => "heading", table => 0, text => "VGA_DEBUG_READBACK_DATA - RW - 32 bits - [GpuF0MMReg:0x35C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "VGA_DEBUG_READBACK_DATA (R)" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "According to the value of " }, { col => 3, table => 0, text => "VGA_DEBUG_READBACK_INDEX, " }, { col => 3, table => 0, text => "VGA_DEBUG_READBACK_DATA will have this values:", }, { col => 3, table => 0, text => "0: VGAREG_DISP_h_total[10:0]" }, { col => 3, table => 0, text => "1: VGAREG_DISP_h_sync_end[10:0]" }, { col => 3, table => 0, text => "2: VGAREG_DISP_h_disp_start[10:0]" }, { col => 3, table => 0, text => "3: VGAREG_DISP_h_disp_width[10:0]" }, { col => 3, table => 0, text => "4: VGAREG_DISP_h_blank_start[10:0]" }, { col => 3, table => 0, text => "5: VGAREG_DISP_h_blank_end[10:0] " }, { col => 3, table => 0, text => "6: VGAREG_DISP_v_total[10:0]" }, { col => 3, table => 0, text => " 7: VGAREG_DISP_v_sync_end[10:0]" }, { col => 3, table => 0, text => "8: VGAREG_DISP_v_disp_start[10:0]" }, { col => 3, table => 0, text => " 9: VGAREG_DISP_v_disp_height[10:0]" }, { col => 3, table => 0, text => "10: VGAREG_DISP_v_blank_start[10:0]" }, { col => 3, table => 0, text => "11: VGAREG_DISP_v_blank_end[10:0]" }, { col => 3, table => 0, text => " 12: VGAREG_DISP_overscan_colorR[5:0]" }, { col => 3, table => 0, text => " 13: VGAREG_DISP_overscan_colorG[5:0]" }, { col => 3, table => 0, text => "14: VGAREG_DISP_overscan_colorB[5:0]" }, { col => 3, table => 0, text => "15: reserved " }, { col => 3, table => 0, text => "16 VGA_DISP_viewport_x_start " }, { col => undef, table => undef, text => "17 VGA_DISP_viewport_y_start" }, { col => undef, table => undef, text => " VGA debug readback data register", }, { col => "heading", table => 1, text => "VGA_MEM_WRITE_PAGE_ADDR - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x48]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "VGA_MEM_WRITE_PAGE0_ADDR" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Write page 0 address" }, { col => 0, table => 1, text => "VGA_MEM_WRITE_PAGE1_ADDR" }, { col => 1, table => 1, text => "25:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Write page 1 address" }, { col => undef, table => undef, text => "VGA write page register" }, { col => "heading", table => 2, text => "VGA_MEM_READ_PAGE_ADDR - RW - 32 bits - [GpuF0MMReg,GpuIOReg:0x4C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "VGA_MEM_READ_PAGE0_ADDR" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Read page 0 address" }, { col => 0, table => 2, text => "VGA_MEM_READ_PAGE1_ADDR" }, { col => 1, table => 2, text => "25:16" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Read page 1 address" }, { col => undef, table => undef, text => "VGA read page register" }, ], }, { num => 175, text => [ { col => undef, table => undef, text => "2.7" }, { col => undef, table => undef, text => "Display Controller Registers" }, { col => undef, table => undef, text => "2.7.1" }, { col => undef, table => undef, text => "Primary Display Graphics Control Registers", }, { col => "heading", table => 0, text => "D1GRPH_ENABLE - RW - 32 bits - [GpuF0MMReg:0x6100]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1GRPH_ENABLE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Primary graphic enabled." }, { col => 3, table => 0, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Primary graphic enabled." }, { col => "heading", table => 1, text => "D1GRPH_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6104]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_DEPTH" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphic pixel depth." }, { col => 3, table => 1, text => " 0=8bpp " }, { col => 3, table => 1, text => " 1=16bpp " }, { col => 3, table => 1, text => " 2=32bpp " }, { col => 3, table => 1, text => " 3=64bpp " }, { col => 0, table => 1, text => "D1GRPH_Z" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Z[1:0] value for tiling" }, { col => 0, table => 1, text => "D1GRPH_FORMAT" }, { col => 1, table => 1, text => "10:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphic pixel format. It is used together with ", }, { col => 3, table => 1, text => "D1GRPH_DEPTH to define the graphic pixel format.", }, { col => 3, table => 1, text => "If (D1GRPH_DEPTH = 0x0)(8 bpp)" }, { col => 3, table => 1, text => " 0x0 - indexed" }, { col => 3, table => 1, text => " others - reserved" }, { col => 3, table => 1, text => "else if (D1GRPH_DEPTH = 0x1)(16 bpp)" }, { col => 3, table => 1, text => " 0x0 - ARGB 1555" }, { col => 3, table => 1, text => " 0x1 - RGB 565" }, { col => 3, table => 1, text => " 0x2 - ARGB 4444" }, { col => 3, table => 1, text => " 0x3 - Alpha index 88" }, { col => 3, table => 1, text => " 0x4 - monochrome 16" }, { col => 3, table => 1, text => " 0x5 - BGRA 5551" }, { col => 3, table => 1, text => " others - reserved" }, { col => 3, table => 1, text => "else if (D1GRPH_DEPTH = 0x2)(32 bpp)" }, { col => 3, table => 1, text => " 0x0 - ARGB 8888" }, { col => 3, table => 1, text => " 0x1 - ARGB 2101010" }, { col => 3, table => 1, text => " 0x2 - 32bpp digital output" }, { col => 3, table => 1, text => " 0x3 - 8-bit ARGB 2101010" }, { col => 3, table => 1, text => " 0x4 - BGRA 1010102" }, { col => 3, table => 1, text => " 0x5 - 8-bit BGRA 1010102" }, { col => 3, table => 1, text => " 0x6 - RGB 111110" }, { col => 3, table => 1, text => " 0x7 - BGR 101111" }, { col => 3, table => 1, text => " others - reserved" }, { col => 3, table => 1, text => "else if (D1GRPH_DEPTH = 0x3)(64 bpp)" }, { col => 3, table => 1, text => " 0x0 - ARGB 16161616" }, { col => 3, table => 1, text => " 0x1 - 64bpp digital output ARGB[13:2]" }, { col => 3, table => 1, text => " 0x2 - 64bpp digital output RGB[15:0]" }, { col => 3, table => 1, text => " 0x3 - 64bpp digital output ARGB[11:0]" }, { col => 3, table => 1, text => " 0x4 - 64bpp digital output BGR[15:0]" }, { col => 3, table => 1, text => " others - reserved" }, { col => 0, table => 1, text => "D1GRPH_TILE_COMPACT_EN" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enables multichip tile compaction" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, ], }, { num => 177, text => [ { col => 0, table => 0, text => "D1GRPH_LUT_10BIT_BYPASS_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable bypass primary graphic LUT for 2101010 format", }, { col => 3, table => 0, text => " 0=Use LUT " }, { col => 3, table => 0, text => " 1=Bypass LUT when in 2101010 format. Ignored for other ", }, { col => 3, table => 0, text => "formats " }, { col => 0, table => 0, text => "D1GRPH_LUT_10BIT_BYPASS_DBL_B" }, { col => 0, table => 0, text => "UF_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable double buffer D1GRPH_LUT_10BIT_BYPASS_EN", }, { col => 3, table => 0, text => " 0=D1GRPH_LUT_10BIT_BYPASS_EN take effect right ", }, { col => 3, table => 0, text => "away " }, { col => 3, table => 0, text => " 1=D1GRPH_LUT_10BIT_BYPASS_EN are double ", }, { col => undef, table => undef, text => "buffered " }, { col => undef, table => undef, text => "Primary graphic LUT selection." }, { col => "heading", table => 1, text => "D1GRPH_SWAP_CNTL - RW - 32 bits - [GpuF0MMReg:0x610C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_ENDIAN_SWAP" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "MC endian swap select" }, { col => 3, table => 1, text => " 0=0=none " }, { col => 3, table => 1, text => " 1=1=8in16(0xaabb=>0xbbaa) " }, { col => 3, table => 1, text => " 2=2=8in32(0xaabbccdd=>0xddccbbaa) " }, { col => 3, table => 1, text => " 3=3=8in64(0xaabbccddeeff0011=>0x1100ffeeddccbbaa) ", }, { col => 0, table => 1, text => "D1GRPH_RED_CROSSBAR" }, { col => 1, table => 1, text => "5:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Red crossbar select" }, { col => 3, table => 1, text => " 0=0=select from R " }, { col => 3, table => 1, text => " 1=1=select from G " }, { col => 3, table => 1, text => " 2=2=select from B " }, { col => 3, table => 1, text => " 3=3=select from A " }, { col => 0, table => 1, text => "D1GRPH_GREEN_CROSSBAR" }, { col => 1, table => 1, text => "7:6" }, { col => 2, table => 1, text => "0x0Green crossbar select" }, { col => 3, table => 1, text => " 0=0=select from G " }, { col => 3, table => 1, text => " 1=1=select from B " }, { col => 3, table => 1, text => " 2=2=select from A " }, { col => 3, table => 1, text => " 3=3=select from R " }, { col => 0, table => 1, text => "D1GRPH_BLUE_CROSSBAR" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Blue crossbar select" }, { col => 3, table => 1, text => " 0=0=select from B " }, { col => 3, table => 1, text => " 1=1=select from A " }, { col => 3, table => 1, text => " 2=2=select from R " }, { col => 3, table => 1, text => " 3=3=select from G " }, { col => 0, table => 1, text => "D1GRPH_ALPHA_CROSSBAR" }, { col => 1, table => 1, text => "11:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Alpha crossbar select" }, { col => 3, table => 1, text => " 0=0=select from A " }, { col => 3, table => 1, text => " 1=1=select from R " }, { col => 3, table => 1, text => " 2=2=select from G " }, { col => undef, table => undef, text => " 3=3=select from B " }, { col => undef, table => undef, text => "Endian swap and component reorder control", }, { col => "heading", table => 2, text => "D1GRPH_PRIMARY_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6110]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_PRIMARY_DFQ_ENABLE" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary surface address DFQ enable" }, { col => 3, table => 2, text => " 0=0 = one deep queue mode " }, { col => 3, table => 2, text => " 1=1 = DFQ mode " }, { col => 0, table => 2, text => "D1GRPH_PRIMARY_SURFACE_ADDRE" }, { col => 0, table => 2, text => "SS" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary surface address for primary graphics in byte. It is ", }, { col => undef, table => undef, text => "256 byte aligned." }, { col => undef, table => undef, text => "Primary surface address for primary graphics in byte.", }, ], }, { num => 178, text => [ { col => "heading", table => 0, text => "D1GRPH_SECONDARY_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6118]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1GRPH_SECONDARY_DFQ_ENABLE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary surface address DFQ enable" }, { col => 3, table => 0, text => " 0=0 = one deep queue mode " }, { col => 3, table => 0, text => " 1=1 = DFQ mode " }, { col => 0, table => 0, text => "D1GRPH_SECONDARY_SURFACE_AD" }, { col => 0, table => 0, text => "DRESS" }, { col => 1, table => 0, text => "31:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary surface address for primary graphics in byte. It ", }, { col => undef, table => undef, text => "is 256 byte aligned." }, { col => undef, table => undef, text => "Secondary surface address for primary graphics in byte.", }, { col => "heading", table => 1, text => "D1GRPH_PITCH - RW - 32 bits - [GpuF0MMReg:0x6120]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_PITCH" }, { col => 1, table => 1, text => "13:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphic surface pitch in pixels. For ", }, { col => 3, table => 1, text => "Micro-tiled/Macro-tiled surface, it must be multiple of 64 ", }, { col => 3, table => 1, text => "pixeld in 8bpp mode. For Micro-linear/Macro-tiled surface, it ", }, { col => 3, table => 1, text => "must be multiple of 256 pixeld in 8bpp mode, multiple of 128 ", }, { col => 3, table => 1, text => "pixels in 16bpp mode and multiple of 64 pixels in 32bpp ", }, { col => 3, table => 1, text => "mode. For Micro-linear/Macro-linear surface, it must be ", }, { col => 3, table => 1, text => "multiple of 64 pixels in 8bpp mode. For other modes, it must ", }, { col => 3, table => 1, text => "be multiple of 32." }, { col => undef, table => undef, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary graphic surface pitch in pixels.", }, { col => "heading", table => 2, text => "D1GRPH_SURFACE_OFFSET_X - RW - 32 bits - [GpuF0MMReg:0x6124]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_SURFACE_OFFSET_X" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary graphic X surface offset. It is 256 pixels aligned.", }, { col => undef, table => undef, text => "NOTE: Bits 0:7 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary graphic X surface offset.", }, { col => "heading", table => 3, text => "D1GRPH_SURFACE_OFFSET_Y - RW - 32 bits - [GpuF0MMReg:0x6128]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1GRPH_SURFACE_OFFSET_Y" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary graphic Y surface offset. It must be even value", }, { col => undef, table => undef, text => "NOTE: Bit 0 of this field is hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary graphic Y surface offset.", }, { col => undef, table => undef, text => "D1GRPH_X_START - RW - 32 bits - [GpuF0MMReg:0x612C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 179, text => [ { col => 0, table => 0, text => "D1GRPH_X_START" }, { col => 1, table => 0, text => "12:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphic X start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Primary graphic X start coordinate relative to the desktop coordinates.", }, { col => "heading", table => 1, text => "D1GRPH_Y_START - RW - 32 bits - [GpuF0MMReg:0x6130]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_Y_START" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphic Y start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Primary graphic Y start coordinate relative to the desktop coordinates.", }, { col => "heading", table => 2, text => "D1GRPH_X_END - RW - 32 bits - [GpuF0MMReg:0x6134]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_X_END" }, { col => 1, table => 2, text => "13:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary graphic X end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => undef, table => undef, text => "Primary graphic X end coordinate relative to the desktop coordinates.", }, { col => "heading", table => 3, text => "D1GRPH_Y_END - RW - 32 bits - [GpuF0MMReg:0x6138]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1GRPH_Y_END" }, { col => 1, table => 3, text => "13:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary graphic Y end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => undef, table => undef, text => "Primary graphic Y end coordinate relative to the desktop coordinates.", }, { col => undef, table => undef, text => "D1GRPH_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6144]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 180, text => [ { col => 0, table => 0, text => "D1GRPH_MODE_UPDATE_PENDING " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphic mode register update pending control. It is ", }, { col => 3, table => 0, text => "set to 1 after a host write to graphics mode register. It is ", }, { col => 3, table => 0, text => "cleared after double buffering is done." }, { col => 3, table => 0, text => "This signal is only visible through register.", }, { col => 3, table => 0, text => "The graphics surface register includes:" }, { col => 3, table => 0, text => "D1GRPH_DEPTH" }, { col => 3, table => 0, text => "D1GRPH_FORMAT" }, { col => 3, table => 0, text => "D1GRPH_SWAP_RB" }, { col => 3, table => 0, text => "D1GRPH_LUT_SEL" }, { col => 3, table => 0, text => "D1GRPH_LUT_10BIT_BYPASS_EN" }, { col => 3, table => 0, text => "D1GRPH_ENABLE" }, { col => 3, table => 0, text => "D1GRPH_X_START" }, { col => 3, table => 0, text => "D1GRPH_Y_START" }, { col => 3, table => 0, text => "D1GRPH_X_END" }, { col => 3, table => 0, text => "D1GRPH_Y_END" }, { col => 3, table => 0, text => "The mode register double buffering can only occur at ", }, { col => 3, table => 0, text => "vertical retrace. The double buffering occurs when ", }, { col => 3, table => 0, text => "D1GRPH_MODE_UPDATE_PENDING = 1 and " }, { col => 3, table => 0, text => "D1GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1.", }, { col => 3, table => 0, text => "If CRTC1 is disabled, the registers will be updated instantly.", }, { col => 3, table => 0, text => " 0=No update pending " }, { col => 3, table => 0, text => " 1=Update pending " }, { col => 0, table => 0, text => "D1GRPH_MODE_UPDATE_TAKEN (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphics update taken status for mode registers. It ", }, { col => 3, table => 0, text => "is set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 0, text => "V_UPDATE = 0." }, { col => 0, table => 0, text => "D1GRPH_SURFACE_UPDATE_PENDIN" }, { col => 0, table => 0, text => "G (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphic surface register update pending control. If it ", }, { col => 3, table => 0, text => "is set to 1 after a host write to graphics surface register. It is ", }, { col => 3, table => 0, text => "cleared after double buffering is done. It is cleared after ", }, { col => 3, table => 0, text => "double buffering is done." }, { col => 3, table => 0, text => "This signal also goes to both the RBBM wait_until and to ", }, { col => 3, table => 0, text => "the CP_RTS_discrete inputs." }, { col => 3, table => 0, text => "The graphics surface register includes: ", }, { col => 3, table => 0, text => "D1GRPH_PRIMARY_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D1GRPH_SECONDARY_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D1GRPH_PITCH" }, { col => 3, table => 0, text => "D1GRPH_SURFACE_OFFSET_X" }, { col => 3, table => 0, text => "D1GRPH_SURFACE_OFFSET_Y." }, { col => 3, table => 0, text => "If D1GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, ", }, { col => 3, table => 0, text => "the double buffering occurs in vertical retrace when ", }, { col => 3, table => 0, text => "D1GRPH_SURFACE_UPDATE_PENDING = 1 and " }, { col => 3, table => 0, text => "D1GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1. ", }, { col => 3, table => 0, text => "Otherwise the double buffering happens at horizontal ", }, { col => 3, table => 0, text => "retrace when D1GRPH_SURFACE_UPDATE_PENDING = ", }, { col => 3, table => 0, text => "1 and D1GRPH_UPDATE_LOCK = 0 and Data request for ", }, { col => 3, table => 0, text => "last chunk of the line is sent from DCP to DMIF.", }, { col => 3, table => 0, text => "If CRTC1 is disabled, the registers will be updated instantly", }, { col => 0, table => 0, text => "D1GRPH_SURFACE_UPDATE_TAKEN " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphics update taken status for surface registers. ", }, { col => 3, table => 0, text => "If D1GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, it ", }, { col => 3, table => 0, text => "is set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 0, text => "V_UPDATE = 0. Otherwise, it is active for one clock cycle ", }, { col => 3, table => 0, text => "when double buffering occurs at the horizontal retrace.", }, { col => 0, table => 0, text => "D1GRPH_UPDATE_LOCK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphic register update lock control. This lock bit ", }, { col => 3, table => 0, text => "control both surface and mode register double buffer", }, { col => 3, table => 0, text => " 0=Unlocked " }, { col => 3, table => 0, text => " 1=Locked " }, ], }, { num => 181, text => [ { col => undef, table => undef, text => "2.7.2" }, { col => undef, table => undef, text => "Primary Display Video Overlay Control Registers", }, { col => 0, table => 0, text => "D1GRPH_MODE_DISABLE_MULTIPLE_" }, { col => 0, table => 0, text => "UPDATE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D1GRPH mode registers can be updated multiple times ", }, { col => 3, table => 0, text => "in one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D1GRPH mode registers can only be updated once in ", }, { col => 3, table => 0, text => "one V_UPDATE period " }, { col => 0, table => 0, text => "D1GRPH_SURFACE_DISABLE_MULTIP" }, { col => 0, table => 0, text => "LE_UPDATE" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D1GRPH surface registers can be updated multiple ", }, { col => 3, table => 0, text => "times in one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D1GRPH surface registers can only be updated once in ", }, { col => undef, table => undef, text => "one V_UPDATE period " }, { col => undef, table => undef, text => "Primary graphic update control" }, { col => "heading", table => 1, text => "D1GRPH_FLIP_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6148]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_SURFACE_UPDATE_H_RETR" }, { col => 0, table => 1, text => "ACE_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable primary graphic surface register double buffer in ", }, { col => 3, table => 1, text => "horizontal retrace." }, { col => 3, table => 1, text => " 0=Vertical retrace flipping " }, { col => undef, table => undef, text => " 1=Horizontal retrace flipping ", }, { col => undef, table => undef, text => "Enable primary graphic surface register double buffer in horizontal retrace", }, { col => "heading", table => 2, text => "D1GRPH_SURFACE_ADDRESS_INUSE - RW - 32 bits - [GpuF0MMReg:0x614C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_SURFACE_ADDRESS_INUSE " }, { col => 0, table => 2, text => "(R)" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "This register reads back snapshot of primary graphics ", }, { col => 3, table => 2, text => "surface address used for data request. The address is the ", }, { col => 3, table => 2, text => "signal sent to DMIF and is updated on SOF or horizontal ", }, { col => 3, table => 2, text => "surface update. The snapshot is triggered by writing 1 into ", }, { col => 3, table => 2, text => "field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC ", }, { col => undef, table => undef, text => "register D1CRTC_SNAPSHOT_STATUS.", }, { col => undef, table => undef, text => "Snapshot of primary graphics surface address in use", }, { col => "heading", table => 3, text => "D1OVL_ENABLE - RW - 32 bits - [GpuF0MMReg:0x6180]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_ENABLE" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay enabled." }, { col => 3, table => 3, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Primary overlay enabled." }, { col => "heading", table => 4, text => "D1OVL_CONTROL1 - RW - 32 bits - [GpuF0MMReg:0x6184]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 182, text => [ { col => 0, table => 0, text => "D1OVL_DEPTH" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay pixel depth" }, { col => 3, table => 0, text => " 0=reserved " }, { col => 3, table => 0, text => " 1=16bpp " }, { col => 3, table => 0, text => " 2=32bpp " }, { col => 3, table => 0, text => " 3=reserved " }, { col => 0, table => 0, text => "D1OVL_Z" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Z[1:0] value for tiling" }, { col => 0, table => 0, text => "D1OVL_FORMAT" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay pixel format. It is used together with ", }, { col => 3, table => 0, text => "D1OVL_DEPTH to define the overlay format.", }, { col => 3, table => 0, text => " If (D1OVL_DEPTH = 0x1)(16 bpp)" }, { col => 3, table => 0, text => " 0x0- ARGB 1555" }, { col => 3, table => 0, text => " 0x1 - RGB 565" }, { col => 3, table => 0, text => " 0x2 - BGRA 5551" }, { col => 3, table => 0, text => " others - reserved" }, { col => 3, table => 0, text => "else if (D1OVL_DEPTH = 0x2)(32 bpp)" }, { col => 3, table => 0, text => " 0x0 - ACrYCb 8888 or ARGB 8888" }, { col => 3, table => 0, text => " 0x1 - ACrYCb 2101010 or ARGB 2101010" }, { col => 3, table => 0, text => " 0x2 - CbACrA or BGRA 1010102" }, { col => 3, table => 0, text => " others - reserved" }, { col => 0, table => 0, text => "D1OVL_TILE_COMPACT_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables multichip tile compaction" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "D1OVL_ADDRESS_TRANSLATION_EN" }, { col => 0, table => 0, text => "ABLE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables Overlay 1 address translation" }, { col => 3, table => 0, text => " 0=0: physical memory " }, { col => 3, table => 0, text => " 1=1: virtual memory " }, { col => 0, table => 0, text => "D1OVL_PRIVILEGED_ACCESS_ENABL" }, { col => 0, table => 0, text => "E" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables Overlay 1 privileged access" }, { col => 3, table => 0, text => " 0=0: no privileged access " }, { col => 3, table => 0, text => " 1=1: privileged access " }, { col => 0, table => 0, text => "D1OVL_ARRAY_MODE" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Defines the tiling mode" }, { col => 3, table => 0, text => " 0=ARRAY_LINEAR_GENERAL: Unaligned linear array ", }, { col => 3, table => 0, text => " 1=ARRAY_LINEAR_ALIGNED: Aligned linear array ", }, { col => 3, table => 0, text => " 2=ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles ", }, { col => 3, table => 0, text => " 3=ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles ", }, { col => 3, table => 0, text => " 4=ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles ", }, { col => 3, table => 0, text => " 5=ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high ", }, { col => 3, table => 0, text => " 6=ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high ", }, { col => 3, table => 0, text => " 7=ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles ", }, { col => 3, table => 0, text => " 8=ARRAY_2B_TILED_THIN1: uses row bank swapping ", }, { col => 3, table => 0, text => " 9=ARRAY_2B_TILED_THIN2: uses row bank swapping ", }, { col => 3, table => 0, text => " 10=ARRAY_2B_TILED_THIN4: uses row bank swapping ", }, { col => 3, table => 0, text => " 11=ARRAY_2B_TILED_THICK: uses row bank swapping ", }, { col => 3, table => 0, text => " 12=ARRAY_3D_TILED_THIN1: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 13=ARRAY_3D_TILED_THICK: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 14=ARRAY_3B_TILED_THIN1: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 15=ARRAY_3B_TILED_THICK: Slices are pipe rotated ", }, { col => 0, table => 0, text => "D1OVL_COLOR_EXPANSION_MODE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay pixel format expansion mode.", }, { col => 3, table => 0, text => " 0=dynamic expansion for RGB " }, { col => undef, table => undef, text => " 1=zero expansion for YCbCr " }, { col => undef, table => undef, text => "Primary overlay pixel depth and format.", }, { col => "heading", table => 1, text => "D1OVL_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x6188]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_HALF_RESOLUTION_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary overlay half resolution control" }, { col => 3, table => 1, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Primary overlay half resolution control", }, ], }, { num => 183, text => [ { col => "heading", table => 0, text => "D1OVL_SWAP_CNTL - RW - 32 bits - [GpuF0MMReg:0x618C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_ENDIAN_SWAP" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "MC endian swap select" }, { col => 3, table => 0, text => " 0=0=none " }, { col => 3, table => 0, text => " 1=1=8in16(0xaabb=>0xbbaa) " }, { col => 3, table => 0, text => " 2=2=8in32(0xaabbccdd=>0xddccbbaa) " }, { col => 3, table => 0, text => " 3=3=8in64(0xaabbccddeeff0011=>0x1100ffeeddccbbaa) ", }, { col => 0, table => 0, text => "D1OVL_RED_CROSSBAR" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0Red crossbar select" }, { col => 3, table => 0, text => " 0=0=select from R " }, { col => 3, table => 0, text => " 1=1=select from G " }, { col => 3, table => 0, text => " 2=2=select from B " }, { col => 3, table => 0, text => " 3=3=select from A " }, { col => 0, table => 0, text => "D1OVL_GREEN_CROSSBAR" }, { col => 1, table => 0, text => "7:6" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Green crossbar select" }, { col => 3, table => 0, text => " 0=0=select from G " }, { col => 3, table => 0, text => " 1=1=select from B " }, { col => 3, table => 0, text => " 2=2=select from A " }, { col => 3, table => 0, text => " 3=3=select from R " }, { col => 0, table => 0, text => "D1OVL_BLUE_CROSSBAR" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Blue crossbar select" }, { col => 3, table => 0, text => " 0=0=select from B " }, { col => 3, table => 0, text => " 1=1=select from A " }, { col => 3, table => 0, text => " 2=2=select from R " }, { col => 3, table => 0, text => " 3=3=select from G " }, { col => 0, table => 0, text => "D1OVL_ALPHA_CROSSBAR" }, { col => 1, table => 0, text => "11:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Alpha crossbar select" }, { col => 3, table => 0, text => " 0=0=select from A " }, { col => 3, table => 0, text => " 1=1=select from R " }, { col => 3, table => 0, text => " 2=2=select from G " }, { col => undef, table => undef, text => " 3=3=select from B " }, { col => undef, table => undef, text => "Endian swap and component reorder control", }, { col => undef, table => undef, text => "D1OVL_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6190]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1OVL_DFQ_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Surface address DFQ enable" }, { col => undef, table => undef, text => "D1OVL_SURFACE_ADDRESS" }, { col => undef, table => undef, text => "31:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Primary overlay surface base address in byte. It is 256 ", }, { col => undef, table => undef, text => "bytes aligned." }, { col => undef, table => undef, text => "Primary overlay surface base address in byte.", }, { col => "heading", table => 1, text => "D1OVL_PITCH - RW - 32 bits - [GpuF0MMReg:0x6198]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_PITCH" }, { col => 1, table => 1, text => "13:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary overlay surface pitch in pixels. For ", }, { col => 3, table => 1, text => "Micro-tiled/Macro-tiled surface, it must be multiple of 64 ", }, { col => 3, table => 1, text => "pixeld in 8bpp mode. For Micro-linear/Macro-tiled surface, it ", }, { col => 3, table => 1, text => "must be multiple of 256 pixeld in 8bpp mode, multiple of 128 ", }, { col => 3, table => 1, text => "pixels in 16bpp mode and multiple of 64 pixels in 32bpp ", }, { col => 3, table => 1, text => "mode. For Micro-linear/Macro-linear surface, it must be ", }, { col => 3, table => 1, text => "multiple of 64 pixels in 8bpp mode. For other modes, it must ", }, { col => 3, table => 1, text => "be multiple of 32." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, ], }, { num => 184, text => [ { col => undef, table => undef, text => "Primary overlay surface pitch in pixels.", }, { col => "heading", table => 0, text => "D1OVL_SURFACE_OFFSET_X - RW - 32 bits - [GpuF0MMReg:0x619C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_SURFACE_OFFSET_X" }, { col => 1, table => 0, text => "12:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay X surface offset. It is 256 pixels aligned.", }, { col => undef, table => undef, text => "NOTE: Bits 0:7 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary overlay X surface offset.", }, { col => "heading", table => 1, text => "D1OVL_SURFACE_OFFSET_Y - RW - 32 bits - [GpuF0MMReg:0x61A0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_SURFACE_OFFSET_Y" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary overlay Y surface offset. It is even value.", }, { col => undef, table => undef, text => "NOTE: Bit 0 of this field is hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary overlay Y surface offset.", }, { col => "heading", table => 2, text => "D1OVL_START - RW - 32 bits - [GpuF0MMReg:0x61A4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_Y_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary overlay Y start coordinate relative to the desktop ", }, { col => 3, table => 2, text => "coordinates." }, { col => 0, table => 2, text => "D1OVL_X_START" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary overlay X start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Primary overlay X, Y start coordinate relative to the desktop coordinates.", }, { col => "heading", table => 3, text => "D1OVL_END - RW - 32 bits - [GpuF0MMReg:0x61A8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_Y_END" }, { col => 1, table => 3, text => "13:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay Y end coordinate relative to the desktop ", }, { col => 3, table => 3, text => "coordinates. It is exclusive and the maximum value is 8K.", }, { col => 0, table => 3, text => "D1OVL_X_END" }, { col => 1, table => 3, text => "29:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay X end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K.", }, { col => undef, table => undef, text => "Primary overlay X, Y end coordinate relative to the desktop coordinates.", }, { col => "heading", table => 4, text => "D1OVL_UPDATE - RW - 32 bits - [GpuF0MMReg:0x61AC]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 185, text => [ { col => 0, table => 0, text => "D1OVL_UPDATE_PENDING (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay register update pending control. It is set to ", }, { col => 3, table => 0, text => "1 after a host write to overlay double buffer register. It is ", }, { col => 3, table => 0, text => "cleared after double buffering is done. The double buffering ", }, { col => 3, table => 0, text => "occurs when UPDATE_PENDING = 1 and UPDATE_LOCK ", }, { col => 3, table => 0, text => "= 0 and V_UPDATE = 1." }, { col => 3, table => 0, text => "If CRTC1 is disabled, the registers will be updated instantly.", }, { col => 3, table => 0, text => "D1OVL double buffer registers include:" }, { col => 3, table => 0, text => "D1OVL_ENABLE" }, { col => 3, table => 0, text => "D1OVL_DEPTH" }, { col => 3, table => 0, text => "D1OVL_FORMAT" }, { col => 3, table => 0, text => "D1OVL_SWAP_RB" }, { col => 3, table => 0, text => "D1OVL_COLOR_EXPANSION_MODE" }, { col => 3, table => 0, text => "D1OVL_HALF_RESOLUTION_ENABLE" }, { col => 3, table => 0, text => "D1OVL_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D1OVL_PITCH" }, { col => 3, table => 0, text => "D1OVL_SURFACE_OFFSET_X" }, { col => 3, table => 0, text => "D1OVL_SURFACE_OFFSET_Y" }, { col => 3, table => 0, text => "D1OVL_START" }, { col => 3, table => 0, text => "D1OVL_END" }, { col => 3, table => 0, text => " 0=No update pending " }, { col => 3, table => 0, text => " 1=Update pending " }, { col => 0, table => 0, text => "D1OVL_UPDATE_TAKEN (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay update taken status. It is set to 1 when ", }, { col => 3, table => 0, text => "double buffering occurs and cleared when V_UPDATE = 0.", }, { col => 0, table => 0, text => "D1OVL_UPDATE_LOCK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay register update lock control.", }, { col => 3, table => 0, text => " 0=Unlocked " }, { col => 3, table => 0, text => " 1=Locked " }, { col => 0, table => 0, text => "D1OVL_DISABLE_MULTIPLE_UPDATE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D1OVL registers can be updated multiple times in one ", }, { col => 3, table => 0, text => "V_UPDATE period " }, { col => 3, table => 0, text => " 1=D1OVL registers can only be updated once in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => "Primary overlay register update" }, { col => "heading", table => 1, text => "D1OVL_SURFACE_ADDRESS_INUSE - RW - 32 bits - [GpuF0MMReg:0x61B0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_SURFACE_ADDRESS_INUSE " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => "31:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This register reads back snapshot of primary overlay ", }, { col => 3, table => 1, text => "surface address used for data request. The address is the ", }, { col => 3, table => 1, text => "signal sent to DMIF and is updated on SOF or horizontal ", }, { col => 3, table => 1, text => "surface update. The snapshot is triggered by writing 1 into ", }, { col => 3, table => 1, text => "field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC ", }, { col => undef, table => undef, text => "register D1CRTC_SNAPSHOT_STATUS.", }, { col => undef, table => undef, text => "Snapshot of primary overlay surface address in use", }, { col => "heading", table => 2, text => "D1OVL_DFQ_CONTROL - RW - 32 bits - [GpuF0MMReg:0x61B4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_DFQ_RESET" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reset the deep flip queue" }, { col => 0, table => 2, text => "D1OVL_DFQ_SIZE" }, { col => 1, table => 2, text => "6:4" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Size of the deep flip queue: 0 = 1 deep queue, 1 = 2 deep ", }, { col => 3, table => 2, text => "queue,..., 7 = 8 deep queue" }, { col => 0, table => 2, text => "D1OVL_DFQ_MIN_FREE_ENTRIES" }, { col => 1, table => 2, text => "10:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Minimum # of free entries before surface pending is ", }, { col => undef, table => undef, text => "asserted" }, { col => undef, table => undef, text => "Control of the deep flip queue for D1 overlay", }, ], }, { num => 186, text => [ { col => undef, table => undef, text => "2.7.3" }, { col => undef, table => undef, text => " Primary Display Video Overlay Transform Registers", }, { col => "heading", table => 0, text => "D1OVL_DFQ_STATUS - RW - 32 bits - [GpuF0MMReg:0x61B8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_DFQ_NUM_ENTRIES (R)" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "# of entries in deep flip queue. 0 = 1 entry, 1 = 2 entries, ... 7 ", }, { col => 3, table => 0, text => "= 8 entries" }, { col => 0, table => 0, text => "D1OVL_DFQ_RESET_FLAG (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Sticky bit: Deep flip queue in reset" }, { col => 0, table => 0, text => "D1OVL_DFQ_RESET_ACK (W)" }, { col => 1, table => 0, text => 9 }, { col => undef, table => undef, text => "0x0Clear D1OVL_DFQ_RESET_FLAG" }, { col => undef, table => undef, text => "Status of the deep flip queue for D1 overlay", }, { col => "heading", table => 1, text => "D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL - RW - 32 bits - [GpuF0MMReg:0x6140]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_COLOR_MATRIX_TRANSFORM" }, { col => 0, table => 1, text => "ATION_CNTL" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Matrix transformation control for primary display overlay ", }, { col => 3, table => 1, text => "pixels. It is used when PIX_TYPE is 0." }, { col => 3, table => 1, text => " 0=No color space adjustment on display output of overlay ", }, { col => 3, table => 1, text => "pixels " }, { col => 3, table => 1, text => " 1=Apply display x color spcae control on the overlay ", }, { col => 3, table => 1, text => "pixels based on DxCOLOR_MATRIX_COEF register ", }, { col => 3, table => 1, text => "settings " }, { col => 3, table => 1, text => " 2=Convert overlay pixel to standard definition YCbCr(601) ", }, { col => 3, table => 1, text => "color space " }, { col => 3, table => 1, text => " 3=Convert overlay pixels to high definition YCbCR(709) ", }, { col => 3, table => 1, text => "color space " }, { col => 3, table => 1, text => " 4=Convert overlay pixels to high definition TVRGB color ", }, { col => undef, table => undef, text => "space " }, { col => undef, table => undef, text => "Matrix transformation control for primary display overlay pixels.", }, { col => "heading", table => 2, text => "D1OVL_MATRIX_TRANSFORM_EN - RW - 32 bits - [GpuF0MMReg:0x6200]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_MATRIX_TRANSFORM_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary overlay matrix conversion enable", }, { col => 3, table => 2, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Primary overlay matrix conversion enable.", }, { col => "heading", table => 3, text => "D1OVL_MATRIX_COEF_1_1 - RW - 32 bits - [GpuF0MMReg:0x6204]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_MATRIX_COEF_1_1" }, { col => 1, table => 3, text => "18:0" }, { col => 2, table => 3, text => "0x198a0" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 3, text => "S3.11." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, ], }, { num => 187, text => [ { col => 0, table => 0, text => "D1OVL_MATRIX_SIGN_1_1" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 1, text => "D1OVL_MATRIX_COEF_1_2 - RW - 32 bits - [GpuF0MMReg:0x6208]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_MATRIX_COEF_1_2" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x12a20" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 1, text => "S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1OVL_MATRIX_SIGN_1_2" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 2, text => "D1OVL_MATRIX_COEF_1_3 - RW - 32 bits - [GpuF0MMReg:0x620C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_MATRIX_COEF_1_3" }, { col => 1, table => 2, text => "18:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 2, text => "S3.11." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1OVL_MATRIX_SIGN_1_3" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 3, text => "D1OVL_MATRIX_COEF_1_4 - RW - 32 bits - [GpuF0MMReg:0x6210]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_MATRIX_COEF_1_4" }, { col => 1, table => 3, text => "26:8" }, { col => 2, table => 3, text => "0x48700" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 3, text => "S11.1." }, { col => 3, table => 3, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D1OVL_MATRIX_SIGN_1_4" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 4, text => "D1OVL_MATRIX_COEF_2_1 - RW - 32 bits - [GpuF0MMReg:0x6214]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1OVL_MATRIX_COEF_2_1" }, { col => 1, table => 4, text => "18:0" }, { col => 2, table => 4, text => "0x72fe0" }, { col => 3, table => 4, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 4, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 4, text => "S3.11." }, { col => 3, table => 4, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 4, text => "D1OVL_MATRIX_SIGN_2_1" }, { col => 1, table => 4, text => 31 }, { col => 2, table => 4, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, ], }, { num => 188, text => [ { col => "heading", table => 0, text => "D1OVL_MATRIX_COEF_2_2 - RW - 32 bits - [GpuF0MMReg:0x6218]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_MATRIX_COEF_2_2" }, { col => 1, table => 0, text => "18:0" }, { col => 2, table => 0, text => "0x12a20" }, { col => 3, table => 0, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 0, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 0, text => "S3.11." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D1OVL_MATRIX_SIGN_2_2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 1, text => "D1OVL_MATRIX_COEF_2_3 - RW - 32 bits - [GpuF0MMReg:0x621C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_MATRIX_COEF_2_3" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x79bc0" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 1, text => "S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1OVL_MATRIX_SIGN_2_3" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 2, text => "D1OVL_MATRIX_COEF_2_4 - RW - 32 bits - [GpuF0MMReg:0x6220]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_MATRIX_COEF_2_4" }, { col => 1, table => 2, text => "26:8" }, { col => 2, table => 2, text => "0x22100" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 2, text => "S11.1." }, { col => 3, table => 2, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1OVL_MATRIX_SIGN_2_4" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 3, text => "D1OVL_MATRIX_COEF_3_1 - RW - 32 bits - [GpuF0MMReg:0x6224]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_MATRIX_COEF_3_1" }, { col => 1, table => 3, text => "18:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 3, text => "S3.11." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D1OVL_MATRIX_SIGN_3_1" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, ], }, { num => 189, text => [ { col => undef, table => undef, text => "2.7.4" }, { col => undef, table => undef, text => "Primary Display Video Overlay Gamma Correction Registers", }, { col => "heading", table => 0, text => "D1OVL_MATRIX_COEF_3_2 - RW - 32 bits - [GpuF0MMReg:0x6228]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_MATRIX_COEF_3_2" }, { col => 1, table => 0, text => "18:0" }, { col => 2, table => 0, text => "0x12a20" }, { col => 3, table => 0, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 0, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 0, text => "S3.11." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D1OVL_MATRIX_SIGN_3_2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 1, text => "D1OVL_MATRIX_COEF_3_3 - RW - 32 bits - [GpuF0MMReg:0x622C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_MATRIX_COEF_3_3" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x20460" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 1, text => "S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1OVL_MATRIX_SIGN_3_3" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 2, text => "D1OVL_MATRIX_COEF_3_4 - RW - 32 bits - [GpuF0MMReg:0x6230]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_MATRIX_COEF_3_4" }, { col => 1, table => 2, text => "26:8" }, { col => 2, table => 2, text => "0x3af80" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for primary overlay. Format fix-point ", }, { col => 3, table => 2, text => "S11.1." }, { col => 3, table => 2, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1OVL_MATRIX_SIGN_3_4" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for primary overlay.", }, { col => "heading", table => 3, text => "D1OVL_PWL_TRANSFORM_EN - RW - 32 bits - [GpuF0MMReg:0x6280]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_PWL_TRANSFORM_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay gamma correction enable.", }, { col => 3, table => 3, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Primary overlay gamma correction enable.", }, { col => undef, table => undef, text => "D1OVL_PWL_0TOF - RW - 32 bits - [GpuF0MMReg:0x6284]", }, ], }, { num => 190, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_PWL_0TOF_OFFSET" }, { col => 1, table => 0, text => "8:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 0x0-0xF. Format fix-point 8.1 (0.0 to +255.5).", }, { col => 0, table => 0, text => "D1OVL_PWL_0TOF_SLOPE" }, { col => 1, table => 0, text => "26:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "0x0-0xF. Format fix-point 3.8 (0.00 to +7.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 0x0-0xF", }, { col => "heading", table => 1, text => "D1OVL_PWL_10TO1F - RW - 32 bits - [GpuF0MMReg:0x6288]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_PWL_10TO1F_OFFSET" }, { col => 1, table => 1, text => "8:0" }, { col => 2, table => 1, text => "0x20" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 0x10-0x1F. Format fix-point 8.1 (0.0 to +255.5).", }, { col => 0, table => 1, text => "D1OVL_PWL_10TO1F_SLOPE" }, { col => 1, table => 1, text => "26:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "0x10-0x1F. Format fix-point 3.8 (0.00 to +7.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 0x10-0x1F", }, { col => "heading", table => 2, text => "D1OVL_PWL_20TO3F - RW - 32 bits - [GpuF0MMReg:0x628C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_PWL_20TO3F_OFFSET" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x40" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 0x20-0x3F. Format fix-point 9.1 (0.0 to +511.5).", }, { col => 0, table => 2, text => "D1OVL_PWL_20TO3F_SLOPE" }, { col => 1, table => 2, text => "25:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "0x20-0x3F. Format fix-point 2.8 (0.00 to +3.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 0x20-0x3F", }, { col => "heading", table => 3, text => "D1OVL_PWL_40TO7F - RW - 32 bits - [GpuF0MMReg:0x6290]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_PWL_40TO7F_OFFSET" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x80" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 40-7F. Format fix-point 9.1 (0.0 to +511.5).", }, { col => 0, table => 3, text => "D1OVL_PWL_40TO7F_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "40-7F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 40-7F.", }, { col => "heading", table => 4, text => "D1OVL_PWL_80TOBF - RW - 32 bits - [GpuF0MMReg:0x6294]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1OVL_PWL_80TOBF_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 80-BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D1OVL_PWL_80TOBF_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "80-BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 80-BF.", }, ], }, { num => 191, text => [ { col => "heading", table => 0, text => "D1OVL_PWL_C0TOFF - RW - 32 bits - [GpuF0MMReg:0x6298]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_PWL_C0TOFF_OFFSET" }, { col => 1, table => 0, text => "10:0" }, { col => 2, table => 0, text => "0x180" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input C0-FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 0, text => "D1OVL_PWL_C0TOFF_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "C0-FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input C0-FF.", }, { col => "heading", table => 1, text => "D1OVL_PWL_100TO13F - RW - 32 bits - [GpuF0MMReg:0x629C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_PWL_100TO13F_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x200" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 100-13F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D1OVL_PWL_100TO13F_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "100-13F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 100-13F.", }, { col => "heading", table => 2, text => "D1OVL_PWL_140TO17F - RW - 32 bits - [GpuF0MMReg:0x62A0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_PWL_140TO17F_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x280" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 140-17F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D1OVL_PWL_140TO17F_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "140-17F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 140-17F.", }, { col => "heading", table => 3, text => "D1OVL_PWL_180TO1BF - RW - 32 bits - [GpuF0MMReg:0x62A4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_PWL_180TO1BF_OFFSET" }, { col => 1, table => 3, text => "10:0" }, { col => 2, table => 3, text => "0x300" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 180-1BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 3, text => "D1OVL_PWL_180TO1BF_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "180-1BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 180-1BF.", }, { col => "heading", table => 4, text => "D1OVL_PWL_1C0TO1FF - RW - 32 bits - [GpuF0MMReg:0x62A8]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1OVL_PWL_1C0TO1FF_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x380" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 1C0-1FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D1OVL_PWL_1C0TO1FF_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "1C0-1FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 1C0-1FF.", }, ], }, { num => 192, text => [ { col => "heading", table => 0, text => "D1OVL_PWL_200TO23F - RW - 32 bits - [GpuF0MMReg:0x62AC]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_PWL_200TO23F_OFFSET" }, { col => 1, table => 0, text => "10:0" }, { col => 2, table => 0, text => "0x400" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 200-23F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 0, text => "D1OVL_PWL_200TO23F_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "200-23F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 200-23F.", }, { col => "heading", table => 1, text => "D1OVL_PWL_240TO27F - RW - 32 bits - [GpuF0MMReg:0x62B0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_PWL_240TO27F_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x480" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 240-27F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D1OVL_PWL_240TO27F_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "240-27F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 240-27F.", }, { col => "heading", table => 2, text => "D1OVL_PWL_280TO2BF - RW - 32 bits - [GpuF0MMReg:0x62B4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_PWL_280TO2BF_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x500" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 280-2BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D1OVL_PWL_280TO2BF_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "280-2BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 280-2BF.", }, { col => "heading", table => 3, text => "D1OVL_PWL_2C0TO2FF - RW - 32 bits - [GpuF0MMReg:0x62B8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_PWL_2C0TO2FF_OFFSET" }, { col => 1, table => 3, text => "10:0" }, { col => 2, table => 3, text => "0x580" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 2C0-2FF. Format fix-point 10.1(0.0 to +1023.5).", }, { col => 0, table => 3, text => "D1OVL_PWL_2C0TO2FF_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "2C0-2FF. Format fix-point 1.8(0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 2C0-2FF.", }, { col => "heading", table => 4, text => "D1OVL_PWL_300TO33F - RW - 32 bits - [GpuF0MMReg:0x62BC]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1OVL_PWL_300TO33F_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x600" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 300-33F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D1OVL_PWL_300TO33F_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "300-33F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 300-33F.", }, ], }, { num => 193, text => [ { col => undef, table => undef, text => "2.7.5" }, { col => undef, table => undef, text => "Primary Display Graphics and Overlay Blending Registers", }, { col => "heading", table => 0, text => "D1OVL_PWL_340TO37F - RW - 32 bits - [GpuF0MMReg:0x62C0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_PWL_340TO37F_OFFSET" }, { col => 1, table => 0, text => "10:0" }, { col => 2, table => 0, text => "0x680" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 340-37F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 0, text => "D1OVL_PWL_340TO37F_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "340-37F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 340-37F.", }, { col => "heading", table => 1, text => "D1OVL_PWL_380TO3BF - RW - 32 bits - [GpuF0MMReg:0x62C4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_PWL_380TO3BF_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x700" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 380-3BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D1OVL_PWL_380TO3BF_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "380-3BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 380-3BF.", }, { col => "heading", table => 2, text => "D1OVL_PWL_3C0TO3FF - RW - 32 bits - [GpuF0MMReg:0x62C8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_PWL_3C0TO3FF_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x780" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 3C0-3FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D1OVL_PWL_3C0TO3FF_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Primary overlay gamma correction non-linear slope for input ", }, { col => undef, table => undef, text => "3C0-3FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Primary overlay gamma correction non-linear offset and slope for input 3C0-3FF.", }, { col => undef, table => undef, text => "D1OVL_KEY_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6300]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1GRPH_KEY_FUNCTION" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Selects graphic keyer result equation for primary display.", }, { col => undef, table => undef, text => " 0=GRPH1_KEY = FALSE = 0 " }, { col => undef, table => undef, text => " 1=GRPH1_KEY = TRUE = 1 " }, { col => undef, table => undef, text => " 2=GPPH1_KEY = (GRPH1_RED in range) AND ", }, { col => undef, table => undef, text => "(GRPH1_GREEN in range) AND (GRPH1_BLUE in range) ", }, { col => undef, table => undef, text => "AND(GRPH1_ALPHA in range) " }, { col => undef, table => undef, text => " 3=GRPH1_KEY = not [(GRPH1_RED in range) AND ", }, { col => undef, table => undef, text => "(GRPH1_GREEN in range) AND (GRPH1_BLUE in range) ", }, { col => undef, table => undef, text => "AND(GRPH1_ALPHA in range)] " }, ], }, { num => 194, text => [ { col => 0, table => 0, text => "D1OVL_KEY_FUNCTION" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects overlay keyer result equation for primary display.", }, { col => 3, table => 0, text => " 0=OVL1_KEY = FALSE = 0 " }, { col => 3, table => 0, text => " 1=OVL1_KEY = TRUE = 1 " }, { col => 3, table => 0, text => " 2=OVL1_KEY = (OVL1_Cr_RED in range) AND ", }, { col => 3, table => 0, text => "(OVL1_Y_GREEN in range) AND (OVL1_Cb_BLUE in ", }, { col => 3, table => 0, text => "range) AND (OVL1_ALPHA in range) " }, { col => 3, table => 0, text => " 3=OVL1_KEY = not [(OVL1_Cr_RED in range) AND ", }, { col => 3, table => 0, text => "(OVL1_Y_GREEN in range) AND (OVL1_Cb_BLUE in ", }, { col => 3, table => 0, text => "range) AND (OVL1_ALPHA in range)] " }, { col => 0, table => 0, text => "D1OVL_KEY_COMPARE_MIX" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects final mix of graphics and overlay keys for primary ", }, { col => 3, table => 0, text => "display." }, { col => 3, table => 0, text => " 0=GRPH_OVL_KEY = GRPH_KEY or OVL_KEY ", }, { col => undef, table => undef, text => " 1=GRPH_OVL_KEY = GRPH_KEY and OVL_KEY ", }, { col => undef, table => undef, text => "Primary display key control" }, { col => "heading", table => 1, text => "D1GRPH_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6304]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_ALPHA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "Global graphic alpha for use in key mode and global alpha ", }, { col => 3, table => 1, text => "modes. See D1OVL_ALPHA_MODE register filed for more ", }, { col => undef, table => undef, text => "details" }, { col => undef, table => undef, text => "Global graphic alpha for use in key mode and global alpha modes.", }, { col => "heading", table => 2, text => "D1OVL_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6308]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_ALPHA" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "Global overlay alpha for use in key mode and global alpha ", }, { col => 3, table => 2, text => "modes. See D1OVL_ALPHA_MODE register filed for more ", }, { col => undef, table => undef, text => "details" }, { col => undef, table => undef, text => "Global overlay alpha for use in key mode and global alpha modes.", }, { col => undef, table => undef, text => "D1OVL_ALPHA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x630C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1OVL_ALPHA_MODE" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Graphics/overlay alpha blending mode for primary ", }, { col => undef, table => undef, text => "controller." }, { col => undef, table => undef, text => "In any case, if there is only graphics, the input OVL_DATA ", }, { col => undef, table => undef, text => "is forced to blank. If there is only overlay, the input ", }, { col => undef, table => undef, text => "GRPH_DATA is forced to blank." }, { col => undef, table => undef, text => " 0=Keyer mode, select graphic or overlay keyer to mix ", }, { col => undef, table => undef, text => "graphics and overlay " }, { col => undef, table => undef, text => " 1=Per pixel graphic alpha mode.Alpha blend graphic and ", }, { col => undef, table => undef, text => "overlay layer. The alpha from graphic pixel may be inverted ", }, { col => undef, table => undef, text => "according to register field " }, { col => undef, table => undef, text => " 2=Global alpha mode " }, { col => undef, table => undef, text => " 3=Per pixel overlay alpha mode ", }, ], }, { num => 195, text => [ { col => 0, table => 0, text => "D1OVL_ALPHA_PREMULT" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For use with per pixel alpha blend mode. Selects whether ", }, { col => 3, table => 0, text => "pre-multiplied alpha or non-multiplied alpha.", }, { col => 3, table => 0, text => " 0=0x0 - When DxOVL_ALPHA_MODE = 0x1, then Pixel = ", }, { col => 3, table => 0, text => "PIX_ALPHA * graphics pixel + (1-PIX_ALPHA) * overlay ", }, { col => 3, table => 0, text => "pixel.When DxOVL_ALPHA_MODE = 0x3, then Pixel = ", }, { col => 3, table => 0, text => "PIX_ALPHA * overlay pixel + (1-PIX_ALPHA) * graphic ", }, { col => 3, table => 0, text => "pixel " }, { col => 3, table => 0, text => " 1=0x1 - When DxOVL_ALPHA_MODE = 0x1, then Pixel = ", }, { col => 3, table => 0, text => "graphic pixel + (1-PIX_ALPHA) * overlay pixel.When ", }, { col => 3, table => 0, text => "DxOVL_ALPHA_MODE = 0x3, then Pixel = overlay pixel + ", }, { col => 3, table => 0, text => "(1-PIX_ALPHA) * graphic pixel " }, { col => 0, table => 0, text => "D1OVL_ALPHA_INV" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For use with pixel blend mode. Apply optional inversion to ", }, { col => 3, table => 0, text => "the alpha value extracted form the graphics or overlay ", }, { col => 3, table => 0, text => "surface data." }, { col => 3, table => 0, text => " 0=PIX_ALPHA = alpha from graphics or overlay ", }, { col => undef, table => undef, text => " 1=PIX_ALPHA = 1 - alpha from graphics or overlay ", }, { col => undef, table => undef, text => "Primary display graphics/overlay alpha blending control", }, { col => "heading", table => 1, text => "D1GRPH_KEY_RANGE_RED - RW - 32 bits - [GpuF0MMReg:0x6310]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_KEY_RED_LOW" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphics keyer red component lower limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D1GRPH_KEY_RED_HIGH" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphics keyer red component upper limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary graphics keyer red component range", }, { col => "heading", table => 2, text => "D1GRPH_KEY_RANGE_GREEN - RW - 32 bits - [GpuF0MMReg:0x6314]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_KEY_GREEN_LOW" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary graphics keyer green component lower limit.", }, { col => 3, table => 2, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 2, text => "all zeros." }, { col => 0, table => 2, text => "D1GRPH_KEY_GREEN_HIGH" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary graphics keyer green component upper limit.", }, { col => 3, table => 2, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary graphics keyer green component range", }, { col => undef, table => undef, text => "D1GRPH_KEY_RANGE_BLUE - RW - 32 bits - [GpuF0MMReg:0x6318]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1GRPH_KEY_BLUE_LOW" }, { col => undef, table => undef, text => "15:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Primary graphics keyer blue component lower limit.", }, { col => undef, table => undef, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, ], }, { num => 196, text => [ { col => 0, table => 0, text => "D1GRPH_KEY_BLUE_HIGH" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary graphics keyer blue component upper limit.", }, { col => 3, table => 0, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary graphics keyer blue component range", }, { col => "heading", table => 1, text => "D1GRPH_KEY_RANGE_ALPHA - RW - 32 bits - [GpuF0MMReg:0x631C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1GRPH_KEY_ALPHA_LOW" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0Primary graphics keyer alpha component lower limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D1GRPH_KEY_ALPHA_HIGH" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary graphics keyer alpha component upper limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary graphics keyer alpha component range", }, { col => "heading", table => 2, text => "D1OVL_KEY_RANGE_RED_CR - RW - 32 bits - [GpuF0MMReg:0x6320]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_KEY_RED_CR_LOW" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary overlay keyer red component lower limit.", }, { col => 3, table => 2, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 2, text => "all zeros." }, { col => 0, table => 2, text => "D1OVL_KEY_RED_CR_HIGH" }, { col => 1, table => 2, text => "25:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary overlay keyer red component upper limit.", }, { col => 3, table => 2, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary overlay keyer red component range", }, { col => "heading", table => 3, text => "D1OVL_KEY_RANGE_GREEN_Y - RW - 32 bits - [GpuF0MMReg:0x6324]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1OVL_KEY_GREEN_Y_LOW" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay keyer green component lower limit.", }, { col => 3, table => 3, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 3, text => "all zeros." }, { col => 0, table => 3, text => "D1OVL_KEY_GREEN_Y_HIGH" }, { col => 1, table => 3, text => "25:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary overlay keyer green component upper limit.", }, { col => 3, table => 3, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary overlay keyer green component range", }, { col => "heading", table => 4, text => "D1OVL_KEY_RANGE_BLUE_CB - RW - 32 bits - [GpuF0MMReg:0x6328]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 197, text => [ { col => undef, table => undef, text => "2.7.6" }, { col => undef, table => undef, text => "Primary Display Color Matrix Transform Registers", }, { col => 0, table => 0, text => "D1OVL_KEY_BLUE_CB_LOW" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay keyer blue component lower limit.", }, { col => 3, table => 0, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 0, text => "all zeros." }, { col => 0, table => 0, text => "D1OVL_KEY_BLUE_CB_HIGH" }, { col => 1, table => 0, text => "25:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary overlay keyer blue component upper limit.", }, { col => 3, table => 0, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary overlay keyer blue component range", }, { col => "heading", table => 1, text => "D1OVL_KEY_ALPHA - RW - 32 bits - [GpuF0MMReg:0x632C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_KEY_ALPHA_LOW" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary overlay keyer alpha component lower limit.", }, { col => 3, table => 1, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D1OVL_KEY_ALPHA_HIGH" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary overlay keyer alpha component upper limit.", }, { col => 3, table => 1, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Primary overlay keyer alpha component range", }, { col => "heading", table => 2, text => "D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL - RW - 32 bits - [GpuF0MMReg:0x6380]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1GRPH_COLOR_MATRIX_TRANSFOR" }, { col => 0, table => 2, text => "MATION_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Matrix transformation control for primary display graphics ", }, { col => 3, table => 2, text => "and cursor pixel. It is used when PIX_TYPE is 1.", }, { col => 3, table => 2, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Matrix transformation control for primary display graphics and cursor pixel.", }, { col => "heading", table => 3, text => "D1COLOR_MATRIX_COEF_1_1 - RW - 32 bits - [GpuF0MMReg:0x6384]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1COLOR_MATRIX_COEF_1_1" }, { col => 1, table => 3, text => "16:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C11 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 3, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D1COLOR_MATRIX_SIGN_1_1" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C11 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, ], }, { num => 198, text => [ { col => "heading", table => 0, text => "D1COLOR_MATRIX_COEF_1_2 - RW - 32 bits - [GpuF0MMReg:0x6388]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1COLOR_MATRIX_COEF_1_2" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Combined matrix constant C12 of RGB->YCbCr, contrast ", }, { col => 3, table => 0, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 0, text => "fix-point S0.11(-1.00 to + 0.99)." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D1COLOR_MATRIX_SIGN_1_2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C12 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 1, text => "D1COLOR_MATRIX_COEF_1_3 - RW - 32 bits - [GpuF0MMReg:0x638C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1COLOR_MATRIX_COEF_1_3" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C13 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 1, text => "fix-point S0.11(-1.0 to +0.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1COLOR_MATRIX_SIGN_1_3" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C13 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 2, text => "D1COLOR_MATRIX_COEF_1_4 - RW - 32 bits - [GpuF0MMReg:0x6390]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1COLOR_MATRIX_COEF_1_4" }, { col => 1, table => 2, text => "26:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C14 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 2, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => 3, table => 2, text => "of 512 offset" }, { col => 3, table => 2, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1COLOR_MATRIX_SIGN_1_4" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C14 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 3, text => "D1COLOR_MATRIX_COEF_2_1 - RW - 32 bits - [GpuF0MMReg:0x6394]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1COLOR_MATRIX_COEF_2_1" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C21 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 3, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D1COLOR_MATRIX_SIGN_2_1" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C21 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, ], }, { num => 199, text => [ { col => "heading", table => 0, text => "D1COLOR_MATRIX_COEF_2_2 - RW - 32 bits - [GpuF0MMReg:0x6398]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1COLOR_MATRIX_COEF_2_2" }, { col => 1, table => 0, text => "16:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Combined matrix constant C22 of RGB->YCbCr, contrast ", }, { col => 3, table => 0, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 0, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D1COLOR_MATRIX_SIGN_2_2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C22 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 1, text => "D1COLOR_MATRIX_COEF_2_3 - RW - 32 bits - [GpuF0MMReg:0x639C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1COLOR_MATRIX_COEF_2_3" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C23 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 1, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1COLOR_MATRIX_SIGN_2_3" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C23 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 2, text => "D1COLOR_MATRIX_COEF_2_4 - RW - 32 bits - [GpuF0MMReg:0x63A0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1COLOR_MATRIX_COEF_2_4" }, { col => 1, table => 2, text => "26:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C24 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 2, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => 3, table => 2, text => "of 512 offset" }, { col => 3, table => 2, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1COLOR_MATRIX_SIGN_2_4" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C24 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 3, text => "D1COLOR_MATRIX_COEF_3_1 - RW - 32 bits - [GpuF0MMReg:0x63A4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1COLOR_MATRIX_COEF_3_1" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C31 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 3, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D1COLOR_MATRIX_SIGN_3_1" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C31 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, ], }, { num => 200, text => [ { col => undef, table => undef, text => "2.7.7" }, { col => undef, table => undef, text => "Primary Display Subsampling Registers", }, { col => "heading", table => 0, text => "D1COLOR_MATRIX_COEF_3_2 - RW - 32 bits - [GpuF0MMReg:0x63A8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1COLOR_MATRIX_COEF_3_2" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Combined matrix constant C32 of RGB->YCbCr, contrast ", }, { col => 3, table => 0, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 0, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D1COLOR_MATRIX_SIGN_3_2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C32 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 1, text => "D1COLOR_MATRIX_COEF_3_3 - RW - 32 bits - [GpuF0MMReg:0x63AC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1COLOR_MATRIX_COEF_3_3" }, { col => 1, table => 1, text => "16:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C33 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 1, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D1COLOR_MATRIX_SIGN_3_3" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C33 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 2, text => "D1COLOR_MATRIX_COEF_3_4 - RW - 32 bits - [GpuF0MMReg:0x63B0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1COLOR_MATRIX_COEF_3_4" }, { col => 1, table => 2, text => "26:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C34 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for primary display. Format ", }, { col => 3, table => 2, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => 3, table => 2, text => "of 512 offset" }, { col => 3, table => 2, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D1COLOR_MATRIX_SIGN_3_4" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C34 of RGB->YCbCr, contrast and brightness adjustment for primary display.", }, { col => "heading", table => 3, text => "D1COLOR_SPACE_CONVERT - RW - 32 bits - [GpuF0MMReg:0x613C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1COLOR_SUBSAMPLE_CRCB_MODE" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Sub-sampling control for primary display", }, { col => 3, table => 3, text => " 0=do not subsample CrCb(RB) " }, { col => 3, table => 3, text => " 1=subsample CrCb (RB) by using 2 tap average method ", }, { col => 3, table => 3, text => " 2=subsample CrCb (RB) by using 1 tap on even pixel ", }, { col => undef, table => undef, text => " 3=subsample CrCb (RB) by using 1 tap on odd pixel ", }, { col => undef, table => undef, text => "Sub-sampling control for primary display.", }, ], }, { num => 201, text => [ { col => undef, table => undef, text => "2.7.8" }, { col => undef, table => undef, text => "Primary Display Realtime Overlay Registers", }, { col => "heading", table => 0, text => "D1OVL_RT_SKEWCOMMAND - RW - 32 bits - [GpuF0MMReg:0x6500]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1OVL_RT_CLEAR_GOBBLE_COUNT " }, { col => 0, table => 0, text => "(W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "writing 1 to this bit clear the gobbleCount ", }, { col => 3, table => 0, text => "this bit has higher priority than inc_gobblecount", }, { col => 0, table => 0, text => "D1OVL_RT_INC_GOBBLE_COUNT (W)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "writing 1 to this bit increments the gobbleCount", }, { col => 0, table => 0, text => "D1OVL_RT_CLEAR_SUBMIT_COUNT " }, { col => 0, table => 0, text => "(W)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "writing 1 to this bit clear the submitCount ", }, { col => 3, table => 0, text => "this bit has higher priority than inc_submitcount", }, { col => 0, table => 0, text => "D1OVL_RT_INC_SUBMIT_COUNT (W)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "writing 1 to this bit increments the submitCount", }, { col => 0, table => 0, text => "D1OVL_RT_GOBBLE_COUNT (R)" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "read only register" }, { col => 3, table => 0, text => "gobble count value which increments with each ", }, { col => 3, table => 0, text => "inc_gobble_count " }, { col => 3, table => 0, text => "and reset with clear_gobble_count commands.", }, { col => 3, table => 0, text => "it wraps around on overflow during increment.", }, { col => 0, table => 0, text => "D1OVL_RT_SUBMIT_COUNT (R)" }, { col => 1, table => 0, text => "26:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "read only register" }, { col => 3, table => 0, text => "submit count value which increments with each ", }, { col => 3, table => 0, text => "inc_submit_count " }, { col => 3, table => 0, text => "and reset with clear_submit_count commands.", }, { col => undef, table => undef, text => "it wraps around on overflow during increment.", }, { col => undef, table => undef, text => "reset or increment submit and gobble count", }, { col => "heading", table => 1, text => "D1OVL_RT_SKEWCONTROL - RW - 32 bits - [GpuF0MMReg:0x6504]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_RT_CAPS" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "max value in submitCount and gobbleCount", }, { col => 3, table => 1, text => "this is the number of contents buffer - 1", }, { col => 3, table => 1, text => "should reset counters before programming this field", }, { col => 0, table => 1, text => "D1OVL_RT_SKEW_MAX" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "max skew allowed between gobbleCount and submitCount", }, { col => undef, table => undef, text => "controls for submit and gobble counts", }, { col => "heading", table => 2, text => "D1OVL_RT_BAND_POSITION - RW - 32 bits - [GpuF0MMReg:0x6508]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1OVL_RT_TOP_SCAN" }, { col => 1, table => 2, text => "13:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "define the top scan line for the next RT (inclusive)", }, { col => 0, table => 2, text => "D1OVL_RT_BTM_SCAN" }, { col => 1, table => 2, text => "29:16" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "define the bottom scan line for next RT (exclusive)", }, { col => undef, table => undef, text => "the position of the top and bottom scan line for next RT", }, { col => undef, table => undef, text => "D1OVL_RT_PROCEED_COND - RW - 32 bits - [GpuF0MMReg:0x650C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1OVL_RT_REDUCE_DELAY" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "0 selects delay optimized scheme", }, { col => undef, table => undef, text => "1 selects basic render behind delay scan scheme", }, ], }, { num => 202, text => [ { col => undef, table => undef, text => "2.7.9" }, { col => undef, table => undef, text => "Primary Display Hardware Cursor Registers", }, { col => 0, table => 0, text => "D1OVL_RT_RT_FLIP" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 selects bandSync to be exposed to CP" }, { col => 3, table => 0, text => "1 selects frameSync to be exposed to CP" }, { col => 0, table => 0, text => "D1OVL_RT_PROCEED_ON_EOF_DISA" }, { col => 0, table => 0, text => "BLE" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 enables unfinished bands to pass bandSync on EOF ", }, { col => 3, table => 0, text => "(valid only in basic scheme)" }, { col => 3, table => 0, text => "1 disables this feature" }, { col => 0, table => 0, text => "D1OVL_RT_WITH_HELD_ON_SOF" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 disables proceedOnEOF on next frameSync", }, { col => 3, table => 0, text => "1 disables proceedOnEOF on next SOF" }, { col => 0, table => 0, text => "D1OVL_RT_CLEAR_GOBBLE_GO (W)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This bit clear gobbleGo " }, { col => 3, table => 0, text => "disable another frame submit before next flip (ignored in ", }, { col => 3, table => 0, text => "basic scheme)" }, { col => 0, table => 0, text => "D1OVL_RT_TEAR_PROOF_HEIGHT" }, { col => 1, table => 0, text => "29:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "define the number of scan lines above topscan.", }, { col => undef, table => undef, text => "if display starts reading from there, RT should wait", }, { col => undef, table => undef, text => "select RT flip proceed condition", }, { col => "heading", table => 1, text => "D1OVL_RT_STAT - RW - 32 bits - [GpuF0MMReg:0x6510]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1OVL_RT_FIP_PROCEED_ACK (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The sticky bit clears the FIP_PROCEED FLAG flag when ", }, { col => 3, table => 1, text => "written" }, { col => 0, table => 1, text => "D1OVL_RT_FRAME_SYNC_ACK (W)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The sticky bit clears the RT_FRAME_SYNC flag when ", }, { col => 3, table => 1, text => "written" }, { col => 0, table => 1, text => "D1OVL_RT_OVL_START_ACK (W)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The sticky bit clears the OVL_START FLAG flag when ", }, { col => 3, table => 1, text => "written" }, { col => 0, table => 1, text => "D1OVL_RT_BAND_INVISIBLE (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that overlay scanning in invisble region", }, { col => 0, table => 1, text => "D1OVL_RT_BAND_SYNC (R)" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that overlay bottom scan is less the line ", }, { col => 3, table => 1, text => "counter" }, { col => 0, table => 1, text => "D1OVL_RT_EOF_PRPCEED (R)" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that overlay is ended. Set at eof and ", }, { col => 3, table => 1, text => "reset at overlay start" }, { col => 0, table => 1, text => "D1OVL_RT_FIP_PROCEED (R)" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Sticky debug bit that set when RT_FLIP_PROCEED signal ", }, { col => 3, table => 1, text => "asserted." }, { col => 0, table => 1, text => "D1OVL_RT_FRAME_SYNC (R)" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Sticky debug bit indicating that overlay start set and a new ", }, { col => 3, table => 1, text => "submission occured" }, { col => 0, table => 1, text => "D1OVL_RT_GOBBLE_GO (R)" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit that set on frame_sync and clear at gobbleclr", }, { col => 0, table => 1, text => "D1OVL_RT_NEW_SUBMIT (R)" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating a new submission occurred", }, { col => 0, table => 1, text => "D1OVL_RT_OVL_START (R)" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that line buffer detects start of overlay ", }, { col => 3, table => 1, text => "being accessed" }, { col => 0, table => 1, text => "D1OVL_RT_OVL_ENDED (R)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that line buffer detects that the end of ", }, { col => 3, table => 1, text => "overlay being accessed" }, { col => 0, table => 1, text => "D1OVL_RT_SAFE_ZONE (R)" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that overlay is scaning in safe zone", }, { col => 0, table => 1, text => "D1OVL_RT_SWITCH_REGIONS (R)" }, { col => 1, table => 1, text => 18 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit showing the postion of scan region relative to ", }, { col => 3, table => 1, text => "display" }, { col => 0, table => 1, text => "D1OVL_SKEW_MAX_REACHED (R)" }, { col => 1, table => 1, text => 19 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug bit indicating that line buffer detected maximum ", }, { col => 3, table => 1, text => "skew reached" }, { col => 0, table => 1, text => "D1OVL_LINE_COUNTER (R)" }, { col => 1, table => 1, text => "31:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "debug bit showing display line counter value", }, { col => undef, table => undef, text => "Status Bits" }, { col => "heading", table => 2, text => "D1CUR_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6400]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 203, text => [ { col => 0, table => 0, text => "D1CURSOR_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor enabled.", }, { col => 3, table => 0, text => " 0=disable " }, { col => 3, table => 0, text => " 1=enable " }, { col => 0, table => 0, text => "D1CURSOR_MODE" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor mode." }, { col => 3, table => 0, text => "For 2bpp mode, each line of cursor data is stored in ", }, { col => 3, table => 0, text => "memory as 16 bits of AND data followed by 16 bits XOR ", }, { col => 3, table => 0, text => "data." }, { col => 3, table => 0, text => "For color AND/XOR mode, each pixel is stored sequentially ", }, { col => 3, table => 0, text => "in memory as 32bits each in aRGB8888 format with bit 31 ", }, { col => 3, table => 0, text => "of each DWord being the AND bit." }, { col => 3, table => 0, text => "For the color alpha modes the format is also 32bpp ", }, { col => 3, table => 0, text => "aRGB8888 with all 8 bits of the alpha being used.All HW ", }, { col => 3, table => 0, text => "cursor lines must be 64 pixels wide and all lines must be ", }, { col => 3, table => 0, text => "stored sequentially in memory." }, { col => 3, table => 0, text => " 0=Mono (2bpp) " }, { col => 3, table => 0, text => " 1=Color 24bpp + 1 bit AND (32bpp) " }, { col => 3, table => 0, text => " 2=Color 24bpp + 8 bit alpha (32bpp) premultiplied alpha ", }, { col => 3, table => 0, text => " 3=Color 24bpp + 8 bit alpha (32bpp)unmultiplied alpha ", }, { col => 0, table => 0, text => "D1CURSOR_2X_MAGNIFY" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor 2x2 magnification.", }, { col => 3, table => 0, text => " 0=no 2x2 magnification " }, { col => 3, table => 0, text => " 1=2x2 magnification in horizontal and vertical direction ", }, { col => 0, table => 0, text => "D1CURSOR_FORCE_MC_ON" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When set, if the incoming data is in D1 cursor region, ", }, { col => 3, table => 0, text => "DCP_LB_cursor1_allow_stutter is set. This field in this ", }, { col => undef, table => undef, text => "double bufferred register is not double buffered", }, { col => undef, table => undef, text => "Primary display hardware control", }, { col => "heading", table => 1, text => "D1CUR_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6408]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CURSOR_SURFACE_ADDRESS" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware cursor surface base address in ", }, { col => 3, table => 1, text => "byte. It is 4K byte aligned." }, { col => undef, table => undef, text => "NOTE: Bits 0:11 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary display hardware cursor surface base address.", }, { col => "heading", table => 2, text => "D1CUR_SIZE - RW - 32 bits - [GpuF0MMReg:0x6410]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CURSOR_HEIGHT" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary display hardware cursor height minus 1.", }, { col => 0, table => 2, text => "D1CURSOR_WIDTH" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware cursor width minus 1.", }, { col => undef, table => undef, text => "Primary display hardware size" }, { col => "heading", table => 3, text => "D1CUR_POSITION - RW - 32 bits - [GpuF0MMReg:0x6414]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CURSOR_Y_POSITION" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary display hardware cursor X coordinate at the hot ", }, { col => 3, table => 3, text => "spot relative to the desktop coordinates.", }, { col => 0, table => 3, text => "D1CURSOR_X_POSITION" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary display hardware cursor X coordinate at the hot ", }, { col => undef, table => undef, text => "spot relative to the desktop coordinates.", }, { col => undef, table => undef, text => "Primary display hardware cursor position", }, ], }, { num => 204, text => [ { col => "heading", table => 0, text => "D1CUR_HOT_SPOT - RW - 32 bits - [GpuF0MMReg:0x6418]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CURSOR_HOT_SPOT_Y" }, { col => 1, table => 0, text => "5:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor hot spot X length relative ", }, { col => 3, table => 0, text => "to the top left corner." }, { col => 0, table => 0, text => "D1CURSOR_HOT_SPOT_X" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor hot spot Y length relative ", }, { col => undef, table => undef, text => "to the top left corner." }, { col => undef, table => undef, text => "Primary display hardware cursor hot spot position", }, { col => "heading", table => 1, text => "D1CUR_COLOR1 - RW - 32 bits - [GpuF0MMReg:0x641C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CUR_COLOR1_BLUE" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware cursor blue component of color 1.", }, { col => 0, table => 1, text => "D1CUR_COLOR1_GREEN" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware cursor green component of color ", }, { col => 3, table => 1, text => "1." }, { col => 0, table => 1, text => "D1CUR_COLOR1_RED" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware cursor red component of color 1.", }, { col => undef, table => undef, text => "Primary display hardware cursor color 1.", }, { col => "heading", table => 2, text => "D1CUR_COLOR2 - RW - 32 bits - [GpuF0MMReg:0x6420]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CUR_COLOR2_BLUE" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary display hardware cursor blue component of color 2.", }, { col => 0, table => 2, text => "D1CUR_COLOR2_GREEN" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary display hardware cursor green component of color ", }, { col => 3, table => 2, text => "2." }, { col => 0, table => 2, text => "D1CUR_COLOR2_RED" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware cursor red component of color 2.", }, { col => undef, table => undef, text => "Primary display hardware cursor color 2.", }, { col => undef, table => undef, text => "D1CUR_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6424]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 205, text => [ { col => undef, table => undef, text => "2.7.10" }, { col => undef, table => undef, text => "Primary Display Hardware Icon Registers", }, { col => 0, table => 0, text => "D1CURSOR_UPDATE_PENDING (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor update pending status. It ", }, { col => 3, table => 0, text => "is set to 1 after a host write to cursor double buffer register. ", }, { col => 3, table => 0, text => "It is cleared after double buffering is done. The double ", }, { col => 3, table => 0, text => "buffering occurs when D1CURSOR_UPDATE_PENDING = ", }, { col => 3, table => 0, text => "1 and D1CURSOR_UPDATE_LOCK = 0 and V_UPDATE = ", }, { col => 3, table => 0, text => "1." }, { col => 3, table => 0, text => "If CRTC1 is disabled, the registers will be updated instantly.", }, { col => 3, table => 0, text => "The D1CUR double buffer registers are:" }, { col => 3, table => 0, text => "D1CURSOR_EN" }, { col => 3, table => 0, text => "D1CURSOR_MODE" }, { col => 3, table => 0, text => "D1CURSOR_2X_MAGNIFY" }, { col => 3, table => 0, text => "D1CURSOR_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D1CURSOR_HEIGHT" }, { col => 3, table => 0, text => "D1CURSOR_WIDTH" }, { col => 3, table => 0, text => "D1CURSOR_X_POSITION" }, { col => 3, table => 0, text => "D1CURSOR_Y_POSITION" }, { col => 3, table => 0, text => "D1CURSOR_HOT_SPOT_X" }, { col => 3, table => 0, text => "D1CURSOR_HOT_SPOT_Y" }, { col => 3, table => 0, text => " 0=No update pending " }, { col => 3, table => 0, text => " 1=Update pending " }, { col => 0, table => 0, text => "D1CURSOR_UPDATE_TAKEN (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor update taken status. It is ", }, { col => 3, table => 0, text => "set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 0, text => "V_UPDATE = 0" }, { col => 0, table => 0, text => "D1CURSOR_UPDATE_LOCK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware cursor update lock control.", }, { col => 3, table => 0, text => " 0=Unlocked " }, { col => 3, table => 0, text => " 1=Locked " }, { col => 0, table => 0, text => "D1CURSOR_DISABLE_MULTIPLE_UPD" }, { col => 0, table => 0, text => "ATE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D1CURSOR registers can be updated multiple times in ", }, { col => 3, table => 0, text => "one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D1CURSOR registers can only be updated once in one ", }, { col => 3, table => 0, text => "V_UPDATE period " }, { col => "heading", table => 1, text => "D1ICON_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6440]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1ICON_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware icon enable." }, { col => 3, table => 1, text => " 0=disable " }, { col => 3, table => 1, text => " 1=enable " }, { col => 0, table => 1, text => "D1ICON_2X_MAGNIFY" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware icon 2x2 magnification.", }, { col => 3, table => 1, text => " 0=no 2x2 magnification " }, { col => 3, table => 1, text => " 1=2x2 magnification in horizontal and vertical direction ", }, { col => 0, table => 1, text => "D1ICON_FORCE_MC_ON" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "When set, if the incoming data is in D1 icon region, ", }, { col => 3, table => 1, text => "DCP_LB_icon1_allow_stutter is set. This field in this double ", }, { col => undef, table => undef, text => "bufferred register is not double buffered.", }, { col => undef, table => undef, text => "Primary display hardware icon control.", }, { col => "heading", table => 2, text => "D1ICON_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6448]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 206, text => [ { col => 0, table => 0, text => "D1ICON_SURFACE_ADDRESS" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Primary display hardware icon surface base address in ", }, { col => 3, table => 0, text => "byte. It is 4K byte aligned." }, { col => undef, table => undef, text => "NOTE: Bits 0:11 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Primary display hardware icon surface base address.", }, { col => "heading", table => 1, text => "D1ICON_SIZE - RW - 32 bits - [GpuF0MMReg:0x6450]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1ICON_HEIGHT" }, { col => 1, table => 1, text => "6:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary display hardware icon height minus 1.", }, { col => 0, table => 1, text => "D1ICON_WIDTH" }, { col => 1, table => 1, text => "22:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon width minus 1.", }, { col => undef, table => undef, text => "Primary display hardware icon size.", }, { col => "heading", table => 2, text => "D1ICON_START_POSITION - RW - 32 bits - [GpuF0MMReg:0x6454]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1ICON_Y_POSITION" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary display hardware icon Y start coordinate related to ", }, { col => 3, table => 2, text => "the desktop coordinates." }, { col => 3, table => 2, text => "Note: Icon can not be off the top and off the left edge of the ", }, { col => 3, table => 2, text => "display surface. But can be off the bottom and off the right ", }, { col => 3, table => 2, text => "edge of the display." }, { col => 0, table => 2, text => "D1ICON_X_POSITION" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Primary display hardware icon X start coordinate relative to ", }, { col => 3, table => 2, text => "the desktop coordinates." }, { col => 3, table => 2, text => "Note: Icon can not be off the top and off the left edge of the ", }, { col => 3, table => 2, text => "display surface. But can be off the bottom and off the right ", }, { col => undef, table => undef, text => "edge of the display." }, { col => undef, table => undef, text => "Primary display hardware icon position", }, { col => "heading", table => 3, text => "D1ICON_COLOR1 - RW - 32 bits - [GpuF0MMReg:0x6458]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1ICON_COLOR1_BLUE" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary display hardware icon blue component of color 1.", }, { col => 0, table => 3, text => "D1ICON_COLOR1_GREEN" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Primary display hardware icon green component of color 1.", }, { col => 0, table => 3, text => "D1ICON_COLOR1_RED" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon red component of color 1.", }, { col => undef, table => undef, text => "Primary display hardware icon color 1.", }, { col => "heading", table => 4, text => "D1ICON_COLOR2 - RW - 32 bits - [GpuF0MMReg:0x645C]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1ICON_COLOR2_BLUE" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Primary display hardware icon blue component of color 2.", }, { col => 0, table => 4, text => "D1ICON_COLOR2_GREEN" }, { col => 1, table => 4, text => "15:8" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Primary display hardware icon green component of color 2.", }, { col => 0, table => 4, text => "D1ICON_COLOR2_RED" }, { col => 1, table => 4, text => "23:16" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon red component of color 2.", }, { col => undef, table => undef, text => "Primary display hardware icon color 2.", }, ], }, { num => 207, text => [ { col => undef, table => undef, text => "2.7.11" }, { col => undef, table => undef, text => "Primary Display Multi-VPU Control Registers", }, { col => undef, table => undef, text => "D1ICON_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6460]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1ICON_UPDATE_PENDING (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon update Pending status. It is ", }, { col => undef, table => undef, text => "set to 1 after a host write to icon double buffer register. It is ", }, { col => undef, table => undef, text => "cleared after double buffering is done. The double buffering ", }, { col => undef, table => undef, text => "occurs when D1ICON_UPDATE_PENDING = 1 and ", }, { col => undef, table => undef, text => "D1ICON_UPDATE_LOCK = 0 and V_UPDATE = 1.", }, { col => undef, table => undef, text => "If CRTC1 is disabled, the registers will be updated instantly.", }, { col => undef, table => undef, text => "D1IOCN double buffer registers include :", }, { col => undef, table => undef, text => "D1ICON_ENABLE" }, { col => undef, table => undef, text => "D1ICON_2X_MAGNIFY" }, { col => undef, table => undef, text => "D1ICON_SURFACE_ADDRESS" }, { col => undef, table => undef, text => "D1ICON_HEIGHT" }, { col => undef, table => undef, text => "D1ICON_WIDTH" }, { col => undef, table => undef, text => "D1ICON_Y_POSITION" }, { col => undef, table => undef, text => "D1ICON_X_POSITION" }, { col => undef, table => undef, text => " 0=No update pending " }, { col => undef, table => undef, text => " 1=Update pending " }, { col => undef, table => undef, text => "D1ICON_UPDATE_TAKEN (R)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon update Taken status. It is set ", }, { col => undef, table => undef, text => "to 1 when double buffering occurs and cleared when ", }, { col => undef, table => undef, text => "V_UPDATE = 0" }, { col => undef, table => undef, text => "D1ICON_UPDATE_LOCK" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Primary display hardware icon update lock control.", }, { col => undef, table => undef, text => " 0=Unlocked " }, { col => undef, table => undef, text => " 1=Locked " }, { col => undef, table => undef, text => "D1ICON_DISABLE_MULTIPLE_UPDATE" }, { col => undef, table => undef, text => 24 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=D1ICON registers can be updated multiple times in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => " 1=D1ICON registers can only be updated once in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => "Primary display hardware icon update control", }, { col => "heading", table => 0, text => "D1CRTC_MVP_CONTROL1 - RW - 32 bits - [GpuF0MMReg:0x6038]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MVP_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable MVP feature" }, { col => 0, table => 0, text => "MVP_MIXER_MODE" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "000 - Split mode/super-tile mode; 001 - AFR manual (driver ", }, { col => 3, table => 0, text => "control); 010 - AFR (switching); 011 - AFR manual switch ", }, { col => 3, table => 0, text => "(set inband control character through register); 100 - ", }, { col => 3, table => 0, text => "SuperAA with gamma and degamma enabled; 101 - ", }, { col => 3, table => 0, text => "SuperAA with only gamma enabled" }, { col => 0, table => 0, text => "MVP_MIXER_SLAVE_SEL" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 - in AFR manual (drive control) mode, use master inputs ", }, { col => 3, table => 0, text => "in the next frame; '1' - use the slave input", }, { col => 0, table => 0, text => "MVP_MIXER_SLAVE_SEL_DELAY_UNT" }, { col => 0, table => 0, text => "IL_END_OF_BLANK" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 - MVP_MIXER_SLAVE_SEL takes effect immediately; '1' ", }, { col => 3, table => 0, text => "- MVP_MIXER_SLAVE_SEL does not take effect until end ", }, { col => 3, table => 0, text => "of horizontal or vertical blank region" }, { col => 0, table => 0, text => "MVP_ARBITRATION_MODE_FOR_AFR_" }, { col => 0, table => 0, text => "MANUAL_SWITCH_MODE" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Arbitration scheme used when both master and slave GPU ", }, { col => 3, table => 0, text => "switch AFR flip queue status" }, { col => 3, table => 0, text => "0 = pixel source comes from the GPU which last make the ", }, { col => 3, table => 0, text => "switch" }, { col => 3, table => 0, text => "1 = pixel source changes to the GPU which is not currently ", }, { col => 3, table => 0, text => "displayed" }, { col => 0, table => 0, text => "MVP_RATE_CONTROL" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 - DDR; 1 - SDR" }, ], }, { num => 208, text => [ { col => 0, table => 0, text => "MVP_CHANNEL_CONTROL" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0 - single channel; 1 - dual channel" }, { col => 0, table => 0, text => "MVP_GPU_CHAIN_LOCATION" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The location of the GPU in a chain: 00 - Master GPU, 01 - ", }, { col => 3, table => 0, text => "middle GPU, 10 - head slave GPU (or slave GPU in ", }, { col => 3, table => 0, text => "dual-GPU system" }, { col => 0, table => 0, text => "MVP_DISABLE_MSB_EXPAND" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "How to expand each color component of pixel data from ", }, { col => 3, table => 0, text => "slave GPU from 8 to 10 bits: 0 - dynamic expansion, 1 - pad ", }, { col => 3, table => 0, text => "0s" }, { col => 0, table => 0, text => "MVP_30BPP_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable 30bpp operation" }, { col => 0, table => 0, text => "MVP_TERMINATION_CNTL_A" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls DVP termination resistors" }, { col => 0, table => 0, text => "MVP_TERMINATION_CNTL_B" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Controls DVP termination resistors", }, { col => undef, table => undef, text => "MVP Control 1" }, { col => "heading", table => 1, text => "D1CRTC_MVP_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x603C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MVP_MUX_DE_DVOCNTL0_SEL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - selects DVOCNT2; 1 - selects DVOCNT0", }, { col => 0, table => 1, text => "MVP_MUX_DE_DVOCNTL2_SEL" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - selects DVOCNT2; 1 - selects DVOCNT0", }, { col => 0, table => 1, text => "MVP_MUXA_CLK_SEL" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - selects CLKA; 1 - selects CLKB" }, { col => 0, table => 1, text => "MVP_MUXB_CLK_SEL" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - selects CLKA; 1 - selects CLKB" }, { col => 0, table => 1, text => "MVP_DVOCNTL_MUX" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - DVOCNTL[2:0] = DVO_DE, DVO_HSYNC, " }, { col => 3, table => 1, text => "DVO_VSYNC; 1 - DVOCNTL[2:0] = DVO_DE, " }, { col => 3, table => 1, text => "MVP_DVOCLK_C, DVO_DE" }, { col => 0, table => 1, text => "MVP_FLOW_CONTROL_OUT_EN" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable flow_control_out" }, { col => 0, table => 1, text => "MVP_SWAP_LOCK_OUT_EN" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 - Swap_lock_out is not enabled; 1 - enable swap_lock out ", }, { col => 3, table => 1, text => "in GPIO" }, { col => 0, table => 1, text => "MVP_SWAP_AB_IN_DC_DDR" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "1 - swap in A & B data in dual channel DDR mode. This is ", }, { col => undef, table => undef, text => "the default" }, { col => undef, table => undef, text => "MVP Control 2" }, { col => "heading", table => 2, text => "D1CRTC_MVP_FIFO_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6040]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MVP_STOP_SLAVE_WM" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x8" }, { col => 3, table => 2, text => "At the period after the start of DE from slave GPU, if MVP ", }, { col => 3, table => 2, text => "FIFO level exceeds this watermark, flow control is asserted", }, { col => 0, table => 2, text => "MVP_PAUSE_SLAVE_WM" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x8" }, { col => 3, table => 2, text => "In the middle of receiving a raster line from the slave GPU, ", }, { col => 3, table => 2, text => "if MVP FIFO level falls below this watermark, flow control ", }, { col => 3, table => 2, text => "signal is asserted for MVP_PAUSE_SLAVE_CNT cycles", }, { col => 0, table => 2, text => "MVP_PAUSE_SLAVE_CNT" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x4" }, { col => 3, table => 2, text => "In the middle of receiving a raster line from the slave GPU, ", }, { col => 3, table => 2, text => "if MVP FIFO level falls below this watermark, flow control ", }, { col => undef, table => undef, text => "signal is asserted for MVP_PAUSE_SLAVE_CNT cycles", }, { col => undef, table => undef, text => "MVP FIFO Control" }, { col => "heading", table => 3, text => "D1CRTC_MVP_FIFO_STATUS - RW - 32 bits - [GpuF0MMReg:0x6044]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "MVP_FIFO_LEVEL (R)" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "MVP FIFO level, in # of pixels" }, { col => 0, table => 3, text => "MVP_FIFO_OVERFLOW (R)" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "MVP FIFO overflows" }, { col => 0, table => 3, text => "MVP_FIFO_OVERFLOW_OCCURRED " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => 12 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Sticky bit - MVP FIFO overflow has occurred", }, { col => 0, table => 3, text => "MVP_FIFO_OVERFLOW_ACK" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Resets MVP_FIFO_OVERFLOW_OCCURRED" }, { col => 0, table => 3, text => "MVP_FIFO_UNDERFLOW (R)" }, { col => 1, table => 3, text => 20 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "MVP FIFO underflows" }, { col => 0, table => 3, text => "MVP_FIFO_UNDERFLOW_OCCURRED " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => 24 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Sticky bit - MVP FIFO underflows occurred", }, ], }, { num => 209, text => [ { col => 0, table => 0, text => "MVP_FIFO_UNDERFLOW_ACK" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Resets MVP_FIFO_UNDERFLOW_OCCURRED" }, { col => 0, table => 0, text => "MVP_FIFO_ERROR_MASK" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable interrupt on mvp fifo overflow or ", }, { col => 3, table => 0, text => "underflow event" }, { col => 0, table => 0, text => "MVP_FIFO_ERROR_INT_STATUS (R)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Fifo error status flag (masked OR of fifo over/uderflow)", }, { col => undef, table => undef, text => "MVP FIFO Status" }, { col => "heading", table => 1, text => "D1CRTC_MVP_SLAVE_STATUS - RW - 32 bits - [GpuF0MMReg:0x6048]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MVP_SLAVE_PIXELS_PER_LINE_RCVE" }, { col => 0, table => 1, text => "D (R)" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The number of active pixels per line received from the slave ", }, { col => 3, table => 1, text => "GPU" }, { col => 0, table => 1, text => "MVP_SLAVE_LINES_PER_FRAME_RCV" }, { col => 0, table => 1, text => "ED (R)" }, { col => 1, table => 1, text => "28:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "The number of active lines per frame received from the ", }, { col => undef, table => undef, text => "slave GPU" }, { col => undef, table => undef, text => "MVP Slave Status" }, { col => "heading", table => 2, text => "D1CRTC_MVP_INBAND_CNTL_CAP - RW - 32 bits - [GpuF0MMReg:0x604C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MVP_IGNOR_INBAND_CNTL" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Master GPU ignors the inband control signal", }, { col => 0, table => 2, text => "MVP_PASSING_INBAND_CNTL_EN" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Slave GPU passes upstream slave GPU to downstream ", }, { col => 3, table => 2, text => "slave GPU/master GPU" }, { col => 0, table => 2, text => "MVP_INBAND_CNTL_CHAR_CAP (R)" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Inband control signal received from slave GPU", }, { col => undef, table => undef, text => "MVP Capture Inband Control" }, { col => "heading", table => 3, text => "D1CRTC_MVP_INBAND_CNTL_INSERT - RW - 32 bits - [GpuF0MMReg:0x6050]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_MVP_INBAND_OUT_MODE" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "00 - disable inband insertion; 01 - used for debug only: ", }, { col => 3, table => 3, text => "insert register MVP_INBAND_CNTL_CHAR_INSERT; 10 - ", }, { col => 3, table => 3, text => "normal mode: insert the character generated by MVP_mixer", }, { col => 0, table => 3, text => "D1CRTC_MVP_INBAND_CNTL_CHAR_I" }, { col => 0, table => 3, text => "NSERT" }, { col => 1, table => 3, text => "31:8" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Used for debug only: 24-bit control character for insertion", }, { col => undef, table => undef, text => "MVP Insert Inband Control" }, { col => "heading", table => 4, text => "D1CRTC_MVP_INBAND_CNTL_INSERT_TIMER - RW - 32 bits - [GpuF0MMReg:0x6054]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1CRTC_MVP_INBAND_CNTL_CHAR_I" }, { col => 0, table => 4, text => "NSERT_TIMER" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x8" }, { col => 3, table => 4, text => "The number of clock cycles the character insertion trigger ", }, { col => 3, table => 4, text => "from the line buffer needs to be ahead of end of lines for ", }, { col => undef, table => undef, text => "CRTC to insert the in-band control character", }, { col => undef, table => undef, text => "MVP Insert Inband Control Timer" }, ], }, { num => 210, text => [ { col => "heading", table => 0, text => "D1CRTC_MVP_BLACK_KEYER - RW - 32 bits - [GpuF0MMReg:0x6058]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "MVP_BLACK_KEYER_R" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Black keyer value, for red pixel" }, { col => 0, table => 0, text => "MVP_BLACK_KEYER_G" }, { col => 1, table => 0, text => "19:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Black keyer value, for green pixel" }, { col => 0, table => 0, text => "MVP_BLACK_KEYER_B" }, { col => 1, table => 0, text => "29:20" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Black keyer value, for blue pixel", }, { col => undef, table => undef, text => "MVP Black keyer for smoothing out pixels after black keyer in LB in SFR mode", }, { col => "heading", table => 1, text => "D1CRTC_MVP_STATUS - RW - 32 bits - [GpuF0MMReg:0x605C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_FLIP_NOW_OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether flip_now has occurred. A sticky bit.", }, { col => 3, table => 1, text => "0 = has not occurred" }, { col => 3, table => 1, text => "1 = has occurred" }, { col => 0, table => 1, text => "D1CRTC_AFR_HSYNC_SWITCH_DONE" }, { col => 0, table => 1, text => "_OCCURRED (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether afr_hsync_switch_done has occurred. A ", }, { col => 3, table => 1, text => "sticky bit." }, { col => 3, table => 1, text => "0 = has not occurred" }, { col => 3, table => 1, text => "1 = has occurred" }, { col => 0, table => 1, text => "D1CRTC_FLIP_NOW_CLEAR (W)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Clears the sticky bit D1CRTC_FLIP_NOW_OCCURRED ", }, { col => 3, table => 1, text => "when written with '1'" }, { col => 0, table => 1, text => "D1CRTC_AFR_HSYNC_SWITCH_DONE" }, { col => 0, table => 1, text => "_CLEAR (W)" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Clears the sticky bit " }, { col => 3, table => 1, text => "D1CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED " }, { col => undef, table => undef, text => "when written with '1'" }, { col => undef, table => undef, text => "Reports status for MVP flipping in CRTC1", }, { col => "heading", table => 2, text => "D2CRTC_MVP_INBAND_CNTL_INSERT - RW - 32 bits - [GpuF0MMReg:0x6838]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_MVP_INBAND_OUT_MODE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "00 - disable inband insertion; 01 - used for debug only: ", }, { col => 3, table => 2, text => "insert register MVP_INBAND_CNTL_CHAR_INSERT; 10 - ", }, { col => 3, table => 2, text => "normal mode: insert the character generated by MVP_mixer", }, { col => 0, table => 2, text => "D2CRTC_MVP_INBAND_CNTL_CHAR_I" }, { col => 0, table => 2, text => "NSERT" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Used for debug only: 24-bit control character for insertion", }, { col => undef, table => undef, text => "MVP Insert Inband Control for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_MVP_INBAND_CNTL_INSERT_TIMER - RW - 32 bits - [GpuF0MMReg:0x683C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_MVP_INBAND_CNTL_CHAR_I" }, { col => 0, table => 3, text => "NSERT_TIMER" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x8" }, { col => 3, table => 3, text => "The number of clock cycles the character insertion trigger ", }, { col => 3, table => 3, text => "from the line buffer needs to be ahead of end of lines for ", }, { col => undef, table => undef, text => "CRTC to insert the in-band control character", }, { col => undef, table => undef, text => "MVP Insert Inband Control Timer for CRTC2", }, { col => "heading", table => 4, text => "D1CRTC_MVP_CRC_CNTL - RW - 32 bits - [GpuF0MMReg:0x6840]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "MVP_CRC_BLUE_MASK" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0xff" }, { col => 3, table => 4, text => "mask bit for blue component" }, ], }, { num => 211, text => [ { col => 0, table => 0, text => "MVP_CRC_GREEN_MASK" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0xff" }, { col => 3, table => 0, text => "mask bit for green component" }, { col => 0, table => 0, text => "MVP_CRC_RED_MASK" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0xff" }, { col => 3, table => 0, text => "mask bit for red component" }, { col => 0, table => 0, text => "MVP_CRC_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "0 - CRC disabled; 1 - CRC enabled", }, { col => undef, table => undef, text => "CRC control register for MVP" }, { col => "heading", table => 1, text => "D1CRTC_MVP_CRC_RESULT - RW - 32 bits - [GpuF0MMReg:0x6844]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MVP_CRC_BLUE_RESULT (R)" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "CRC result for each frame (DE region only) - Blue ", }, { col => 3, table => 1, text => "component" }, { col => 0, table => 1, text => "MVP_CRC_GREEN_RESULT (R)" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "CRC result for each frame (DE region only) - Green ", }, { col => 3, table => 1, text => "component" }, { col => 0, table => 1, text => "MVP_CRC_RED_RESULT (R)" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "CRC result for each frame (DE region only) - Red ", }, { col => undef, table => undef, text => "component" }, { col => undef, table => undef, text => "CRC result for each frame" }, { col => "heading", table => 2, text => "D1CRTC_MVP_CRC2_CNTL - RW - 32 bits - [GpuF0MMReg:0x6848]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MVP_CRC2_BLUE_MASK" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "mask bit for blue component" }, { col => 0, table => 2, text => "MVP_CRC2_GREEN_MASK" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "mask bit for green component" }, { col => 0, table => 2, text => "MVP_CRC2_RED_MASK" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "mask bit for red component" }, { col => 0, table => 2, text => "MVP_CRC2_EN" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "0 - CRC2 disabled; 1 - CRC2 enabled", }, { col => undef, table => undef, text => "CRC2 control register for MVP" }, { col => "heading", table => 3, text => "D1CRTC_MVP_CRC2_RESULT - RW - 32 bits - [GpuF0MMReg:0x684C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "MVP_CRC2_BLUE_RESULT (R)" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "CRC2 result for each frame (DE region only) - Blue ", }, { col => 3, table => 3, text => "component" }, { col => 0, table => 3, text => "MVP_CRC2_GREEN_RESULT (R)" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "CRC2 result for each frame (DE region only) - Green ", }, { col => 3, table => 3, text => "component" }, { col => 0, table => 3, text => "MVP_CRC2_RED_RESULT (R)" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "CRC2 result for each frame (DE region only) - Red ", }, { col => undef, table => undef, text => "component" }, { col => undef, table => undef, text => "CRC2 result for each frame" }, { col => undef, table => undef, text => "D1CRTC_MVP_CONTROL3 - RW - 32 bits - [GpuF0MMReg:0x6850]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "MVP_RESET_IN_BETWEEN_FRAMES" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "1 - reset pointers, state machines of the MVP receiving ", }, { col => undef, table => undef, text => "logic between frames" }, { col => undef, table => undef, text => "MVP_DDR_SC_AB_SEL" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "0 - select bundle A in DDR single channel mode, 1 - select ", }, { col => undef, table => undef, text => "bundle B" }, { col => undef, table => undef, text => "MVP_DDR_SC_B_START_MODE" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "0 - Assuming the read & write clocks for meso-FIFO B is ", }, { col => undef, table => undef, text => "meso-chronous; 1 - assuming they are synchronous", }, { col => undef, table => undef, text => "MVP_FLOW_CONTROL_OUT_FORCE_" }, { col => undef, table => undef, text => "ONE" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "1 - force flow_control_out to 1" }, ], }, { num => 212, text => [ { col => 0, table => 0, text => "MVP_FLOW_CONTROL_OUT_FORCE_" }, { col => 0, table => 0, text => "ZERO" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "1 - force flow_control_out to 0" }, { col => 0, table => 0, text => "MVP_FLOW_CONTROL_CASCADE_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "1 - cascade flow control in multi-GPU" }, { col => 0, table => 0, text => "MVP_SWAP_48BIT_EN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "1 - swap the least & most signficant 24 bits of the data as ", }, { col => 3, table => 0, text => "they read out of the FIFO" }, { col => 0, table => 0, text => "MVP_FLOW_CONTROL_IN_CAP (R)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "capture flow_control_in, used for diagnostics", }, { col => undef, table => undef, text => "MVP Control Register 3" }, { col => "heading", table => 1, text => "D1CRTC_MVP_RECEIVE_CNT_CNTL1 - RW - 32 bits - [GpuF0MMReg:0x6854]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "MVP_SLAVE_PIXEL_ERROR_CNT (R)" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Count # of pixels in a line that is wrong, reset by active edge ", }, { col => 3, table => 1, text => "of hsync" }, { col => 0, table => 1, text => "MVP_SLAVE_LINE_ERROR_CNT (R)" }, { col => 1, table => 1, text => "28:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Count # of lines in a frame that is wrong, reset by frame ", }, { col => 3, table => 1, text => "start" }, { col => 0, table => 1, text => "MVP_SLAVE_DATA_CHK_EN" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Enable line & pixel counter, should be enabled a couple of ", }, { col => undef, table => undef, text => "frames after master is enabled" }, { col => undef, table => undef, text => "MVP Receive Counter Control 1" }, { col => "heading", table => 2, text => "D1CRTC_MVP_RECEIVE_CNT_CNTL2 - RW - 32 bits - [GpuF0MMReg:0x6858]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "MVP_SLAVE_FRAME_ERROR_CNT (R)" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Count # of frames that is wrong" }, { col => 0, table => 2, text => "MVP_SLAVE_FRAME_ERROR_CNT_RE" }, { col => 0, table => 2, text => "SET" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Reset MVP_SLAVE_FRAME_ERROR_CNT" }, { col => undef, table => undef, text => "MVP Receiver Counter Control 2" }, { col => "heading", table => 3, text => "D1_MVP_AFR_FLIP_MODE - RW - 32 bits - [GpuF0MMReg:0x6514]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1_MVP_AFR_FLIP_MODE" }, { col => 1, table => 3, text => "1:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "10 - real flip; 11 - dummy flip" }, { col => undef, table => undef, text => "S/W writes to this register in AFR mode for display 1 page flip", }, { col => "heading", table => 4, text => "D1_MVP_AFR_FLIP_FIFO_CNTL - RW - 32 bits - [GpuF0MMReg:0x6518]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D1_MVP_AFR_FLIP_FIFO_NUM_ENTRI" }, { col => 0, table => 4, text => "ES (R)" }, { col => 1, table => 4, text => "3:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "number of valid entries in the AFR flip FIFO", }, { col => 0, table => 4, text => "D1_MVP_AFR_FLIP_FIFO_RESET" }, { col => 1, table => 4, text => 4 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "reset the AFR flip FIFO" }, { col => 0, table => 4, text => "D1_MVP_AFR_FLIP_FIFO_RESET_FLA" }, { col => 0, table => 4, text => "G (R)" }, { col => 1, table => 4, text => 8 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "sticky bit of the AFR flip fifo reset status", }, { col => 0, table => 4, text => "D1_MVP_AFR_FLIP_FIFO_RESET_ACK" }, { col => 1, table => 4, text => 12 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "clear the DC_LB_MVP_AFR_FLIP_RESET_FLAG register ", }, { col => undef, table => undef, text => "bit" }, { col => undef, table => undef, text => "This register controls AFR Flip FIFO in display 1", }, ], }, { num => 213, text => [ { col => undef, table => undef, text => "2.7.12" }, { col => undef, table => undef, text => "Secondary Display Graphics Control Registers", }, { col => "heading", table => 0, text => "D1_MVP_FLIP_LINE_NUM_INSERT - RW - 32 bits - [GpuF0MMReg:0x651C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1_MVP_FLIP_LINE_NUM_INSERT_MO" }, { col => 0, table => 0, text => "DE" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "00 - no insertion, 0 is appended; 01 - debug: insert ", }, { col => 3, table => 0, text => "D1_MVP_FLIP_LINE_NUM_INSERT register value; 10 - ", }, { col => 3, table => 0, text => "normal Hsync mode, insert the sum of LB line number + ", }, { col => 3, table => 0, text => "DC_LB_MVP_FLIP_LINE_NUM_OFFSET" }, { col => 0, table => 0, text => "D1_MVP_FLIP_LINE_NUM_INSERT" }, { col => 1, table => 0, text => "21:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "used for debug purpose, this is what will be the line number ", }, { col => 3, table => 0, text => "carried to downstream GPUs if " }, { col => 3, table => 0, text => "D1_MVP_FLIP_LINE_NUM_INSERT_EN is set" }, { col => 0, table => 0, text => "D1_MVP_FLIP_LINE_NUM_OFFSET" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "used in normal HSYNC flipping operation. this is the ", }, { col => 3, table => 0, text => "number added to the current LB (desktop) line number for ", }, { col => 3, table => 0, text => "carrying to the downstream GPUs" }, { col => 0, table => 0, text => "D1_MVP_FLIP_AUTO_ENABLE" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Enabling automatic AFR/SFR flipping for display 1", }, { col => undef, table => undef, text => "This register controls line number insertion for the Hsync flipping mode in display 1", }, { col => "heading", table => 1, text => "D2GRPH_ENABLE - RW - 32 bits - [GpuF0MMReg:0x6900]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Secondary graphic enabled." }, { col => 3, table => 1, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Secondary graphic enabled." }, { col => "heading", table => 2, text => "D2GRPH_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6904]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2GRPH_DEPTH" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphic pixel depth." }, { col => 3, table => 2, text => " 0=8bpp " }, { col => 3, table => 2, text => " 1=16bpp " }, { col => 3, table => 2, text => " 2=32bpp " }, { col => 3, table => 2, text => " 3=64bpp " }, { col => 0, table => 2, text => "D2GRPH_Z" }, { col => 1, table => 2, text => "5:4" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Z[1:0] value for tiling" }, ], }, { num => 214, text => [ { col => 0, table => 0, text => "D2GRPH_FORMAT" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphic pixel format. It is used together with ", }, { col => 3, table => 0, text => "D1GRPH_DEPTH to define the graphic pixel format.", }, { col => 3, table => 0, text => "If (D1GRPH_DEPTH = 0x0)(8 bpp)" }, { col => 3, table => 0, text => " 0x0 - indexed" }, { col => 3, table => 0, text => " others - reserved" }, { col => 3, table => 0, text => "else if (D1GRPH_DEPTH = 0x1)(16 bpp)" }, { col => 3, table => 0, text => " 0x0 - ARGB 1555" }, { col => 3, table => 0, text => " 0x1 - RGB 565" }, { col => 3, table => 0, text => " 0x2 - ARGB 4444" }, { col => 3, table => 0, text => " 0x3 - Alpha index 88" }, { col => 3, table => 0, text => " 0x4 - monochrome 16" }, { col => 3, table => 0, text => " 0x5 - BGRA 5551" }, { col => 3, table => 0, text => " others - reserved" }, { col => 3, table => 0, text => "else if (D1GRPH_DEPTH = 0x2)(32 bpp)" }, { col => 3, table => 0, text => " 0x0 - ARGB 8888" }, { col => 3, table => 0, text => " 0x1 - ARGB 2101010" }, { col => 3, table => 0, text => " 0x2 - 32bpp digital output" }, { col => 3, table => 0, text => " 0x3 - 8-bit ARGB 2101010" }, { col => 3, table => 0, text => " 0x4 - BGRA 1010102" }, { col => 3, table => 0, text => " 0x5 - 8-bit BGRA 1010102" }, { col => 3, table => 0, text => " 0x6 - RGB 111110" }, { col => 3, table => 0, text => " 0x7 - BGR 101111" }, { col => 3, table => 0, text => " others - reserved" }, { col => 3, table => 0, text => "else if (D1GRPH_DEPTH = 0x3)(64 bpp)" }, { col => 3, table => 0, text => " 0x0 - ARGB 16161616" }, { col => 3, table => 0, text => " 0x1 - 64bpp digital output ARGB[13:2]" }, { col => 3, table => 0, text => " 0x2 - 64bpp digital output RGB[15:0]" }, { col => 3, table => 0, text => " 0x3 - 64bpp digital output ARGB[11:0]" }, { col => 3, table => 0, text => " 0x4 - 64bpp digital output BGR[15:0]" }, { col => 3, table => 0, text => " others - reserved" }, { col => 0, table => 0, text => "D2GRPH_TILE_COMPACT_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables multichip tile compaction" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "D2GRPH_ADDRESS_TRANSLATION_E" }, { col => 0, table => 0, text => "NABLE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables display 2 address translation" }, { col => 3, table => 0, text => " 0=0=physical memory " }, { col => 3, table => 0, text => " 1=1=virtual memory " }, { col => 0, table => 0, text => "D2GRPH_PRIVILEGED_ACCESS_ENAB" }, { col => 0, table => 0, text => "LE" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables display 2 privileged page access", }, { col => 3, table => 0, text => " 0=0=no priveledged access " }, { col => 3, table => 0, text => " 1=1=priveledged access " }, { col => 0, table => 0, text => "D2GRPH_ARRAY_MODE" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Defines the tiling mode" }, { col => 3, table => 0, text => " 0=ARRAY_LINEAR_GENERAL: Unaligned linear array ", }, { col => 3, table => 0, text => " 1=ARRAY_LINEAR_ALIGNED: Aligned linear array ", }, { col => 3, table => 0, text => " 2=ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles ", }, { col => 3, table => 0, text => " 3=ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles ", }, { col => 3, table => 0, text => " 4=ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles ", }, { col => 3, table => 0, text => " 5=ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high ", }, { col => 3, table => 0, text => " 6=ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high ", }, { col => 3, table => 0, text => " 7=ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles ", }, { col => 3, table => 0, text => " 8=ARRAY_2B_TILED_THIN1: uses row bank swapping ", }, { col => 3, table => 0, text => " 9=ARRAY_2B_TILED_THIN2: uses row bank swapping ", }, { col => 3, table => 0, text => " 10=ARRAY_2B_TILED_THIN4: uses row bank swapping ", }, { col => 3, table => 0, text => " 11=ARRAY_2B_TILED_THICK: uses row bank swapping ", }, { col => 3, table => 0, text => " 12=ARRAY_3D_TILED_THIN1: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 13=ARRAY_3D_TILED_THICK: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 14=ARRAY_3B_TILED_THIN1: Slices are pipe rotated ", }, { col => 3, table => 0, text => " 15=ARRAY_3B_TILED_THICK: Slices are pipe rotated ", }, ], }, { num => 215, text => [ { col => 0, table => 0, text => "D2GRPH_16BIT_ALPHA_MODE" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This field is only used if 64 bpp graphics bit depth and ", }, { col => 3, table => 0, text => "graphics/overlay blend using per-pixel alpha from graphics ", }, { col => 3, table => 0, text => "channel. It is used for processing 16 bit alpha. The fixed ", }, { col => 3, table => 0, text => "point graphics alpha value in the frame buffer is always ", }, { col => 3, table => 0, text => "clamped to 0.0 - 1.0 data range." }, { col => 3, table => 0, text => " 0x0 - Floating point alpha (1 sign bit, 5 bit exponent, 10 bit ", }, { col => 3, table => 0, text => "mantissa)" }, { col => 3, table => 0, text => " 0x1 - Fixed point alpha with normalization from 256/256 to ", }, { col => 3, table => 0, text => "255/255 to represent 1.0" }, { col => 3, table => 0, text => " 0x2 - Fixed point alpha with no normalization", }, { col => 3, table => 0, text => " 0x3 - Fixed point alpha using lower 8 bits of frame buffer ", }, { col => 3, table => 0, text => "value, no normalization" }, { col => 0, table => 0, text => "D2GRPH_16BIT_FIXED_ALPHA_RANG" }, { col => 0, table => 0, text => "E" }, { col => 1, table => 0, text => "30:28" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This register field is only used if 64 bpp graphics bit depth ", }, { col => 3, table => 0, text => "and D2GRPH_16BIT_ALPHA_MODE = 01 or 10. Also only ", }, { col => 3, table => 0, text => "used if graphics/overlay blend using per-pixel alpha from ", }, { col => 3, table => 0, text => "graphics channel. Final alpha blend value is rounded to 8 ", }, { col => 3, table => 0, text => "bits after optional normalization step (see ", }, { col => 3, table => 0, text => "D2GRPH_16BIT_ALPHA_MODE)." }, { col => 3, table => 0, text => " 0x0 - Use bits 15:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x1 - Use bits 14:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x2 - Use bits 13:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x3 - Use bits 12:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x4 - Use bits 11:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x5 - Use bits 10:0 of input alpha value for blend alpha", }, { col => 3, table => 0, text => " 0x6 - Use bits 9:0 of input alpha value for blend alpha", }, { col => undef, table => undef, text => " 0x7 - Use bits 8:0 of input alpha value for blend alpha", }, { col => undef, table => undef, text => "Secondary graphic pixel depth and format.", }, { col => "heading", table => 1, text => "D2GRPH_LUT_SEL - RW - 32 bits - [GpuF0MMReg:0x6908]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_LUT_SEL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphic LUT selection." }, { col => 3, table => 1, text => " 0=select LUTA " }, { col => 3, table => 1, text => " 1=select LUTB " }, { col => 0, table => 1, text => "D2GRPH_LUT_10BIT_BYPASS_EN" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable bypass secondary graphic LUT for 2101010 format", }, { col => 3, table => 1, text => " 0=Use LUT " }, { col => 3, table => 1, text => " 1=Bypass LUT when in 2101010 format. Ignored for other ", }, { col => 3, table => 1, text => "formats " }, { col => 0, table => 1, text => "D2GRPH_LUT_10BIT_BYPASS_DBL_B" }, { col => 0, table => 1, text => "UF_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable double buffer D2GRPH_LUT_10BIT_BYPASS_EN", }, { col => 3, table => 1, text => " 0=D1GRPH_LUT_10BIT_BYPASS_EN take effect right ", }, { col => 3, table => 1, text => "away " }, { col => 3, table => 1, text => " 1=D1GRPH_LUT_10BIT_BYPASS_EN are double ", }, { col => undef, table => undef, text => "buffered " }, { col => undef, table => undef, text => "Secondary graphic LUT selection.", }, { col => "heading", table => 2, text => "D2GRPH_SWAP_CNTL - RW - 32 bits - [GpuF0MMReg:0x690C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 216, text => [ { col => 0, table => 0, text => "D2GRPH_ENDIAN_SWAP" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "MC endian swap select" }, { col => 3, table => 0, text => " 0=0=none " }, { col => 3, table => 0, text => " 1=1=8in16(0xaabb=>0xbbaa) " }, { col => 3, table => 0, text => " 2=2=8in32(0xaabbccdd=>0xddccbbaa) " }, { col => 3, table => 0, text => " 3=3=8in64(0xaabbccddeeff0011=>0x1100ffeeddccbbaa) ", }, { col => 0, table => 0, text => "D2GRPH_RED_CROSSBAR" }, { col => 1, table => 0, text => "5:4" }, { col => 2, table => 0, text => "0x0Red crossbar select" }, { col => 3, table => 0, text => " 0=0=select from R " }, { col => 3, table => 0, text => " 1=1=select from G " }, { col => 3, table => 0, text => " 2=2=select from B " }, { col => 3, table => 0, text => " 3=3=select from A " }, { col => 0, table => 0, text => "D2GRPH_GREEN_CROSSBAR" }, { col => 1, table => 0, text => "7:6" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Green crossbar select" }, { col => 3, table => 0, text => " 0=0=select from G " }, { col => 3, table => 0, text => " 1=1=select from B " }, { col => 3, table => 0, text => " 2=2=select from A " }, { col => 3, table => 0, text => " 3=3=select from R " }, { col => 0, table => 0, text => "D2GRPH_BLUE_CROSSBAR" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Blue crossbar select" }, { col => 3, table => 0, text => " 0=0=select from B " }, { col => 3, table => 0, text => " 1=1=select from A " }, { col => 3, table => 0, text => " 2=2=select from R " }, { col => 3, table => 0, text => " 3=3=select from G " }, { col => 0, table => 0, text => "D2GRPH_ALPHA_CROSSBAR" }, { col => 1, table => 0, text => "11:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Alpha crossbar select" }, { col => 3, table => 0, text => " 0=0=select from A " }, { col => 3, table => 0, text => " 1=1=select from R " }, { col => 3, table => 0, text => " 2=2=select from G " }, { col => undef, table => undef, text => " 3=3=select from B " }, { col => undef, table => undef, text => "Endian swap and component reorder control", }, { col => "heading", table => 1, text => "D2GRPH_PRIMARY_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6910]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_PRIMARY_DFQ_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Primary surface address DFQ enable" }, { col => 3, table => 1, text => " 0=0 = one deep queue mode " }, { col => 3, table => 1, text => " 1=1 = DFQ mode " }, { col => 0, table => 1, text => "D2GRPH_PRIMARY_SURFACE_ADDRE" }, { col => 0, table => 1, text => "SS" }, { col => 1, table => 1, text => "31:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary surface address for secondary graphics in byte. ", }, { col => undef, table => undef, text => "It is 256 byte aligned." }, { col => undef, table => undef, text => "Secondary surface address for secondary graphics in byte.", }, { col => "heading", table => 2, text => "D2GRPH_SECONDARY_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6918]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2GRPH_SECONDARY_DFQ_ENABLE" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary surface address DFQ enable" }, { col => 3, table => 2, text => " 0=0 = one deep queue mode " }, { col => 3, table => 2, text => " 1=1 = DFQ mode " }, { col => 0, table => 2, text => "D2GRPH_SECONDARY_SURFACE_AD" }, { col => 0, table => 2, text => "DRESS" }, { col => 1, table => 2, text => "31:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary surface address for secondary graphics in byte. ", }, { col => undef, table => undef, text => "It is 256 byte aligned." }, { col => undef, table => undef, text => "Secondary surface address for secondary graphics in byte.", }, { col => "heading", table => 3, text => "D2GRPH_PITCH - RW - 32 bits - [GpuF0MMReg:0x6920]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 217, text => [ { col => 0, table => 0, text => "D2GRPH_PITCH" }, { col => 1, table => 0, text => "13:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphic surface pitch in pixels. For ", }, { col => 3, table => 0, text => "Micro-tiled/Macro-tiled surface, it must be multiple of 64 ", }, { col => 3, table => 0, text => "pixeld in 8bpp mode. For Micro-linear/Macro-tiled surface, it ", }, { col => 3, table => 0, text => "must be multiple of 256 pixeld in 8bpp mode, multiple of 128 ", }, { col => 3, table => 0, text => "pixels in 16bpp mode and multiple of 64 pixels in 32bpp ", }, { col => 3, table => 0, text => "mode. For Micro-linear/Macro-linear surface, it must be ", }, { col => 3, table => 0, text => "multiple of 64 pixels in 8bpp mode. For other modes, it must ", }, { col => 3, table => 0, text => "be multiple of 32." }, { col => undef, table => undef, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary graphic surface pitch in pixels.", }, { col => "heading", table => 1, text => "D2GRPH_SURFACE_OFFSET_X - RW - 32 bits - [GpuF0MMReg:0x6924]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_SURFACE_OFFSET_X" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphic X surface offset. It is 256 pixels aligned.", }, { col => undef, table => undef, text => "NOTE: Bits 0:7 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary graphic X surface offset.", }, { col => "heading", table => 2, text => "D2GRPH_SURFACE_OFFSET_Y - RW - 32 bits - [GpuF0MMReg:0x6928]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2GRPH_SURFACE_OFFSET_Y" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphic Y surface offset. It must be even value", }, { col => undef, table => undef, text => "NOTE: Bit 0 of this field is hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary graphic Y surface offset.", }, { col => "heading", table => 3, text => "D2GRPH_X_START - RW - 32 bits - [GpuF0MMReg:0x692C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2GRPH_X_START" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary graphic X start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Secondary graphic X start coordinate relative to the desktop coordinates.", }, { col => "heading", table => 4, text => "D2GRPH_Y_START - RW - 32 bits - [GpuF0MMReg:0x6930]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2GRPH_Y_START" }, { col => 1, table => 4, text => "12:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Secondary graphic Y start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Secondary graphic Y start coordinate relative to the desktop coordinates.", }, ], }, { num => 218, text => [ { col => "heading", table => 0, text => "D2GRPH_X_END - RW - 32 bits - [GpuF0MMReg:0x6934]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2GRPH_X_END" }, { col => 1, table => 0, text => "13:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphic X end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => undef, table => undef, text => "Secondary graphic X end coordinate relative to the desktop coordinates.", }, { col => "heading", table => 1, text => "D2GRPH_Y_END - RW - 32 bits - [GpuF0MMReg:0x6938]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_Y_END" }, { col => 1, table => 1, text => "13:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphic Y end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => undef, table => undef, text => "Secondary graphic Y end coordinate relative to the desktop coordinates.", }, { col => "heading", table => 2, text => "D2GRPH_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6944]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2GRPH_MODE_UPDATE_PENDING " }, { col => 0, table => 2, text => "(R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphic mode register update pending control. It ", }, { col => 3, table => 2, text => "is set to 1 after a host write to graphics mode register. It is ", }, { col => 3, table => 2, text => "cleared after double buffering is done." }, { col => 3, table => 2, text => "This signal is only visible through register.", }, { col => 3, table => 2, text => "The graphics surface register includes:" }, { col => 3, table => 2, text => "D2GRPH_DEPTH" }, { col => 3, table => 2, text => "D2GRPH_FORMAT" }, { col => 3, table => 2, text => "D2GRPH_SWAP_RB" }, { col => 3, table => 2, text => "D2GRPH_LUT_SEL" }, { col => 3, table => 2, text => "D2GRPH_LUT_10BIT_BYPASS_EN" }, { col => 3, table => 2, text => "D2GRPH_ENABLE" }, { col => 3, table => 2, text => "D2GRPH_X_START" }, { col => 3, table => 2, text => "D2GRPH_Y_START" }, { col => 3, table => 2, text => "D2GRPH_X_END" }, { col => 3, table => 2, text => "D2GRPH_Y_END" }, { col => 3, table => 2, text => "The mode register double buffering can only occur at ", }, { col => 3, table => 2, text => "vertical retrace. The double buffering occurs when ", }, { col => 3, table => 2, text => "D2GRPH_MODE_UPDATE_PENDING = 1 and " }, { col => 3, table => 2, text => "D2GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1.", }, { col => 3, table => 2, text => "If CRTC2 is disabled, the registers will be updated instantly.", }, { col => 3, table => 2, text => " 0=No update pending " }, { col => 3, table => 2, text => " 1=Update pending " }, { col => 0, table => 2, text => "D2GRPH_MODE_UPDATE_TAKEN (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphics update taken status for mode registers. ", }, { col => 3, table => 2, text => "It is set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 2, text => "V_UPDATE = 0." }, ], }, { num => 219, text => [ { col => 0, table => 0, text => "D2GRPH_SURFACE_UPDATE_PENDIN" }, { col => 0, table => 0, text => "G (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphic surface register update pending control. ", }, { col => 3, table => 0, text => "If it is set to 1 after a host write to graphics surface register. ", }, { col => 3, table => 0, text => "It is cleared after double buffering is done. It is cleared after ", }, { col => 3, table => 0, text => "double buffering is done." }, { col => 3, table => 0, text => "This signal also goes to both the RBBM wait_until and to ", }, { col => 3, table => 0, text => "the CP_RTS_discrete inputs." }, { col => 3, table => 0, text => "The graphics surface register includes: ", }, { col => 3, table => 0, text => "D2GRPH_PRIMARY_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D2GRPH_SECONDARY_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D2GRPH_PITCH" }, { col => 3, table => 0, text => "D2GRPH_SURFACE_OFFSET_X" }, { col => 3, table => 0, text => "D2GRPH_SURFACE_OFFSET_Y." }, { col => 3, table => 0, text => "If D2GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, ", }, { col => 3, table => 0, text => "the double buffering occurs in vertical retrace when ", }, { col => 3, table => 0, text => "D2GRPH_SURFACE_UPDATE_PENDING = 1 and " }, { col => 3, table => 0, text => "D2GRPH_UPDATE_LOCK = 0 and V_UPDATE = 1. ", }, { col => 3, table => 0, text => "Otherwise the double buffering happens at horizontal ", }, { col => 3, table => 0, text => "retrace when D2GRPH_SURFACE_UPDATE_PENDING = ", }, { col => 3, table => 0, text => "1 and D2GRPH_UPDATE_LOCK = 0 and Data request for ", }, { col => 3, table => 0, text => "last chunk of the line is sent from DCP to DMIF.", }, { col => 3, table => 0, text => "If CRTC2 is disabled, the registers will be updated instantly.", }, { col => 0, table => 0, text => "D2GRPH_SURFACE_UPDATE_TAKEN " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphics update taken status for surface ", }, { col => 3, table => 0, text => "registers. If " }, { col => 3, table => 0, text => "D2GRPH_SURFACE_UPDATE_H_RETRACE_EN = 0, it is ", }, { col => 3, table => 0, text => "set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 0, text => "V_UPDATE = 0. Otherwise, it is active for one clock cycle ", }, { col => 3, table => 0, text => "when double buffering occurs at the horizontal retrace.", }, { col => 0, table => 0, text => "D2GRPH_UPDATE_LOCK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphic register update lock control. This lock bit ", }, { col => 3, table => 0, text => "control both surface and mode register double buffer", }, { col => 3, table => 0, text => " 0=Unlocked " }, { col => 3, table => 0, text => " 1=Locked " }, { col => 0, table => 0, text => "D2GRPH_MODE_DISABLE_MULTIPLE_" }, { col => 0, table => 0, text => "UPDATE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D2GRPH mode registers can be updated multiple times ", }, { col => 3, table => 0, text => "in one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D2GRPH mode registers can only be updated once in ", }, { col => 3, table => 0, text => "one V_UPDATE period " }, { col => 0, table => 0, text => "D2GRPH_SURFACE_DISABLE_MULTIP" }, { col => 0, table => 0, text => "LE_UPDATE" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D2GRPH surface registers can be updated multiple ", }, { col => 3, table => 0, text => "times in one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D2GRPH surface registers can only be updated once in ", }, { col => undef, table => undef, text => "one V_UPDATE period " }, { col => undef, table => undef, text => "Secondary graphic update control", }, { col => "heading", table => 1, text => "D2GRPH_FLIP_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6948]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_SURFACE_UPDATE_H_RETR" }, { col => 0, table => 1, text => "ACE_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable secondary graphic surface register double buffer in ", }, { col => 3, table => 1, text => "horizontal retrace." }, { col => 3, table => 1, text => " 0=Vertical retrace flipping " }, { col => undef, table => undef, text => " 1=Horizontal retrace flipping ", }, { col => undef, table => undef, text => "Enable secondary graphic surface register double buffer in horizontal retrace", }, { col => undef, table => undef, text => "D2GRPH_SURFACE_ADDRESS_INUSE - RW - 32 bits - [GpuF0MMReg:0x694C]", }, ], }, { num => 220, text => [ { col => undef, table => undef, text => "2.7.13" }, { col => undef, table => undef, text => "Secondary Display Video Overlay Control Registers", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2GRPH_SURFACE_ADDRESS_INUSE " }, { col => undef, table => undef, text => "(R)" }, { col => undef, table => undef, text => "31:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This register reads back snapshot of secondary graphics ", }, { col => undef, table => undef, text => "surface address used for data request. The address is the ", }, { col => undef, table => undef, text => "signal sent to DMIF and is updated on SOF or horizontal ", }, { col => undef, table => undef, text => "surface update. The snapshot is triggered by writing 1 into ", }, { col => undef, table => undef, text => "field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC ", }, { col => undef, table => undef, text => "register D1CRTC_SNAPSHOT_STATUS.", }, { col => undef, table => undef, text => "Snapshot of secondary graphics surface address in use", }, { col => "heading", table => 0, text => "D2OVL_ENABLE - RW - 32 bits - [GpuF0MMReg:0x6980]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_ENABLE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay enabled." }, { col => 3, table => 0, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Secondary overlay enabled." }, { col => undef, table => undef, text => "D2OVL_CONTROL1 - RW - 32 bits - [GpuF0MMReg:0x6984]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2OVL_DEPTH" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary overlay pixel depth" }, { col => undef, table => undef, text => " 0=reserved " }, { col => undef, table => undef, text => " 1=16bpp " }, { col => undef, table => undef, text => " 2=32bpp " }, { col => undef, table => undef, text => " 3=reserved " }, { col => undef, table => undef, text => "D2OVL_Z" }, { col => undef, table => undef, text => "5:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Z[1:0] value for tiling" }, { col => undef, table => undef, text => "D2OVL_FORMAT" }, { col => undef, table => undef, text => "10:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary overlay pixel format. It is used together with ", }, { col => undef, table => undef, text => "D1OVL_DEPTH to define the overlay format.", }, { col => undef, table => undef, text => " If (D1OVL_DEPTH = 0x1)(16 bpp)" }, { col => undef, table => undef, text => " 0x0- ARGB 1555" }, { col => undef, table => undef, text => " 0x1 - RGB 565" }, { col => undef, table => undef, text => " 0x2 - BGRA 5551" }, { col => undef, table => undef, text => " others - reserved" }, { col => undef, table => undef, text => "else if (D1OVL_DEPTH = 0x2)(32 bpp)", }, { col => undef, table => undef, text => " 0x0 - ACrYCb 8888 or ARGB 8888", }, { col => undef, table => undef, text => " 0x1 - ACrYCb 2101010 or ARGB 2101010", }, { col => undef, table => undef, text => " 0x2 - CbACrA or BGRA 1010102" }, { col => undef, table => undef, text => " others - reserved" }, { col => undef, table => undef, text => "D2OVL_TILE_COMPACT_EN" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables multichip tile compaction", }, { col => undef, table => undef, text => " 0=Enables multichip tile compaction ", }, { col => undef, table => undef, text => "D2OVL_ADDRESS_TRANSLATION_EN" }, { col => undef, table => undef, text => "ABLE" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "enables Overlay 2 address translation", }, { col => undef, table => undef, text => " 0=0: physical memory " }, { col => undef, table => undef, text => " 1=1: virtual memory " }, { col => undef, table => undef, text => "D2OVL_PRIVILEGED_ACCESS_ENABL" }, { col => undef, table => undef, text => "E" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables overlay 2 privileged page access", }, { col => undef, table => undef, text => " 0=0: no privileged access " }, { col => undef, table => undef, text => " 1=1: privileged access " }, ], }, { num => 221, text => [ { col => undef, table => undef, text => "D2OVL_ARRAY_MODE" }, { col => undef, table => undef, text => "23:20" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Defines the tiling mode" }, { col => undef, table => undef, text => " 0=ARRAY_LINEAR_GENERAL: Unaligned linear array ", }, { col => undef, table => undef, text => " 1=ARRAY_LINEAR_ALIGNED: Aligned linear array ", }, { col => undef, table => undef, text => " 2=ARRAY_1D_TILED_THIN1: Uses 1D 8x8x1 tiles ", }, { col => undef, table => undef, text => " 3=ARRAY_1D_TILED_THICK: Uses 1D 8x8x4 tiles ", }, { col => undef, table => undef, text => " 4=ARRAY_2D_TILED_THIN1: Uses 8x8x1 macro-tiles ", }, { col => undef, table => undef, text => " 5=ARRAY_2D_TILED_THIN2: Macro-tiles are 2x high ", }, { col => undef, table => undef, text => " 6=ARRAY_2D_TILED_THIN4: Macro-tiles are 4x high ", }, { col => undef, table => undef, text => " 7=ARRAY_2D_TILED_THICK: Uses 8x8x4 macro-tiles ", }, { col => undef, table => undef, text => " 8=ARRAY_2B_TILED_THIN1: uses row bank swapping ", }, { col => undef, table => undef, text => " 9=ARRAY_2B_TILED_THIN2: uses row bank swapping ", }, { col => undef, table => undef, text => " 10=ARRAY_2B_TILED_THIN4: uses row bank swapping ", }, { col => undef, table => undef, text => " 11=ARRAY_2B_TILED_THICK: uses row bank swapping ", }, { col => undef, table => undef, text => " 12=ARRAY_3D_TILED_THIN1: Slices are pipe rotated ", }, { col => undef, table => undef, text => " 13=ARRAY_3D_TILED_THICK: Slices are pipe rotated ", }, { col => undef, table => undef, text => " 14=ARRAY_3B_TILED_THIN1: Slices are pipe rotated ", }, { col => undef, table => undef, text => " 15=ARRAY_3B_TILED_THICK: Slices are pipe rotated ", }, { col => undef, table => undef, text => "D2OVL_COLOR_EXPANSION_MODE" }, { col => undef, table => undef, text => 24 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary overlay pixel format expansion mode.", }, { col => undef, table => undef, text => " 0=dynamic expansion for RGB " }, { col => undef, table => undef, text => " 1=zero expansion for YCbCr " }, { col => undef, table => undef, text => "Secondary overlay pixel depth and format.", }, { col => "heading", table => 1, text => "D2OVL_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x6988]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_HALF_RESOLUTION_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay half resolution control", }, { col => 3, table => 1, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Secondary overlay half resolution control", }, { col => "heading", table => 2, text => "D2OVL_SWAP_CNTL - RW - 32 bits - [GpuF0MMReg:0x698C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_ENDIAN_SWAP" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "MC endian swap select" }, { col => 3, table => 2, text => " 0=0=none " }, { col => 3, table => 2, text => " 1=1=8in16(0xaabb=>0xbbaa) " }, { col => 3, table => 2, text => " 2=2=8in32(0xaabbccdd=>0xddccbbaa) " }, { col => 3, table => 2, text => " 3=3=8in64(0xaabbccddeeff0011=>0x1100ffeeddccbbaa) ", }, { col => 0, table => 2, text => "D2OVL_RED_CROSSBAR" }, { col => 1, table => 2, text => "5:4" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Red Crossbar select" }, { col => 3, table => 2, text => " 0=0=select from R " }, { col => 3, table => 2, text => " 1=1=select from G " }, { col => 3, table => 2, text => " 2=2=select from B " }, { col => 3, table => 2, text => " 3=3=select from A " }, { col => 0, table => 2, text => "D2OVL_GREEN_CROSSBAR" }, { col => 1, table => 2, text => "7:6" }, { col => 2, table => 2, text => "0x0Green Crossbar select" }, { col => 3, table => 2, text => " 0=0=select from G " }, { col => 3, table => 2, text => " 1=1=select from B " }, { col => 3, table => 2, text => " 2=2=select from A " }, { col => 3, table => 2, text => " 3=3=select from R " }, { col => 0, table => 2, text => "D2OVL_BLUE_CROSSBAR" }, { col => 1, table => 2, text => "9:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Blue Crossbar select" }, { col => 3, table => 2, text => " 0=0=select from B " }, { col => 3, table => 2, text => " 1=1=select from A " }, { col => 3, table => 2, text => " 2=2=select from R " }, { col => 3, table => 2, text => " 3=3=select from G " }, ], }, { num => 222, text => [ { col => 0, table => 0, text => "D2OVL_ALPHA_CROSSBAR" }, { col => 1, table => 0, text => "11:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Alpha Crossbar select" }, { col => 3, table => 0, text => " 0=0=select from A " }, { col => 3, table => 0, text => " 1=1=select from R " }, { col => 3, table => 0, text => " 2=2=select from G " }, { col => undef, table => undef, text => " 3=3=select from B " }, { col => undef, table => undef, text => "Endian swap and component reorder control", }, { col => "heading", table => 1, text => "D2OVL_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6990]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_DFQ_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay surface address DFQ enable", }, { col => 0, table => 1, text => "D2OVL_SURFACE_ADDRESS" }, { col => 1, table => 1, text => "31:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay surface base address in byte. It is 256 ", }, { col => undef, table => undef, text => "bytes aligned." }, { col => undef, table => undef, text => "Secondary overlay surface base address in byte.", }, { col => "heading", table => 2, text => "D2OVL_PITCH - RW - 32 bits - [GpuF0MMReg:0x6998]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_PITCH" }, { col => 1, table => 2, text => "13:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay surface pitch in pixels. For ", }, { col => 3, table => 2, text => "Micro-tiled/Macro-tiled surface, it must be multiple of 64 ", }, { col => 3, table => 2, text => "pixeld in 8bpp mode. For Micro-linear/Macro-tiled surface, it ", }, { col => 3, table => 2, text => "must be multiple of 256 pixeld in 8bpp mode, multiple of 128 ", }, { col => 3, table => 2, text => "pixels in 16bpp mode and multiple of 64 pixels in 32bpp ", }, { col => 3, table => 2, text => "mode. For Micro-linear/Macro-linear surface, it must be ", }, { col => 3, table => 2, text => "multiple of 64 pixels in 8bpp mode. For other modes, it must ", }, { col => 3, table => 2, text => "be multiple of 32." }, { col => undef, table => undef, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary overlay surface pitch in pixels.", }, { col => "heading", table => 3, text => "D2OVL_SURFACE_OFFSET_X - RW - 32 bits - [GpuF0MMReg:0x699C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_SURFACE_OFFSET_X" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary overlay X surface offset. It is 256 pixels aligned.", }, { col => undef, table => undef, text => "NOTE: Bits 0:7 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary overlay X surface offset.", }, { col => "heading", table => 4, text => "D2OVL_SURFACE_OFFSET_Y - RW - 32 bits - [GpuF0MMReg:0x69A0]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2OVL_SURFACE_OFFSET_Y" }, { col => 1, table => 4, text => "12:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Secondary overlay Y surface offset. It is even value.", }, { col => undef, table => undef, text => "NOTE: Bit 0 of this field is hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary overlay Y surface offset.", }, ], }, { num => 223, text => [ { col => "heading", table => 0, text => "D2OVL_START - RW - 32 bits - [GpuF0MMReg:0x69A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_Y_START" }, { col => 1, table => 0, text => "12:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay Y start coordinate relative to the desktop ", }, { col => 3, table => 0, text => "coordinates." }, { col => 0, table => 0, text => "D2OVL_X_START" }, { col => 1, table => 0, text => "28:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay X start coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates." }, { col => undef, table => undef, text => "Secondary overlay X, Y start coordinate relative to the desktop coordinates.", }, { col => "heading", table => 1, text => "D2OVL_END - RW - 32 bits - [GpuF0MMReg:0x69A8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_Y_END" }, { col => 1, table => 1, text => "13:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay Y end coordinate relative to the desktop ", }, { col => 3, table => 1, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => 0, table => 1, text => "D2OVL_X_END" }, { col => 1, table => 1, text => "29:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay X end coordinate relative to the desktop ", }, { col => undef, table => undef, text => "coordinates. It is exclusive and the maximum value is 8K", }, { col => undef, table => undef, text => "Secondary overlay X, Y end coordinate relative to the desktop coordinates.", }, { col => "heading", table => 2, text => "D2OVL_UPDATE - RW - 32 bits - [GpuF0MMReg:0x69AC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_UPDATE_PENDING (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay register update pending control. It is set ", }, { col => 3, table => 2, text => "to 1 after a host write to overlay double buffer register. It is ", }, { col => 3, table => 2, text => "cleared after double buffering is done. The double buffering ", }, { col => 3, table => 2, text => "occurs when UPDATE_PENDING = 1 and UPDATE_LOCK ", }, { col => 3, table => 2, text => "= 0 and V_UPDATE = 1." }, { col => 3, table => 2, text => "If CRTC2 is disabled, the registers will be updated instantly.", }, { col => 3, table => 2, text => "D2OVL double buffer registers include:" }, { col => 3, table => 2, text => "D2OVL_ENABLE" }, { col => 3, table => 2, text => "D2OVL_DEPTH" }, { col => 3, table => 2, text => "D2OVL_FORMAT" }, { col => 3, table => 2, text => "D2OVL_SWAP_RB" }, { col => 3, table => 2, text => "D2OVL_COLOR_EXPANSION_MODE" }, { col => 3, table => 2, text => "D2OVL_HALF_RESOLUTION_ENABLE" }, { col => 3, table => 2, text => "D2OVL_SURFACE_ADDRESS" }, { col => 3, table => 2, text => "D2OVL_PITCH" }, { col => 3, table => 2, text => "D2OVL_SURFACE_OFFSET_X" }, { col => 3, table => 2, text => "D2OVL_SURFACE_OFFSET_Y" }, { col => 3, table => 2, text => "D2OVL_START" }, { col => 3, table => 2, text => "D2OVL_END" }, { col => 3, table => 2, text => " 0=No update pending " }, { col => 3, table => 2, text => " 1=Update pending " }, { col => 0, table => 2, text => "D2OVL_UPDATE_TAKEN (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay update taken status. It is set to 1 when ", }, { col => 3, table => 2, text => "double buffering occurs and cleared when V_UPDATE = 0.", }, { col => 0, table => 2, text => "D2OVL_UPDATE_LOCK" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay register update lock control.", }, { col => 3, table => 2, text => " 0=Unlocked " }, { col => 3, table => 2, text => " 1=Locked " }, { col => 0, table => 2, text => "D2OVL_DISABLE_MULTIPLE_UPDATE" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=D2OVL registers can be updated multiple times in one ", }, { col => 3, table => 2, text => "V_UPDATE period " }, { col => 3, table => 2, text => " 1=D2OVL registers can only be updated once in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => "Secondary overlay register update", }, ], }, { num => 224, text => [ { col => undef, table => undef, text => "2.7.14" }, { col => undef, table => undef, text => "Secondary Display Video Overlay Transform Registers", }, { col => "heading", table => 0, text => "D2OVL_SURFACE_ADDRESS_INUSE - RW - 32 bits - [GpuF0MMReg:0x69B0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_SURFACE_ADDRESS_INUSE " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => "31:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "This register reads back snapshot of secondary overlay ", }, { col => 3, table => 0, text => "surface address used for data request. The address is the ", }, { col => 3, table => 0, text => "signal sent to DMIF and is updated on SOF or horizontal ", }, { col => 3, table => 0, text => "surface update. The snapshot is triggered by writing 1 into ", }, { col => 3, table => 0, text => "field D1CRTC_SNAPSHOT_MANUAL_TRIGGER of CRTC ", }, { col => undef, table => undef, text => "register D1CRTC_SNAPSHOT_STATUS.", }, { col => undef, table => undef, text => "Snapshot of secondary overlay surface address in use", }, { col => "heading", table => 1, text => "D2OVL_DFQ_CONTROL - RW - 32 bits - [GpuF0MMReg:0x69B4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_DFQ_RESET" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reset the deep flip queue" }, { col => 0, table => 1, text => "D2OVL_DFQ_SIZE" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Size of the deep flip queue: 0 = 1 deep queue, 1 = 2 deep ", }, { col => 3, table => 1, text => "queue,..., 7 = 8 deep queue" }, { col => 0, table => 1, text => "D2OVL_DFQ_MIN_FREE_ENTRIES" }, { col => 1, table => 1, text => "10:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Minimum # of free entries before surface pending is ", }, { col => undef, table => undef, text => "asserted" }, { col => undef, table => undef, text => "Control of the deep flip queue for D2 overlay", }, { col => "heading", table => 2, text => "D2OVL_DFQ_STATUS - RW - 32 bits - [GpuF0MMReg:0x69B8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_DFQ_NUM_ENTRIES (R)" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "# of entries in deep flip queue. 0 = 1 entry, 1 = 2 entries, ... 7 ", }, { col => 3, table => 2, text => "= 8 entries" }, { col => 0, table => 2, text => "D2OVL_DFQ_RESET_FLAG (R)" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Sticky bit: Deep flip queue in reset" }, { col => 0, table => 2, text => "D2OVL_DFQ_RESET_ACK (W)" }, { col => 1, table => 2, text => 9 }, { col => undef, table => undef, text => "0x0Clear D2OVL_DFQ_RESET_FLAG" }, { col => undef, table => undef, text => "Status of the deep flip queue for D2 overlay", }, { col => "heading", table => 3, text => "D2OVL_MATRIX_TRANSFORM_EN - RW - 32 bits - [GpuF0MMReg:0x6A00]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_MATRIX_TRANSFORM_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary overlay matrix conversion enable", }, { col => 3, table => 3, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Secondary overlay matrix conversion enable.", }, ], }, { num => 225, text => [ { col => "heading", table => 0, text => "D2OVL_MATRIX_COEF_1_1 - RW - 32 bits - [GpuF0MMReg:0x6A04]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_MATRIX_COEF_1_1" }, { col => 1, table => 0, text => "18:0" }, { col => 2, table => 0, text => "0x198a0" }, { col => 3, table => 0, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 0, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 0, text => "fix-point S3.11." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D2OVL_MATRIX_SIGN_1_1" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 1, text => "D2OVL_MATRIX_COEF_1_2 - RW - 32 bits - [GpuF0MMReg:0x6A08]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_MATRIX_COEF_1_2" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x12a20" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 1, text => "fix-point S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2OVL_MATRIX_SIGN_1_2" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 2, text => "D2OVL_MATRIX_COEF_1_3 - RW - 32 bits - [GpuF0MMReg:0x6A0C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_MATRIX_COEF_1_3" }, { col => 1, table => 2, text => "18:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 2, text => "fix-point S3.11." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2OVL_MATRIX_SIGN_1_3" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 3, text => "D2OVL_MATRIX_COEF_1_4 - RW - 32 bits - [GpuF0MMReg:0x6A10]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_MATRIX_COEF_1_4" }, { col => 1, table => 3, text => "26:8" }, { col => 2, table => 3, text => "0x48700" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 3, text => "fix-point S11.1." }, { col => 3, table => 3, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2OVL_MATRIX_SIGN_1_4" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => undef, table => undef, text => "D2OVL_MATRIX_COEF_2_1 - RW - 32 bits - [GpuF0MMReg:0x6A14]", }, ], }, { num => 226, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_MATRIX_COEF_2_1" }, { col => 1, table => 0, text => "18:0" }, { col => 2, table => 0, text => "0x72fe0" }, { col => 3, table => 0, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 0, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 0, text => "fix-point S3.11." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D2OVL_MATRIX_SIGN_2_1" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 1, text => "D2OVL_MATRIX_COEF_2_2 - RW - 32 bits - [GpuF0MMReg:0x6A18]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_MATRIX_COEF_2_2" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x12a20" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 1, text => "fix-point S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2OVL_MATRIX_SIGN_2_2" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 2, text => "D2OVL_MATRIX_COEF_2_3 - RW - 32 bits - [GpuF0MMReg:0x6A1C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_MATRIX_COEF_2_3" }, { col => 1, table => 2, text => "18:0" }, { col => 2, table => 2, text => "0x79bc0" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 2, text => "fix-point S3.11." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2OVL_MATRIX_SIGN_2_3" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 3, text => "D2OVL_MATRIX_COEF_2_4 - RW - 32 bits - [GpuF0MMReg:0x6A20]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_MATRIX_COEF_2_4" }, { col => 1, table => 3, text => "26:8" }, { col => 2, table => 3, text => "0x22100" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 3, text => "fix-point S11.1." }, { col => 3, table => 3, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2OVL_MATRIX_SIGN_2_4" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 4, text => "D2OVL_MATRIX_COEF_3_1 - RW - 32 bits - [GpuF0MMReg:0x6A24]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 227, text => [ { col => 0, table => 0, text => "D2OVL_MATRIX_COEF_3_1" }, { col => 1, table => 0, text => "18:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 0, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 0, text => "fix-point S3.11." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D2OVL_MATRIX_SIGN_3_1" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 1, text => "D2OVL_MATRIX_COEF_3_2 - RW - 32 bits - [GpuF0MMReg:0x6A28]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_MATRIX_COEF_3_2" }, { col => 1, table => 1, text => "18:0" }, { col => 2, table => 1, text => "0x12a20" }, { col => 3, table => 1, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 1, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 1, text => "fix-point S3.11." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2OVL_MATRIX_SIGN_3_2" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 2, text => "D2OVL_MATRIX_COEF_3_3 - RW - 32 bits - [GpuF0MMReg:0x6A2C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_MATRIX_COEF_3_3" }, { col => 1, table => 2, text => "18:0" }, { col => 2, table => 2, text => "0x20460" }, { col => 3, table => 2, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 2, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 2, text => "fix-point S3.11." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2OVL_MATRIX_SIGN_3_3" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 3, text => "D2OVL_MATRIX_COEF_3_4 - RW - 32 bits - [GpuF0MMReg:0x6A30]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_MATRIX_COEF_3_4" }, { col => 1, table => 3, text => "26:8" }, { col => 2, table => 3, text => "0x3af80" }, { col => 3, table => 3, text => "Combined matrix constant of YCbCr->RGB, contrast and ", }, { col => 3, table => 3, text => "brightness adjustment for secondary overlay. Format ", }, { col => 3, table => 3, text => "fix-point S11.1." }, { col => 3, table => 3, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2OVL_MATRIX_SIGN_3_4" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x1" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant of YCbCr->RGB, contrast and brightness adjustment for secondary overlay.", }, { col => "heading", table => 4, text => "D2OVL_COLOR_MATRIX_TRANSFORMATION_CNTL - RW - 32 bits - [GpuF0MMReg:0x6940]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2OVL_COLOR_MATRIX_TRANSFORM" }, { col => 0, table => 4, text => "ATION_CNTL" }, { col => 1, table => 4, text => "2:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Matrix transformation control for secondary display overlay ", }, { col => undef, table => undef, text => "pixels. It is used when PIX_TYPE is 0.", }, { col => undef, table => undef, text => "Matrix transformation control for secondary display overlay pixels.", }, ], }, { num => 228, text => [ { col => undef, table => undef, text => "2.7.15" }, { col => undef, table => undef, text => "Secondary Display Video Overlay Gamma Correction Registers", }, { col => "heading", table => 0, text => "D2OVL_PWL_TRANSFORM_EN - RW - 32 bits - [GpuF0MMReg:0x6A80]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_PWL_TRANSFORM_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay gamma correction enable.", }, { col => 3, table => 0, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Secondary overlay gamma correction enable.", }, { col => "heading", table => 1, text => "D2OVL_PWL_0TOF - RW - 32 bits - [GpuF0MMReg:0x6A84]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_PWL_0TOF_OFFSET" }, { col => 1, table => 1, text => "8:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 0x0-0xF. Format fix-point 8.1 (0.0 to +255.5).", }, { col => 0, table => 1, text => "D2OVL_PWL_0TOF_SLOPE" }, { col => 1, table => 1, text => "26:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 0x0-0xF. Format fix-point 3.8 (0.00 to +7.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 0x0-0xF", }, { col => "heading", table => 2, text => "D2OVL_PWL_10TO1F - RW - 32 bits - [GpuF0MMReg:0x6A88]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_PWL_10TO1F_OFFSET" }, { col => 1, table => 2, text => "8:0" }, { col => 2, table => 2, text => "0x20" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 0x10-0x1F. Format fix-point 8.1 (0.0 to +255.5).", }, { col => 0, table => 2, text => "D2OVL_PWL_10TO1F_SLOPE" }, { col => 1, table => 2, text => "26:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 0x10-0x1F. Format fix-point 3.8 (0.00 to +7.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 0x10-0x1F", }, { col => "heading", table => 3, text => "D2OVL_PWL_20TO3F - RW - 32 bits - [GpuF0MMReg:0x6A8C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_PWL_20TO3F_OFFSET" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x40" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 0x20-0x3F. Format fix-point 9.1 (0.0 to +511.5).", }, { col => 0, table => 3, text => "D2OVL_PWL_20TO3F_SLOPE" }, { col => 1, table => 3, text => "25:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 0x20-0x3F. Format fix-point 2.8 (0.00 to +3.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 0x20-0x3F", }, { col => "heading", table => 4, text => "D2OVL_PWL_40TO7F - RW - 32 bits - [GpuF0MMReg:0x6A90]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 229, text => [ { col => 0, table => 0, text => "D2OVL_PWL_40TO7F_OFFSET" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x80" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 40-7F. Format fix-point 9.1 (0.0 to +511.5).", }, { col => 0, table => 0, text => "D2OVL_PWL_40TO7F_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 40-7F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 40-7F.", }, { col => "heading", table => 1, text => "D2OVL_PWL_80TOBF - RW - 32 bits - [GpuF0MMReg:0x6A94]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_PWL_80TOBF_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 80-BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D2OVL_PWL_80TOBF_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 80-BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 80-BF.", }, { col => "heading", table => 2, text => "D2OVL_PWL_C0TOFF - RW - 32 bits - [GpuF0MMReg:0x6A98]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_PWL_C0TOFF_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x180" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input C0-FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D2OVL_PWL_C0TOFF_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input C0-FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input C0-FF.", }, { col => "heading", table => 3, text => "D2OVL_PWL_100TO13F - RW - 32 bits - [GpuF0MMReg:0x6A9C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_PWL_100TO13F_OFFSET" }, { col => 1, table => 3, text => "10:0" }, { col => 2, table => 3, text => "0x200" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 100-13F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 3, text => "D2OVL_PWL_100TO13F_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 100-13F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 100-13F.", }, { col => "heading", table => 4, text => "D2OVL_PWL_140TO17F - RW - 32 bits - [GpuF0MMReg:0x6AA0]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2OVL_PWL_140TO17F_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x280" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 140-17F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D2OVL_PWL_140TO17F_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 140-17F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 140-17F.", }, ], }, { num => 230, text => [ { col => "heading", table => 0, text => "D2OVL_PWL_180TO1BF - RW - 32 bits - [GpuF0MMReg:0x6AA4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_PWL_180TO1BF_OFFSET" }, { col => 1, table => 0, text => "10:0" }, { col => 2, table => 0, text => "0x300" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 180-1BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 0, text => "D2OVL_PWL_180TO1BF_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 180-1BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 180-1BF.", }, { col => "heading", table => 1, text => "D2OVL_PWL_1C0TO1FF - RW - 32 bits - [GpuF0MMReg:0x6AA8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_PWL_1C0TO1FF_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x380" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 1C0-1FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D2OVL_PWL_1C0TO1FF_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 1C0-1FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 1C0-1FF.", }, { col => "heading", table => 2, text => "D2OVL_PWL_200TO23F - RW - 32 bits - [GpuF0MMReg:0x6AAC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_PWL_200TO23F_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x400" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 200-23F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D2OVL_PWL_200TO23F_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 200-23F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 200-23F.", }, { col => "heading", table => 3, text => "D2OVL_PWL_240TO27F - RW - 32 bits - [GpuF0MMReg:0x6AB0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_PWL_240TO27F_OFFSET" }, { col => 1, table => 3, text => "10:0" }, { col => 2, table => 3, text => "0x480" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 240-27F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 3, text => "D2OVL_PWL_240TO27F_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 240-27F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 240-27F.", }, { col => "heading", table => 4, text => "D2OVL_PWL_280TO2BF - RW - 32 bits - [GpuF0MMReg:0x6AB4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2OVL_PWL_280TO2BF_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x500" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 280-2BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D2OVL_PWL_280TO2BF_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 280-2BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 280-2BF.", }, ], }, { num => 231, text => [ { col => "heading", table => 0, text => "D2OVL_PWL_2C0TO2FF - RW - 32 bits - [GpuF0MMReg:0x6AB8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_PWL_2C0TO2FF_OFFSET" }, { col => 1, table => 0, text => "10:0" }, { col => 2, table => 0, text => "0x580" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 0, text => "input 2C0-2FF. Format fix-point 10.1(0.0 to +1023.5).", }, { col => 0, table => 0, text => "D2OVL_PWL_2C0TO2FF_SLOPE" }, { col => 1, table => 0, text => "24:16" }, { col => 2, table => 0, text => "0x100" }, { col => 3, table => 0, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 2C0-2FF. Format fix-point 1.8(0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 2C0-2FF.", }, { col => "heading", table => 1, text => "D2OVL_PWL_300TO33F - RW - 32 bits - [GpuF0MMReg:0x6ABC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_PWL_300TO33F_OFFSET" }, { col => 1, table => 1, text => "10:0" }, { col => 2, table => 1, text => "0x600" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 1, text => "input 300-33F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 1, text => "D2OVL_PWL_300TO33F_SLOPE" }, { col => 1, table => 1, text => "24:16" }, { col => 2, table => 1, text => "0x100" }, { col => 3, table => 1, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 300-33F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 300-33F.", }, { col => "heading", table => 2, text => "D2OVL_PWL_340TO37F - RW - 32 bits - [GpuF0MMReg:0x6AC0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_PWL_340TO37F_OFFSET" }, { col => 1, table => 2, text => "10:0" }, { col => 2, table => 2, text => "0x680" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 2, text => "input 340-37F. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 2, text => "D2OVL_PWL_340TO37F_SLOPE" }, { col => 1, table => 2, text => "24:16" }, { col => 2, table => 2, text => "0x100" }, { col => 3, table => 2, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 340-37F. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 340-37F.", }, { col => "heading", table => 3, text => "D2OVL_PWL_380TO3BF - RW - 32 bits - [GpuF0MMReg:0x6AC4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_PWL_380TO3BF_OFFSET" }, { col => 1, table => 3, text => "10:0" }, { col => 2, table => 3, text => "0x700" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 3, text => "input 380-3BF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 3, text => "D2OVL_PWL_380TO3BF_SLOPE" }, { col => 1, table => 3, text => "24:16" }, { col => 2, table => 3, text => "0x100" }, { col => 3, table => 3, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 380-3BF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 380-3BF.", }, { col => "heading", table => 4, text => "D2OVL_PWL_3C0TO3FF - RW - 32 bits - [GpuF0MMReg:0x6AC8]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2OVL_PWL_3C0TO3FF_OFFSET" }, { col => 1, table => 4, text => "10:0" }, { col => 2, table => 4, text => "0x780" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear offset for ", }, { col => 3, table => 4, text => "input 3C0-3FF. Format fix-point 10.1 (0.0 to +1023.5).", }, { col => 0, table => 4, text => "D2OVL_PWL_3C0TO3FF_SLOPE" }, { col => 1, table => 4, text => "24:16" }, { col => 2, table => 4, text => "0x100" }, { col => 3, table => 4, text => "Secondary overlay gamma correction non-linear slope for ", }, { col => undef, table => undef, text => "input 3C0-3FF. Format fix-point 1.8 (0.00 to +1.99).", }, { col => undef, table => undef, text => "Secondary overlay gamma correction non-linear offset and slope for input 3C0-3FF.", }, ], }, { num => 232, text => [ { col => undef, table => undef, text => "2.7.16" }, { col => undef, table => undef, text => "Secondary Display Graphics and Overlay Blending Registers", }, { col => "heading", table => 0, text => "D2OVL_KEY_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6B00]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2GRPH_KEY_FUNCTION" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects graphic keyer result equation for secondary display.", }, { col => 3, table => 0, text => " 0=GRPH2_KEY = FALSE = 0 " }, { col => 3, table => 0, text => " 1=GRPH2_KEY = TRUE = 1 " }, { col => 3, table => 0, text => " 2=GPPH2_KEY = (GRPH2_RED in range) AND ", }, { col => 3, table => 0, text => "(GRPH2_GREEN in range) AND (GRPH2_BLUE in range) ", }, { col => 3, table => 0, text => "AND (GRPH2_ALPHA in range) " }, { col => 3, table => 0, text => " 3=GRPH2_KEY = not [(GRPH2_RED in range) AND ", }, { col => 3, table => 0, text => "(GRPH2_GREEN in range) AND (GRPH2_BLUE in range) ", }, { col => 3, table => 0, text => "AND (GRPH2_ALPHA in range)] " }, { col => 0, table => 0, text => "D2OVL_KEY_FUNCTION" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects overlay keyer result equation for secondary display.", }, { col => 3, table => 0, text => " 0=OVL2_KEY = FALSE = 0 " }, { col => 3, table => 0, text => " 1=OVL2_KEY = TRUE = 1 " }, { col => 3, table => 0, text => " 2=OVL2_KEY = (OVL2_Cr_RED in range) AND ", }, { col => 3, table => 0, text => "(OVL2_Y_GREEN in range) AND (OVL2_Cb_BLUE in ", }, { col => 3, table => 0, text => "range) AND (OVL2_ALPHA in range) " }, { col => 3, table => 0, text => " 3=OVL2_KEY = not [(OVL2_Cr_RED in range) AND ", }, { col => 3, table => 0, text => "(OVL2_Y_GREEN in range) AND (OVL2_Cb_BLUE in ", }, { col => 3, table => 0, text => "range) AND (OVL2_ALPHA in range)] " }, { col => 0, table => 0, text => "D2OVL_KEY_COMPARE_MIX" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects final mix of graphics and overlay keys for secondary ", }, { col => 3, table => 0, text => "display." }, { col => 3, table => 0, text => " 0=GRPH_OVL_KEY = GRPH_KEY or OVL_KEY ", }, { col => undef, table => undef, text => " 1=GRPH_OVL_KEY = GRPH_KEY and OVL_KEY ", }, { col => undef, table => undef, text => "Secondary display key control" }, { col => "heading", table => 1, text => "D2GRPH_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6B04]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_ALPHA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "Global graphic alpha for use in key mode and global alpha ", }, { col => 3, table => 1, text => "modes. See D2OVL_ALPHA_MODE register filed for more ", }, { col => undef, table => undef, text => "details" }, { col => undef, table => undef, text => "Global graphic alpha for use in key mode and global alpha modes.", }, { col => "heading", table => 2, text => "D2OVL_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6B08]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_ALPHA" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "Global overlay alpha for use in key mode and global alpha ", }, { col => 3, table => 2, text => "modes. See D2OVL_ALPHA_MODE register filed for more ", }, { col => undef, table => undef, text => "details" }, { col => undef, table => undef, text => "Global overlay alpha for use in key mode and global alpha modes.", }, ], }, { num => 233, text => [ { col => "heading", table => 0, text => "D2OVL_ALPHA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6B0C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_ALPHA_MODE" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Graphics/overlay alpha blending mode for secondary ", }, { col => 3, table => 0, text => "controller." }, { col => 3, table => 0, text => "In any case, if there is only graphics, the input OVL_DATA ", }, { col => 3, table => 0, text => "is forced to blank. If there is only overlay, the input ", }, { col => 3, table => 0, text => "GRPH_DATA is forced to blank." }, { col => 3, table => 0, text => " 0=Keyer mode, select graphic or overlay keyer to mix ", }, { col => 3, table => 0, text => "graphics and overlay " }, { col => 3, table => 0, text => " 1=Per pixel graphic alpha mode.Alpha blend graphic and ", }, { col => 3, table => 0, text => "overlay layer. The alpha from graphic pixel may be inverted ", }, { col => 3, table => 0, text => "according to register field " }, { col => 3, table => 0, text => " 2=Global alpha mode " }, { col => 3, table => 0, text => " 3=Per pixel overlay alpha mode " }, { col => 0, table => 0, text => "D2OVL_ALPHA_PREMULT" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For use with per pixel alpha blend mode. Selects whether ", }, { col => 3, table => 0, text => "pre-multiplied alpha or non-multiplied alpha.", }, { col => 3, table => 0, text => " 0=0x0 - When DxOVL_ALPHA_MODE = 0x1, then Pixel = ", }, { col => 3, table => 0, text => "PIX_ALPHA * graphics pixel + (1-PIX_ALPHA) * overlay ", }, { col => 3, table => 0, text => "pixel.When DxOVL_ALPHA_MODE = 0x3, then Pixel = ", }, { col => 3, table => 0, text => "PIX_ALPHA * overlay pixel + (1-PIX_ALPHA) * graphic ", }, { col => 3, table => 0, text => "pixel " }, { col => 3, table => 0, text => " 1=0x1 - When DxOVL_ALPHA_MODE = 0x1, then Pixel = ", }, { col => 3, table => 0, text => "graphic pixel + (1-PIX_ALPHA) * overlay pixel.When ", }, { col => 3, table => 0, text => "DxOVL_ALPHA_MODE = 0x3, then Pixel = overlay pixel + ", }, { col => 3, table => 0, text => "(1-PIX_ALPHA) * graphic pixel " }, { col => 0, table => 0, text => "D2OVL_ALPHA_INV" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "For use with pixel blend mode. Apply optional inversion to ", }, { col => 3, table => 0, text => "the alpha value extracted form the graphics or overlay ", }, { col => 3, table => 0, text => "surface data." }, { col => 3, table => 0, text => " 0=PIX_ALPHA = alpha from graphics or overlay ", }, { col => undef, table => undef, text => " 1=PIX_ALPHA = 1 - alpha from graphics or overlay ", }, { col => undef, table => undef, text => "Secondary display graphics/overlay alpha blending control", }, { col => "heading", table => 1, text => "D2GRPH_KEY_RANGE_RED - RW - 32 bits - [GpuF0MMReg:0x6B10]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_KEY_RED_LOW" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphics keyer red component lower limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D2GRPH_KEY_RED_HIGH" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphics keyer red component upper limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary graphics keyer red component range", }, { col => "heading", table => 2, text => "D2GRPH_KEY_RANGE_GREEN - RW - 32 bits - [GpuF0MMReg:0x6B14]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 234, text => [ { col => 0, table => 0, text => "D2GRPH_KEY_GREEN_LOW" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphics keyer green component lower limit.", }, { col => 3, table => 0, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 0, text => "all zeros." }, { col => 0, table => 0, text => "D2GRPH_KEY_GREEN_HIGH" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary graphics keyer green component upper limit.", }, { col => 3, table => 0, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary graphics keyer green component range", }, { col => "heading", table => 1, text => "D2GRPH_KEY_RANGE_BLUE - RW - 32 bits - [GpuF0MMReg:0x6B18]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2GRPH_KEY_BLUE_LOW" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphics keyer blue component lower limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D2GRPH_KEY_BLUE_HIGH" }, { col => 1, table => 1, text => "31:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary graphics keyer blue component upper limit.", }, { col => 3, table => 1, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary graphics keyer blue component range", }, { col => "heading", table => 2, text => "D2GRPH_KEY_RANGE_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6B1C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2GRPH_KEY_ALPHA_LOW" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphics keyer alpha component lower limit.", }, { col => 3, table => 2, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => 3, table => 2, text => "all zeros." }, { col => 0, table => 2, text => "D2GRPH_KEY_ALPHA_HIGH" }, { col => 1, table => 2, text => "31:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary graphics keyer alpha component upper limit.", }, { col => 3, table => 2, text => "Note: If the graphic component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary graphics keyer alpha component range", }, { col => "heading", table => 3, text => "D2OVL_KEY_RANGE_RED_CR - RW - 32 bits - [GpuF0MMReg:0x6B20]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2OVL_KEY_RED_CR_LOW" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary overlay keyer red component lower limit.", }, { col => 3, table => 3, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 3, text => "all zeros." }, { col => 0, table => 3, text => "D2OVL_KEY_RED_CR_HIGH" }, { col => 1, table => 3, text => "25:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary overlay keyer red component upper limit.", }, { col => 3, table => 3, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary overlay keyer red component range", }, ], }, { num => 235, text => [ { col => undef, table => undef, text => "2.7.17" }, { col => undef, table => undef, text => "Secondary Display Color Matrix Transform Registers", }, { col => "heading", table => 0, text => "D2OVL_KEY_RANGE_GREEN_Y - RW - 32 bits - [GpuF0MMReg:0x6B24]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_KEY_GREEN_Y_LOW" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay keyer green component lower limit.", }, { col => 3, table => 0, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 0, text => "all zeros." }, { col => 0, table => 0, text => "D2OVL_KEY_GREEN_Y_HIGH" }, { col => 1, table => 0, text => "25:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary overlay keyer green component upper limit.", }, { col => 3, table => 0, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary overlay keyer green component range", }, { col => "heading", table => 1, text => "D2OVL_KEY_RANGE_BLUE_CB - RW - 32 bits - [GpuF0MMReg:0x6B28]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_KEY_BLUE_CB_LOW" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay keyer blue component lower limit.", }, { col => 3, table => 1, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 1, text => "all zeros." }, { col => 0, table => 1, text => "D2OVL_KEY_BLUE_CB_HIGH" }, { col => 1, table => 1, text => "25:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary overlay keyer blue component upper limit.", }, { col => 3, table => 1, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary overlay keyer blue component range", }, { col => "heading", table => 2, text => "D2OVL_KEY_ALPHA - RW - 32 bits - [GpuF0MMReg:0x6B2C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_KEY_ALPHA_LOW" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay keyer alpha component lower limit.", }, { col => 3, table => 2, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => 3, table => 2, text => "all zeros." }, { col => 0, table => 2, text => "D2OVL_KEY_ALPHA_HIGH" }, { col => 1, table => 2, text => "23:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary overlay keyer alpha component upper limit.", }, { col => 3, table => 2, text => "Note: If the overlay component is less than 16 bit, msbs are ", }, { col => undef, table => undef, text => "all zeros." }, { col => undef, table => undef, text => "Secondary overlay keyer alpha component range", }, { col => "heading", table => 3, text => "D2GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL - RW - 32 bits - [GpuF0MMReg:0x6B80]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 236, text => [ { col => 0, table => 0, text => "D2GRPH_COLOR_MATRIX_TRANSFOR" }, { col => 0, table => 0, text => "MATION_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Matrix transformation control for secondary display graphics ", }, { col => 3, table => 0, text => "and cursor pixel. It is used when PIX_TYPE is 1.", }, { col => 3, table => 0, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "Matrix transformation control for secondary display graphics and cursor pixel.", }, { col => "heading", table => 1, text => "D2COLOR_MATRIX_COEF_1_1 - RW - 32 bits - [GpuF0MMReg:0x6B84]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2COLOR_MATRIX_COEF_1_1" }, { col => 1, table => 1, text => "16:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C11 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 1, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2COLOR_MATRIX_SIGN_1_1" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C11 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 2, text => "D2COLOR_MATRIX_COEF_1_2 - RW - 32 bits - [GpuF0MMReg:0x6B88]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2COLOR_MATRIX_COEF_1_2" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C12 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 2, text => "fix-point S0.11(-1.00 to + 0.99)." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2COLOR_MATRIX_SIGN_1_2" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C12 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 3, text => "D2COLOR_MATRIX_COEF_1_3 - RW - 32 bits - [GpuF0MMReg:0x6B8C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2COLOR_MATRIX_COEF_1_3" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C13 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 3, text => "fix-point S0.11(-1.0 to +0.99)." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2COLOR_MATRIX_SIGN_1_3" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C13 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => undef, table => undef, text => "D2COLOR_MATRIX_COEF_1_4 - RW - 32 bits - [GpuF0MMReg:0x6B90]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2COLOR_MATRIX_COEF_1_4" }, { col => undef, table => undef, text => "26:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Combined matrix constant C14 of RGB->YCbCr, contrast ", }, { col => undef, table => undef, text => "and brightness adjustment for secondary display. Format ", }, { col => undef, table => undef, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => undef, table => undef, text => "of 512 offset" }, { col => undef, table => undef, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, ], }, { num => 237, text => [ { col => 0, table => 0, text => "D2COLOR_MATRIX_SIGN_1_4" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C14 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 1, text => "D2COLOR_MATRIX_COEF_2_1 - RW - 32 bits - [GpuF0MMReg:0x6B94]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2COLOR_MATRIX_COEF_2_1" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C21 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 1, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2COLOR_MATRIX_SIGN_2_1" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C21 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 2, text => "D2COLOR_MATRIX_COEF_2_2 - RW - 32 bits - [GpuF0MMReg:0x6B98]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2COLOR_MATRIX_COEF_2_2" }, { col => 1, table => 2, text => "16:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C22 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 2, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2COLOR_MATRIX_SIGN_2_2" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C22 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 3, text => "D2COLOR_MATRIX_COEF_2_3 - RW - 32 bits - [GpuF0MMReg:0x6B9C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2COLOR_MATRIX_COEF_2_3" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C23 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 3, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 3, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2COLOR_MATRIX_SIGN_2_3" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C23 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 4, text => "D2COLOR_MATRIX_COEF_2_4 - RW - 32 bits - [GpuF0MMReg:0x6BA0]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2COLOR_MATRIX_COEF_2_4" }, { col => 1, table => 4, text => "26:8" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Combined matrix constant C24 of RGB->YCbCr, contrast ", }, { col => 3, table => 4, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 4, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => 3, table => 4, text => "of 512 offset" }, { col => 3, table => 4, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 4, text => "D2COLOR_MATRIX_SIGN_2_4" }, { col => 1, table => 4, text => 31 }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C24 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, ], }, { num => 238, text => [ { col => "heading", table => 0, text => "D2COLOR_MATRIX_COEF_3_1 - RW - 32 bits - [GpuF0MMReg:0x6BA4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2COLOR_MATRIX_COEF_3_1" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Combined matrix constant C31 of RGB->YCbCr, contrast ", }, { col => 3, table => 0, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 0, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 0, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "D2COLOR_MATRIX_SIGN_3_1" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C31 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 1, text => "D2COLOR_MATRIX_COEF_3_2 - RW - 32 bits - [GpuF0MMReg:0x6BA8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2COLOR_MATRIX_COEF_3_2" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Combined matrix constant C32 of RGB->YCbCr, contrast ", }, { col => 3, table => 1, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 1, text => "fix-point S0.11(-1.00 to +0.99)." }, { col => 3, table => 1, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 1, text => "D2COLOR_MATRIX_SIGN_3_2" }, { col => 1, table => 1, text => 31 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C32 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 2, text => "D2COLOR_MATRIX_COEF_3_3 - RW - 32 bits - [GpuF0MMReg:0x6BAC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2COLOR_MATRIX_COEF_3_3" }, { col => 1, table => 2, text => "16:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Combined matrix constant C33 of RGB->YCbCr, contrast ", }, { col => 3, table => 2, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 2, text => "fix-point S1.11(-2.00 to +1.99)." }, { col => 3, table => 2, text => "NOTE: Bits 0:4 of this field are hardwired to ZERO.", }, { col => 0, table => 2, text => "D2COLOR_MATRIX_SIGN_3_3" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C33 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, { col => "heading", table => 3, text => "D2COLOR_MATRIX_COEF_3_4 - RW - 32 bits - [GpuF0MMReg:0x6BB0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2COLOR_MATRIX_COEF_3_4" }, { col => 1, table => 3, text => "26:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Combined matrix constant C34 of RGB->YCbCr, contrast ", }, { col => 3, table => 3, text => "and brightness adjustment for secondary display. Format ", }, { col => 3, table => 3, text => "fix-point S11.1(-2048.5 to +2047.5). It includes subtraction ", }, { col => 3, table => 3, text => "of 512 offset" }, { col => 3, table => 3, text => "NOTE: Bits 0:6 of this field are hardwired to ZERO.", }, { col => 0, table => 3, text => "D2COLOR_MATRIX_SIGN_3_4" }, { col => 1, table => 3, text => 31 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Sign bit of combined matrix constant", }, { col => undef, table => undef, text => "Combined matrix constant C34 of RGB->YCbCr, contrast and brightness adjustment for secondary display.", }, ], }, { num => 239, text => [ { col => undef, table => undef, text => "2.7.18" }, { col => undef, table => undef, text => "Secondary Display Subsampling Registers", }, { col => undef, table => undef, text => "2.7.19" }, { col => undef, table => undef, text => " Secondary Display Realtime Overlay Registers", }, { col => "heading", table => 0, text => "D2COLOR_SPACE_CONVERT - RW - 32 bits - [GpuF0MMReg:0x693C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2COLOR_SUBSAMPLE_CRCB_MODE" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Sub-sampling control for secondary display", }, { col => 3, table => 0, text => " 0=do not subsample CrCb(RB) " }, { col => 3, table => 0, text => " 1=subsample CrCb (RB) by using 2 tap average method ", }, { col => 3, table => 0, text => " 2=subsample CrCb (RB) by using 1 tap on even pixel ", }, { col => undef, table => undef, text => " 3=subsample CrCb (RB) by using 1 tap on odd pixel ", }, { col => undef, table => undef, text => "Sub-sampling control for secondary display.", }, { col => "heading", table => 1, text => "D2OVL_RT_SKEWCOMMAND - RW - 32 bits - [GpuF0MMReg:0x6D00]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_RT_CLEAR_GOBBLE_COUNT " }, { col => 0, table => 1, text => "(W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "writing 1 to this bit clear the gobbleCount ", }, { col => 3, table => 1, text => "this bit has higher priority than inc_gobblecount", }, { col => 0, table => 1, text => "D2OVL_RT_INC_GOBBLE_COUNT (W)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "writing 1 to this bit increments the gobbleCount", }, { col => 0, table => 1, text => "D2OVL_RT_CLEAR_SUBMIT_COUNT " }, { col => 0, table => 1, text => "(W)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "writing 1 to this bit clear the submitCount ", }, { col => 3, table => 1, text => "this bit has higher priority than inc_submitcount", }, { col => 0, table => 1, text => "D2OVL_RT_INC_SUBMIT_COUNT (W)" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "writing 1 to this bit increments the submitCount", }, { col => 0, table => 1, text => "D2OVL_RT_GOBBLE_COUNT (R)" }, { col => 1, table => 1, text => "18:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "read only register" }, { col => 3, table => 1, text => "gobble count value which increments with each ", }, { col => 3, table => 1, text => "inc_gobble_count " }, { col => 3, table => 1, text => "and reset with clear_gobble_count commands.", }, { col => 3, table => 1, text => "it wraps around on overflow during increment.", }, { col => 0, table => 1, text => "D2OVL_RT_SUBMIT_COUNT (R)" }, { col => 1, table => 1, text => "22:20" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "read only register" }, { col => 3, table => 1, text => "submit count value which increments with each ", }, { col => 3, table => 1, text => "inc_submit_count " }, { col => 3, table => 1, text => "and reset with clear_submit_count commands.", }, { col => undef, table => undef, text => "it wraps around on overflow during increment.", }, { col => undef, table => undef, text => "reset or increment submit and gobble count", }, { col => "heading", table => 2, text => "D2OVL_RT_SKEWCONTROL - RW - 32 bits - [GpuF0MMReg:0x6D04]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2OVL_RT_CAPS" }, { col => 1, table => 2, text => "2:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "max value in submitCount and gobbleCount", }, { col => 3, table => 2, text => "this is the number of contents buffer - 1", }, { col => 3, table => 2, text => "should reset counters before programming this field", }, { col => 0, table => 2, text => "D2OVL_RT_SKEW_MAX" }, { col => 1, table => 2, text => "6:4" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "max skew allowed between gobbleCount and submitCount", }, { col => undef, table => undef, text => "controls for submit and gobble counts", }, ], }, { num => 240, text => [ { col => "heading", table => 0, text => "D2OVL_RT_BAND_POSITION - RW - 32 bits - [GpuF0MMReg:0x6D08]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2OVL_RT_TOP_SCAN" }, { col => 1, table => 0, text => "13:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "define the top scan line for the next RT (inclusive)", }, { col => 0, table => 0, text => "D2OVL_RT_BTM_SCAN" }, { col => 1, table => 0, text => "29:16" }, { col => undef, table => undef, text => "0x0define the bottom scan line for next RT (exclusive)", }, { col => undef, table => undef, text => "The position of the top and bottom scan line for next RT", }, { col => "heading", table => 1, text => "D2OVL_RT_PROCEED_COND - RW - 32 bits - [GpuF0MMReg:0x6D0C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2OVL_RT_REDUCE_DELAY" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 selects delay optimized scheme" }, { col => 3, table => 1, text => "1 selects basic render behind delay scan scheme", }, { col => 0, table => 1, text => "D2OVL_RT_RT_FLIP" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 selects bandSync to be exposed to CP" }, { col => 3, table => 1, text => "1 selects frameSync to be exposed to CP" }, { col => 0, table => 1, text => "D2OVL_RT_PROCEED_ON_EOF_DISA" }, { col => 0, table => 1, text => "BLE" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 enables unfinished bands to pass bandSync on EOF ", }, { col => 3, table => 1, text => "(valid only in basic scheme)" }, { col => 3, table => 1, text => "1 disables this feature" }, { col => 0, table => 1, text => "D2OVL_RT_WITH_HELD_ON_SOF" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 disables proceedOnEOF on next frameSync", }, { col => 3, table => 1, text => "1 disables proceedOnEOF on next SOF" }, { col => 0, table => 1, text => "D2OVL_RT_CLEAR_GOBBLE_GO (W)" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This bit clear gobbleGo " }, { col => 3, table => 1, text => "disable another frame submit before next flip (ignored in ", }, { col => 3, table => 1, text => "basic scheme)" }, { col => 0, table => 1, text => "D2OVL_RT_TEAR_PROOF_HEIGHT" }, { col => 1, table => 1, text => "29:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "define the number of scan lines above topscan.", }, { col => undef, table => undef, text => "if display starts reading from there, RT should wait", }, { col => undef, table => undef, text => "select RT flip proceed condition", }, { col => undef, table => undef, text => "D2OVL_RT_STAT - RW - 32 bits - [GpuF0MMReg:0x6D10]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2OVL_RT_FIP_PROCEED_ACK (W)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The sticky bit clears the FIP_PROCEED FLAG flag when ", }, { col => undef, table => undef, text => "written" }, { col => undef, table => undef, text => "D2OVL_RT_FRAME_SYNC_ACK (W)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The sticky bit clears the RT_FRAME_SYNC flag when ", }, { col => undef, table => undef, text => "written" }, { col => undef, table => undef, text => "D2OVL_RT_OVL_START_ACK (W)" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "The sticky bit clears the OVL_START FLAG flag when ", }, { col => undef, table => undef, text => "written" }, { col => undef, table => undef, text => "D2OVL_RT_BAND_INVISIBLE (R)" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that overlay scanning in invisble region", }, { col => undef, table => undef, text => "D2OVL_RT_BAND_SYNC (R)" }, { col => undef, table => undef, text => 9 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that overlay bottom scan is less the line ", }, { col => undef, table => undef, text => "counter" }, { col => undef, table => undef, text => "D2OVL_RT_EOF_PRPCEED (R)" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that overlay is ended. Set at eof and ", }, { col => undef, table => undef, text => "reset at overlay start" }, { col => undef, table => undef, text => "D2OVL_RT_FIP_PROCEED (R)" }, { col => undef, table => undef, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Sticky debug bit that set when RT_FLIP_PROCEED signal ", }, { col => undef, table => undef, text => "asserted." }, { col => undef, table => undef, text => "D2OVL_RT_FRAME_SYNC (R)" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Sticky debug bit indicating that overlay start set and a new ", }, { col => undef, table => undef, text => "submission occured" }, { col => undef, table => undef, text => "D2OVL_RT_GOBBLE_GO (R)" }, { col => undef, table => undef, text => 13 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit that set on frame_sync and clear at gobbleclr", }, { col => undef, table => undef, text => "D2OVL_RT_NEW_SUBMIT (R)" }, { col => undef, table => undef, text => 14 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating a new submission occurred", }, { col => undef, table => undef, text => "D2OVL_RT_OVL_START (R)" }, { col => undef, table => undef, text => 15 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that line buffer detects start of overlay ", }, { col => undef, table => undef, text => "being accessed" }, { col => undef, table => undef, text => "D2OVL_RT_OVL_ENDED (R)" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that line buffer detects that the end of ", }, { col => undef, table => undef, text => "overlay being accessed" }, { col => undef, table => undef, text => "D2OVL_RT_SAFE_ZONE (R)" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug bit indicating that overlay is scaning in safe zone", }, ], }, { num => 241, text => [ { col => undef, table => undef, text => "2.7.20" }, { col => undef, table => undef, text => "Secondary Display Hardware Cursor Registers", }, { col => 0, table => 0, text => "D2OVL_RT_SWITCH_REGIONS (R)" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug bit showing the postion of scan region relative to ", }, { col => 3, table => 0, text => "display" }, { col => 0, table => 0, text => "D2OVL_SKEW_MAX_REACHED (R)" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug bit indicating that line buffer detected maximum ", }, { col => 3, table => 0, text => "skew reached" }, { col => 0, table => 0, text => "D2OVL_LINE_COUNTER (R)" }, { col => 1, table => 0, text => "31:20" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "debug bit showing display line counter value", }, { col => undef, table => undef, text => "Status Bits" }, { col => "heading", table => 1, text => "D2CUR_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6C00]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CURSOR_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware cursor enabled.", }, { col => 3, table => 1, text => " 0=disable " }, { col => 3, table => 1, text => " 1=enable " }, { col => 0, table => 1, text => "D2CURSOR_MODE" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware cursor mode." }, { col => 3, table => 1, text => "For 2bpp mode, each line of cursor data is stored in ", }, { col => 3, table => 1, text => "memory as 16 bits of AND data followed by 16 bits XOR ", }, { col => 3, table => 1, text => "data." }, { col => 3, table => 1, text => "For color AND/XOR mode, each pixel is stored sequentially ", }, { col => 3, table => 1, text => "in memory as 32bits each in aRGB8888 format with bit 31 ", }, { col => 3, table => 1, text => "of each DWord being the AND bit." }, { col => 3, table => 1, text => "For the color alpha modes the format is also 32bpp ", }, { col => 3, table => 1, text => "aRGB8888 with all 8 bits of the alpha being used.All HW ", }, { col => 3, table => 1, text => "cursor lines must be 64 pixels wide and all lines must be ", }, { col => 3, table => 1, text => "stored sequentially in memory." }, { col => 3, table => 1, text => " 0=Mono (2bpp) " }, { col => 3, table => 1, text => " 1=Color 24bpp + 1 bit AND (32bpp) " }, { col => 3, table => 1, text => " 2=Color 24bpp + 8 bit alpha (32bpp) premultiplied alpha ", }, { col => 3, table => 1, text => " 3=Color 24bpp + 8 bit alpha (32bpp)unmultiplied alpha ", }, { col => 0, table => 1, text => "D2CURSOR_2X_MAGNIFY" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware cursor 2x2 magnification.", }, { col => 3, table => 1, text => " 0=no 2x2 magnification " }, { col => 3, table => 1, text => " 1=2x2 magnification in horizontal and vertical direction ", }, { col => 0, table => 1, text => "D2CURSOR_FORCE_MC_ON" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "When set, if the incoming data is in D1 cursor region, ", }, { col => 3, table => 1, text => "DCP_LB_cursor1_allow_stutter is set. This field in this ", }, { col => undef, table => undef, text => "double bufferred register is not double buffered.", }, { col => undef, table => undef, text => "Secondary display hardware control", }, { col => "heading", table => 2, text => "D2CUR_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6C08]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CURSOR_SURFACE_ADDRESS" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary display hardware cursor surface base address ", }, { col => 3, table => 2, text => "in byte. It is 4K byte aligned." }, { col => undef, table => undef, text => "NOTE: Bits 0:11 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary display hardware cursor surface base address.", }, { col => undef, table => undef, text => "D2CUR_SIZE - RW - 32 bits - [GpuF0MMReg:0x6C10]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CURSOR_HEIGHT" }, { col => undef, table => undef, text => "5:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware cursor height minus 1.", }, ], }, { num => 242, text => [ { col => 0, table => 0, text => "D2CURSOR_WIDTH" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware cursor width minus 1.", }, { col => undef, table => undef, text => "Secondary display hardware size" }, { col => "heading", table => 1, text => "D2CUR_POSITION - RW - 32 bits - [GpuF0MMReg:0x6C14]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CURSOR_Y_POSITION" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware cursor X coordinate at the hot ", }, { col => 3, table => 1, text => "spot relative to the desktop coordinates.", }, { col => 0, table => 1, text => "D2CURSOR_X_POSITION" }, { col => 1, table => 1, text => "28:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware cursor X coordinate at the hot ", }, { col => undef, table => undef, text => "spot relative to the desktop coordinates.", }, { col => undef, table => undef, text => "Secondary display hardware cursor position", }, { col => "heading", table => 2, text => "D2CUR_HOT_SPOT - RW - 32 bits - [GpuF0MMReg:0x6C18]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CURSOR_HOT_SPOT_Y" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary display hardware cursor hot spot X length ", }, { col => 3, table => 2, text => "relative to the top left corner." }, { col => 0, table => 2, text => "D2CURSOR_HOT_SPOT_X" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary display hardware cursor hot spot Y length ", }, { col => undef, table => undef, text => "relative to the top left corner.", }, { col => undef, table => undef, text => "Secondary display hardware cursor hot spot position", }, { col => "heading", table => 3, text => "D2CUR_COLOR1 - RW - 32 bits - [GpuF0MMReg:0x6C1C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CUR_COLOR1_BLUE" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary display hardware cursor blue component of ", }, { col => 3, table => 3, text => "color 1." }, { col => 0, table => 3, text => "D2CUR_COLOR1_GREEN" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary display hardware cursor green component of ", }, { col => 3, table => 3, text => "color 1." }, { col => 0, table => 3, text => "D2CUR_COLOR1_RED" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary display hardware cursor red component of color ", }, { col => undef, table => undef, text => "1." }, { col => undef, table => undef, text => "Secondary display hardware cursor color 1.", }, { col => "heading", table => 4, text => "D2CUR_COLOR2 - RW - 32 bits - [GpuF0MMReg:0x6C20]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "D2CUR_COLOR2_BLUE" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Secondary display hardware cursor blue component of ", }, { col => 3, table => 4, text => "color 2." }, { col => 0, table => 4, text => "D2CUR_COLOR2_GREEN" }, { col => 1, table => 4, text => "15:8" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Secondary display hardware cursor green component of ", }, { col => 3, table => 4, text => "color 2." }, { col => 0, table => 4, text => "D2CUR_COLOR2_RED" }, { col => 1, table => 4, text => "23:16" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Secondary display hardware cursor red component of color ", }, { col => undef, table => undef, text => "2." }, { col => undef, table => undef, text => "Secondary display hardware cursor color 2.", }, ], }, { num => 243, text => [ { col => undef, table => undef, text => "2.7.21" }, { col => undef, table => undef, text => "Secondary Display Hardware Icon Registers", }, { col => "heading", table => 0, text => "D2CUR_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6C24]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CURSOR_UPDATE_PENDING (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware cursor update pending status. ", }, { col => 3, table => 0, text => "It is set to 1 after a host write to cursor double buffer ", }, { col => 3, table => 0, text => "register. It is cleared after double buffering is done. The ", }, { col => 3, table => 0, text => "double buffering occurs when " }, { col => 3, table => 0, text => "D2CURSOR_UPDATE_PENDING = 1 and " }, { col => 3, table => 0, text => "D2CURSOR_UPDATE_LOCK = 0 and V_UPDATE = 1.", }, { col => 3, table => 0, text => "If CRTC2 is disabled, the registers will be updated instantly.", }, { col => 3, table => 0, text => "The D2CUR double buffer registers are:" }, { col => 3, table => 0, text => "D2CURSOR_EN" }, { col => 3, table => 0, text => "D2CURSOR_MODE" }, { col => 3, table => 0, text => "D2CURSOR_2X_MAGNIFY" }, { col => 3, table => 0, text => "D2CURSOR_SURFACE_ADDRESS" }, { col => 3, table => 0, text => "D2CURSOR_HEIGHT" }, { col => 3, table => 0, text => "D2CURSOR_WIDTH" }, { col => 3, table => 0, text => "D2CURSOR_X_POSITION" }, { col => 3, table => 0, text => "D2CURSOR_Y_POSITION" }, { col => 3, table => 0, text => "D2CURSOR_HOT_SPOT_X" }, { col => 3, table => 0, text => "D2CURSOR_HOT_SPOT_Y" }, { col => 3, table => 0, text => " 0=No update pending " }, { col => 3, table => 0, text => " 1=Update pending " }, { col => 0, table => 0, text => "D2CURSOR_UPDATE_TAKEN (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware cursor update taken status. It ", }, { col => 3, table => 0, text => "is set to 1 when double buffering occurs and cleared when ", }, { col => 3, table => 0, text => "V_UPDATE = 0" }, { col => 0, table => 0, text => "D2CURSOR_UPDATE_LOCK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware cursor update lock control.", }, { col => 3, table => 0, text => " 0=Unlocked " }, { col => 3, table => 0, text => " 1=Locked " }, { col => 0, table => 0, text => "D2CURSOR_DISABLE_MULTIPLE_UPD" }, { col => 0, table => 0, text => "ATE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=D2CURSOR registers can be updated multiple times in ", }, { col => 3, table => 0, text => "one V_UPDATE period " }, { col => 3, table => 0, text => " 1=D2CURSOR registers can only be updated once in one ", }, { col => 3, table => 0, text => "V_UPDATE period " }, { col => "heading", table => 1, text => "D2ICON_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6C40]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2ICON_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware icon enable." }, { col => 3, table => 1, text => " 0=disable " }, { col => 3, table => 1, text => " 1=enable " }, { col => 0, table => 1, text => "D2ICON_2X_MAGNIFY" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware icon 2x2 magnification.", }, { col => 3, table => 1, text => " 0=no 2x2 magnification " }, { col => 3, table => 1, text => " 1=2x2 magnification in horizontal and vertical direction ", }, { col => 0, table => 1, text => "D2ICON_FORCE_MC_ON" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "When set, if the incoming data is in D1 icon region, ", }, { col => 3, table => 1, text => "DCP_LB_icon2_allow_stutter is set. This field in this double ", }, { col => undef, table => undef, text => "bufferred register is not double buffered.", }, { col => undef, table => undef, text => "Secondary display hardware icon control.", }, ], }, { num => 244, text => [ { col => "heading", table => 0, text => "D2ICON_SURFACE_ADDRESS - RW - 32 bits - [GpuF0MMReg:0x6C48]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2ICON_SURFACE_ADDRESS" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware icon surface base address in ", }, { col => 3, table => 0, text => "byte. It is 4K byte aligned." }, { col => undef, table => undef, text => "NOTE: Bits 0:11 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Secondary display hardware icon surface base address.", }, { col => "heading", table => 1, text => "D2ICON_SIZE - RW - 32 bits - [GpuF0MMReg:0x6C50]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2ICON_HEIGHT" }, { col => 1, table => 1, text => "6:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Secondary display hardware icon height minus 1.", }, { col => 0, table => 1, text => "D2ICON_WIDTH" }, { col => 1, table => 1, text => "22:16" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon width minus 1.", }, { col => undef, table => undef, text => "Secondary display hardware icon size.", }, { col => "heading", table => 2, text => "D2ICON_START_POSITION - RW - 32 bits - [GpuF0MMReg:0x6C54]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2ICON_Y_POSITION" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary display hardware icon Y start coordinate related ", }, { col => 3, table => 2, text => "to the desktop coordinates." }, { col => 3, table => 2, text => "Note: Icon can not be off the top and off the left edge of the ", }, { col => 3, table => 2, text => "display surface. But can be off the bottom and off the right ", }, { col => 3, table => 2, text => "edge of the display." }, { col => 0, table => 2, text => "D2ICON_X_POSITION" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Secondary display hardware icon X start coordinate relative ", }, { col => 3, table => 2, text => "to the desktop coordinates." }, { col => 3, table => 2, text => "Note: Icon can not be off the top and off the left edge of the ", }, { col => 3, table => 2, text => "display surface. But can be off the bottom and off the right ", }, { col => undef, table => undef, text => "edge of the display." }, { col => undef, table => undef, text => "Secondary display hardware icon position", }, { col => "heading", table => 3, text => "D2ICON_COLOR1 - RW - 32 bits - [GpuF0MMReg:0x6C58]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2ICON_COLOR1_BLUE" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary display hardware icon blue component of color ", }, { col => 3, table => 3, text => "1." }, { col => 0, table => 3, text => "D2ICON_COLOR1_GREEN" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Secondary display hardware icon green component of color ", }, { col => 3, table => 3, text => "1." }, { col => 0, table => 3, text => "D2ICON_COLOR1_RED" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon red component of color 1.", }, { col => undef, table => undef, text => "Secondary display hardware icon color 1.", }, { col => "heading", table => 4, text => "D2ICON_COLOR2 - RW - 32 bits - [GpuF0MMReg:0x6C5C]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 245, text => [ { col => undef, table => undef, text => "2.7.22" }, { col => undef, table => undef, text => "Secondary Display Multi-VPU Control Registers", }, { col => 0, table => 0, text => "D2ICON_COLOR2_BLUE" }, { col => 1, table => 0, text => "7:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware icon blue component of color ", }, { col => 3, table => 0, text => "2." }, { col => 0, table => 0, text => "D2ICON_COLOR2_GREEN" }, { col => 1, table => 0, text => "15:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary display hardware icon green component of color ", }, { col => 3, table => 0, text => "2." }, { col => 0, table => 0, text => "D2ICON_COLOR2_RED" }, { col => 1, table => 0, text => "23:16" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon red component of color 2.", }, { col => undef, table => undef, text => "Secondary display hardware icon color 2.", }, { col => undef, table => undef, text => "D2ICON_UPDATE - RW - 32 bits - [GpuF0MMReg:0x6C60]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2ICON_UPDATE_PENDING (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon update Pending status. It ", }, { col => undef, table => undef, text => "is set to 1 after a host write to icon double buffer register. It ", }, { col => undef, table => undef, text => "is cleared after double buffering is done. The double ", }, { col => undef, table => undef, text => "buffering occurs when D2ICON_UPDATE_PENDING = 1 ", }, { col => undef, table => undef, text => "and D2ICON_UPDATE_LOCK = 0 and V_UPDATE = 1.", }, { col => undef, table => undef, text => "If CRTC2 is disabled, the registers will be updated instantly.", }, { col => undef, table => undef, text => "D2IOCN double buffer registers include :", }, { col => undef, table => undef, text => "D2ICON_ENABLE" }, { col => undef, table => undef, text => "D2ICON_2X_MAGNIFY" }, { col => undef, table => undef, text => "D2ICON_SURFACE_ADDRESS" }, { col => undef, table => undef, text => "D2ICON_HEIGHT" }, { col => undef, table => undef, text => "D2ICON_WIDTH" }, { col => undef, table => undef, text => "D2ICON_Y_POSITION" }, { col => undef, table => undef, text => "D2ICON_X_POSITION" }, { col => undef, table => undef, text => " 0=No update pending " }, { col => undef, table => undef, text => " 1=Update pending " }, { col => undef, table => undef, text => "D2ICON_UPDATE_TAKEN (R)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon update Taken status. It is ", }, { col => undef, table => undef, text => "set to 1 when double buffering occurs and cleared when ", }, { col => undef, table => undef, text => "V_UPDATE = 0" }, { col => undef, table => undef, text => "D2ICON_UPDATE_LOCK" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Secondary display hardware icon update lock control.", }, { col => undef, table => undef, text => " 0=Unlocked " }, { col => undef, table => undef, text => " 1=Locked " }, { col => undef, table => undef, text => "D2ICON_DISABLE_MULTIPLE_UPDATE" }, { col => undef, table => undef, text => 24 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=D2ICON registers can be updated multiple times in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => " 1=D2ICON registers can only be updated once in one ", }, { col => undef, table => undef, text => "V_UPDATE period " }, { col => undef, table => undef, text => "Secondary display hardware icon update control", }, { col => "heading", table => 1, text => "D2CRTC_MVP_STATUS - RW - 32 bits - [GpuF0MMReg:0x685C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_FLIP_NOW_OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether flip_now has occurred. A sticky bit.", }, { col => 3, table => 1, text => "0 = has not occurred" }, { col => 3, table => 1, text => "1 = has occurred" }, { col => 0, table => 1, text => "D2CRTC_FLIP_NOW_CLEAR (W)" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Clears the sticky bit D2CRTC_FLIP_NOW_OCCURRED ", }, { col => undef, table => undef, text => "when written with '1'" }, { col => undef, table => undef, text => "Reports status for MVP flipping in CRTC2", }, ], }, { num => 246, text => [ { col => undef, table => undef, text => "2.7.23" }, { col => undef, table => undef, text => "Display Look Up Table Control Registers", }, { col => "heading", table => 0, text => "D2_MVP_AFR_FLIP_MODE - RW - 32 bits - [GpuF0MMReg:0x65E8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2_MVP_AFR_FLIP_MODE" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "10 - real flip; 11 - dummy flip" }, { col => undef, table => undef, text => "S/W writes to this register in AFR mode for display 2 page flip", }, { col => "heading", table => 1, text => "D2_MVP_AFR_FLIP_FIFO_CNTL - RW - 32 bits - [GpuF0MMReg:0x65EC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2_MVP_AFR_FLIP_FIFO_NUM_ENTRI" }, { col => 0, table => 1, text => "ES (R)" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "number of valid entries in the AFR flip FIFO", }, { col => 0, table => 1, text => "D2_MVP_AFR_FLIP_FIFO_RESET" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "reset the AFR flip FIFO" }, { col => 0, table => 1, text => "D2_MVP_AFR_FLIP_FIFO_RESET_FLA" }, { col => 0, table => 1, text => "G (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "sticky bit of the AFR flip fifo reset status", }, { col => 0, table => 1, text => "D2_MVP_AFR_FLIP_FIFO_RESET_ACK" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "clear the DC_LB_MVP_AFR_FLIP_RESET_FLAG register ", }, { col => undef, table => undef, text => "bit" }, { col => undef, table => undef, text => "This register controls AFR Flip FIFO in display 2", }, { col => "heading", table => 2, text => "D2_MVP_FLIP_LINE_NUM_INSERT - RW - 32 bits - [GpuF0MMReg:0x65F0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2_MVP_FLIP_LINE_NUM_INSERT_MO" }, { col => 0, table => 2, text => "DE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => "00 - no insertion, 0 is appended; 01 - debug: insert ", }, { col => 3, table => 2, text => "D2_MVP_FLIP_LINE_NUM_INSERT regiser value; 10 - ", }, { col => 3, table => 2, text => "normal Hsync mode, insert the sum of LB line number + ", }, { col => 3, table => 2, text => "DC_LB_MVP_FLIP_LINE_NUM_OFFSET" }, { col => 0, table => 2, text => "D2_MVP_FLIP_LINE_NUM_INSERT" }, { col => 1, table => 2, text => "21:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "used for debug purpose, this is what will be the line number ", }, { col => 3, table => 2, text => "carried to downstream GPUs if " }, { col => 3, table => 2, text => "D2_MVP_FLIP_LINE_NUM_INSERT_EN is set" }, { col => 0, table => 2, text => "D2_MVP_FLIP_LINE_NUM_OFFSET" }, { col => 1, table => 2, text => "29:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "used in normal HSYNC flipping operation. this is the ", }, { col => 3, table => 2, text => "number added to the current LB (desktop) line number for ", }, { col => 3, table => 2, text => "carrying to the downstream GPUs" }, { col => 0, table => 2, text => "D2_MVP_FLIP_AUTO_ENABLE" }, { col => 1, table => 2, text => 30 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Enabling automatic AFR/SFR flipping for display 2", }, { col => undef, table => undef, text => "This register controls line number insertion for the Hsync flipping mode in display 2", }, { col => "heading", table => 3, text => "DC_LUT_RW_SELECT - RW - 32 bits - [GpuF0MMReg:0x6480]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 247, text => [ { col => 0, table => 0, text => "DC_LUT_RW_SELECT" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "LUT host Read/write selection." }, { col => 3, table => 0, text => " 0=Host reads/writes to the LUT access the lower half of ", }, { col => 3, table => 0, text => "the LUT " }, { col => 3, table => 0, text => " 1=Host reads/writes to the LUT access the upper half of ", }, { col => undef, table => undef, text => "the LUT " }, { col => undef, table => undef, text => "LUT host Read/write selection." }, { col => "heading", table => 1, text => "DC_LUT_RW_MODE - RW - 32 bits - [GpuF0MMReg:0x6484]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_LUT_RW_MODE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "LUT host read/write mode." }, { col => 3, table => 1, text => " 0=Host reads/writes to the LUT in 256-entry table mode ", }, { col => 3, table => 1, text => " 1=Host reads/writes to the LUT in piece wise linear (PWL) ", }, { col => undef, table => undef, text => "mode " }, { col => undef, table => undef, text => "LUT host read/write mode." }, { col => "heading", table => 2, text => "DC_LUT_RW_INDEX - RW - 32 bits - [GpuF0MMReg:0x6488]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_LUT_RW_INDEX" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "LUT index for host read/write." }, { col => 3, table => 2, text => "In 256-entry table mode: LUT_ADDR[6:0] = INDEX[7:1]. ", }, { col => 3, table => 2, text => "INDEX[0] is used to select LUT lower or upper 10 bits.", }, { col => 3, table => 2, text => "In piece wise linear (PWL) mode: LUT_ADDR[6:0] = ", }, { col => undef, table => undef, text => "INDEX[6:0]. INDEX[7] is not used", }, { col => undef, table => undef, text => "LUT index for host read/write." }, { col => "heading", table => 3, text => "DC_LUT_SEQ_COLOR - RW - 32 bits - [GpuF0MMReg:0x648C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_LUT_SEQ_COLOR" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Sequential 10-bit R,G,B host read/write for LUT 256-entry ", }, { col => 3, table => 3, text => "table mode. After reset or writing DC_LUT_RW_INDEX ", }, { col => 3, table => 3, text => "register, first DC_LUT_SEQ_COLOR access is for red ", }, { col => 3, table => 3, text => "component, the second one is for green component and the ", }, { col => 3, table => 3, text => "third one is for blue component. Always access this register ", }, { col => 3, table => 3, text => "three times for one LUT entry in LUT 256-entry table mode. ", }, { col => 3, table => 3, text => "The LUT index is increased by 1 when LUT blue data is ", }, { col => 3, table => 3, text => "accessed. This allow you to access the next LUT entry ", }, { col => 3, table => 3, text => "without programming DC_LUT_RW_INDEX again.", }, { col => undef, table => undef, text => "NOTE: Bits 0:5 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Sequential 10-bit R,G,B host read/write for LUT 256-entry table mode.", }, { col => "heading", table => 4, text => "DC_LUT_PWL_DATA - RW - 32 bits - [GpuF0MMReg:0x6490]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 248, text => [ { col => 0, table => 0, text => "DC_LUT_BASE" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Linear interpolation of base value for host read/write.", }, { col => 3, table => 0, text => "NOTE: Bits 0:5 of this field are hardwired to ZERO.", }, { col => 0, table => 0, text => "DC_LUT_DELTA" }, { col => 1, table => 0, text => "31:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Linear interpolation of delta value for host read/write. The ", }, { col => 3, table => 0, text => "LUT index is increased by 1 when register ", }, { col => 3, table => 0, text => "DC_LUT_PWL_DATA is accessed." }, { col => undef, table => undef, text => "NOTE: Bits 0:5 of this field are hardwired to ZERO.", }, { col => undef, table => undef, text => "Linear interpolation of base and delta host read/write for LUT PWL mode", }, { col => "heading", table => 1, text => "DC_LUT_30_COLOR - RW - 32 bits - [GpuF0MMReg:0x6494]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_LUT_COLOR_10_BLUE" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "10-bit blue value for host read/write. The LUT index is ", }, { col => 3, table => 1, text => "increased by 1 when register DC_LUT_30_COLOR is ", }, { col => 3, table => 1, text => "accessed." }, { col => 0, table => 1, text => "DC_LUT_COLOR_10_GREEN" }, { col => 1, table => 1, text => "19:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "10-bit green value for host read/write." }, { col => 0, table => 1, text => "DC_LUT_COLOR_10_RED" }, { col => 1, table => 1, text => "29:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "10-bit red value for host read/write.", }, { col => undef, table => undef, text => "Host read/write LUT R,G,B value for LUT 256-entry table mode", }, { col => "heading", table => 2, text => "DC_LUT_READ_PIPE_SELECT - RW - 32 bits - [GpuF0MMReg:0x6498]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_LUT_READ_PIPE_SELECT" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "LUT pipe selection for host read." }, { col => 3, table => 2, text => " 0=Host read select pipe 0 " }, { col => undef, table => undef, text => " 1=Host read select pipe 1 " }, { col => undef, table => undef, text => "LUT pipe selection for host read.", }, { col => "heading", table => 3, text => "DC_LUT_WRITE_EN_MASK - RW - 32 bits - [GpuF0MMReg:0x649C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_LUT_WRITE_EN_MASK" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x3f" }, { col => 3, table => 3, text => "Look-up table macro write enable mask for host write.", }, { col => 3, table => 3, text => "For each bit" }, { col => 3, table => 3, text => " 0 - host write disable " }, { col => 3, table => 3, text => " 1 - host write enable" }, { col => 3, table => 3, text => " Bit[0] - For pipe 1, B macro" }, { col => 3, table => 3, text => "Bit[1] - For pipe 1, G macro" }, { col => 3, table => 3, text => "Bit[2] - For pipe 1, R macro" }, { col => 3, table => 3, text => "Bit[3] - For pipe 0, B macro" }, { col => 3, table => 3, text => "Bit[4] - For pipe 0, G macro" }, { col => undef, table => undef, text => "Bit[5] - For pipe 0, R macro" }, { col => undef, table => undef, text => "Look-up table macro write enable mask for host write.", }, { col => "heading", table => 4, text => "DC_LUT_AUTOFILL - RW - 32 bits - [GpuF0MMReg:0x64A0]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 249, text => [ { col => undef, table => undef, text => "2.7.24" }, { col => undef, table => undef, text => "Display Controller Look Up Table A Registers", }, { col => 0, table => 0, text => "DC_LUT_AUTOFILL (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable LUT autofill when 1 is written into this field", }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Start LUT autofill " }, { col => 0, table => 0, text => "DC_LUT_AUTOFILL_DONE (R)" }, { col => 1, table => 0, text => "10x0" }, { col => 3, table => 0, text => "LUT autofill is done" }, { col => 3, table => 0, text => " 0=LUT autofill is not completed " }, { col => undef, table => undef, text => " 1=LUT autofill is done " }, { col => undef, table => undef, text => "LUT autofill control" }, { col => undef, table => undef, text => "DC_LUTA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x64C0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DC_LUTA_INC_B" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Exponent of Power-of-two of blue data increment of LUTA ", }, { col => undef, table => undef, text => "palette." }, { col => undef, table => undef, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => undef, table => undef, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => undef, table => undef, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => undef, table => undef, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => undef, table => undef, text => "base and delta values." }, { col => undef, table => undef, text => "LUT_INDEX = PIX_DATA[INC+6:INC].", }, { col => undef, table => undef, text => "Mult = PIX_DATA[INC-1:0]." }, { col => undef, table => undef, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => undef, table => undef, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => undef, table => undef, text => "Output = Base + (Mult * Delta) / increment", }, { col => undef, table => undef, text => " 0=Blue data increment = N/A " }, { col => undef, table => undef, text => " 1=Blue data increment = 2 " }, { col => undef, table => undef, text => " 2=Blue data increment = 4 " }, { col => undef, table => undef, text => " 3=Blue data increment = 8 " }, { col => undef, table => undef, text => " 4=Blue data increment = 16 " }, { col => undef, table => undef, text => " 5=Blue data increment = 32 " }, { col => undef, table => undef, text => " 6=Blue data increment = 64 " }, { col => undef, table => undef, text => " 7=Blue data increment = 128 " }, { col => undef, table => undef, text => " 8=Blue data increment = 256 " }, { col => undef, table => undef, text => " 9=Blue data increment = 512 " }, { col => undef, table => undef, text => "DC_LUTA_DATA_B_SIGNED_EN" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Frame buffer blue data signed enable for look-up table A.", }, { col => undef, table => undef, text => " 0=Blue data is unsigned " }, { col => undef, table => undef, text => " 1=Blue data is signed " }, { col => undef, table => undef, text => "DC_LUTA_DATA_B_FLOAT_POINT_EN" }, { col => undef, table => undef, text => 5 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Frame buffer blue data float point enable for look-up table ", }, { col => undef, table => undef, text => "A." }, { col => undef, table => undef, text => " 0=Blue data is fix point " }, { col => undef, table => undef, text => " 1=Blue data is float point " }, ], }, { num => 250, text => [ { col => 0, table => 0, text => "DC_LUTA_INC_G" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Exponent of Power-of-two of green data increment of LUTA ", }, { col => 3, table => 0, text => "palette." }, { col => 3, table => 0, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => 3, table => 0, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => 3, table => 0, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => 3, table => 0, text => "base and delta values." }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[INC+6:INC]." }, { col => 3, table => 0, text => "Mult = PIX_DATA[INC-1:0]." }, { col => 3, table => 0, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => 3, table => 0, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => 3, table => 0, text => "Output = Base + (Mult * Delta) / increment", }, { col => 3, table => 0, text => " 0=Green data increment = N/A " }, { col => 3, table => 0, text => " 1=Green data increment = 2 " }, { col => 3, table => 0, text => " 2=Green data increment = 4 " }, { col => 3, table => 0, text => " 3=Green data increment = 8 " }, { col => 3, table => 0, text => " 4=Green data increment = 16 " }, { col => 3, table => 0, text => " 5=Green data increment = 32 " }, { col => 3, table => 0, text => " 6=Green data increment = 64 " }, { col => 3, table => 0, text => " 7=Green data increment = 128 " }, { col => 3, table => 0, text => " 8=Green data increment = 256 " }, { col => 3, table => 0, text => " 9=Green data increment = 512 " }, { col => 0, table => 0, text => "DC_LUTA_DATA_G_SIGNED_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer green data signed enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Green data is unsigned " }, { col => 3, table => 0, text => " 1=Green data is signed " }, { col => 0, table => 0, text => "DC_LUTA_DATA_G_FLOAT_POINT_EN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer green data float point enable for look-up table ", }, { col => 3, table => 0, text => "A." }, { col => 3, table => 0, text => " 0=Green data is fix point " }, { col => 3, table => 0, text => " 1=Green data is float point " }, { col => 0, table => 0, text => "DC_LUTA_INC_R" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Exponent of Power-of-two of red data increment of LUTA ", }, { col => 3, table => 0, text => "palette." }, { col => 3, table => 0, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => 3, table => 0, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => 3, table => 0, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => 3, table => 0, text => "base and delta values." }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[INC+6:INC]." }, { col => 3, table => 0, text => "Mult = PIX_DATA[INC-1:0]." }, { col => 3, table => 0, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => 3, table => 0, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => 3, table => 0, text => "Output = Base + (Mult * Delta) / increment", }, { col => 3, table => 0, text => " 0=Red data increment = N/A " }, { col => 3, table => 0, text => " 1=Red data increment = 2 " }, { col => 3, table => 0, text => " 2=Red data increment = 4 " }, { col => 3, table => 0, text => " 3=Red data increment = 8 " }, { col => 3, table => 0, text => " 4=Red data increment = 16 " }, { col => 3, table => 0, text => " 5=Red data increment = 32 " }, { col => 3, table => 0, text => " 6=Red data increment = 64 " }, { col => 3, table => 0, text => " 7=Red data increment = 128 " }, { col => 3, table => 0, text => " 8=Red data increment = 256 " }, { col => 3, table => 0, text => " 9=Red data increment = 512 " }, { col => 0, table => 0, text => "DC_LUTA_DATA_R_SIGNED_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer red data signed enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Red data is unsigned " }, { col => 3, table => 0, text => " 1=Red data is signed " }, { col => 0, table => 0, text => "DC_LUTA_DATA_R_FLOAT_POINT_EN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer red data float point enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Red data is fix point " }, { col => undef, table => undef, text => " 1=Red data is float point " }, { col => undef, table => undef, text => "LUTA mode control" }, ], }, { num => 251, text => [ { col => "heading", table => 0, text => "DC_LUTA_BLACK_OFFSET_BLUE - RW - 32 bits - [GpuF0MMReg:0x64C4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_LUTA_BLACK_OFFSET_BLUE" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of blue component for LUTA.", }, { col => undef, table => undef, text => "Black value offset of blue component for LUTA.", }, { col => "heading", table => 1, text => "DC_LUTA_BLACK_OFFSET_GREEN - RW - 32 bits - [GpuF0MMReg:0x64C8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_LUTA_BLACK_OFFSET_GREEN" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of green component for LUTA.", }, { col => undef, table => undef, text => "Black value offset of green component for LUTA.", }, { col => "heading", table => 2, text => "DC_LUTA_BLACK_OFFSET_RED - RW - 32 bits - [GpuF0MMReg:0x64CC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_LUTA_BLACK_OFFSET_RED" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of red component for LUTA.", }, { col => undef, table => undef, text => "Black value offset of red component for LUTA.", }, { col => "heading", table => 3, text => "DC_LUTA_WHITE_OFFSET_BLUE - RW - 32 bits - [GpuF0MMReg:0x64D0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_LUTA_WHITE_OFFSET_BLUE" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of blue component for LUTA", }, { col => undef, table => undef, text => "White value offset of blue component for LUTA.", }, { col => "heading", table => 4, text => "DC_LUTA_WHITE_OFFSET_GREEN - RW - 32 bits - [GpuF0MMReg:0x64D4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DC_LUTA_WHITE_OFFSET_GREEN" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of green component for LUTA", }, { col => undef, table => undef, text => "White value offset of green component for LUTA", }, { col => "heading", table => 5, text => "DC_LUTA_WHITE_OFFSET_RED - RW - 32 bits - [GpuF0MMReg:0x64D8]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "DC_LUTA_WHITE_OFFSET_RED" }, { col => 1, table => 5, text => "15:0" }, { col => 2, table => 5, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of red component for LUTA", }, { col => undef, table => undef, text => "White value offset of red component for LUTA", }, ], }, { num => 252, text => [ { col => undef, table => undef, text => "2.7.25" }, { col => undef, table => undef, text => "Display Controller Look Up Table B Registers", }, { col => "heading", table => 0, text => "DC_LUTB_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6CC0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_LUTB_INC_B" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Exponent of Power-of-two of blue data increment of LUTB ", }, { col => 3, table => 0, text => "palette." }, { col => 3, table => 0, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => 3, table => 0, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => 3, table => 0, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => 3, table => 0, text => "base and delta values." }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[INC+6:INC]." }, { col => 3, table => 0, text => "Mult = PIX_DATA[INC-1:0]." }, { col => 3, table => 0, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => 3, table => 0, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => 3, table => 0, text => "Output = Base + (Mult * Delta) / increment", }, { col => 3, table => 0, text => " 0=Blue data increment = N/A " }, { col => 3, table => 0, text => " 1=Blue data increment = 2 " }, { col => 3, table => 0, text => " 2=Blue data increment = 4 " }, { col => 3, table => 0, text => " 3=Blue data increment = 8 " }, { col => 3, table => 0, text => " 4=Blue data increment = 16 " }, { col => 3, table => 0, text => " 5=Blue data increment = 32 " }, { col => 3, table => 0, text => " 6=Blue data increment = 64 " }, { col => 3, table => 0, text => " 7=Blue data increment = 128 " }, { col => 3, table => 0, text => " 8=Blue data increment = 256 " }, { col => 3, table => 0, text => " 9=Blue data increment = 512 " }, { col => 0, table => 0, text => "DC_LUTB_DATA_B_SIGNED_EN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer blue data signed enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Blue data is unsigned " }, { col => 3, table => 0, text => " 1=Blue data is signed " }, { col => 0, table => 0, text => "DC_LUTB_DATA_B_FLOAT_POINT_EN" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer blue data float point enable for look-up table ", }, { col => 3, table => 0, text => "A." }, { col => 3, table => 0, text => " 0=Blue data is fix point " }, { col => 3, table => 0, text => " 1=Blue data is float point " }, ], }, { num => 253, text => [ { col => 0, table => 0, text => "DC_LUTB_INC_G" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Exponent of Power-of-two of green data increment of LUTB ", }, { col => 3, table => 0, text => "palette." }, { col => 3, table => 0, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => 3, table => 0, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => 3, table => 0, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => 3, table => 0, text => "base and delta values." }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[INC+6:INC]." }, { col => 3, table => 0, text => "Mult = PIX_DATA[INC-1:0]." }, { col => 3, table => 0, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => 3, table => 0, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => 3, table => 0, text => "Output = Base + (Mult * Delta) / increment", }, { col => 3, table => 0, text => " 0=Green data increment = N/A " }, { col => 3, table => 0, text => " 1=Green data increment = 2 " }, { col => 3, table => 0, text => " 2=Green data increment = 4 " }, { col => 3, table => 0, text => " 3=Green data increment = 8 " }, { col => 3, table => 0, text => " 4=Green data increment = 16 " }, { col => 3, table => 0, text => " 5=Green data increment = 32 " }, { col => 3, table => 0, text => " 6=Green data increment = 64 " }, { col => 3, table => 0, text => " 7=Green data increment = 128 " }, { col => 3, table => 0, text => " 8=Green data increment = 256 " }, { col => 3, table => 0, text => " 9=Green data increment = 512 " }, { col => 0, table => 0, text => "DC_LUTB_DATA_G_SIGNED_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer green data signed enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Green data is unsigned " }, { col => 3, table => 0, text => " 1=Green data is signed " }, { col => 0, table => 0, text => "DC_LUTB_DATA_G_FLOAT_POINT_EN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer green data float point enable for look-up table ", }, { col => 3, table => 0, text => "A." }, { col => 3, table => 0, text => " 0=Green data is fix point " }, { col => 3, table => 0, text => " 1=Green data is float point " }, { col => 0, table => 0, text => "DC_LUTB_INC_R" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Exponent of Power-of-two of red data increment of LUTB ", }, { col => 3, table => 0, text => "palette." }, { col => 3, table => 0, text => "If INC = 0, LUT 256-entry table mode is enabled.", }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[7:0]." }, { col => 3, table => 0, text => "Output = LUT_DATA[LUT_INDEX]." }, { col => 3, table => 0, text => "If INC > 0, LUT PWL mode is enabled with 128 entries of ", }, { col => 3, table => 0, text => "base and delta values." }, { col => 3, table => 0, text => "LUT_INDEX = PIX_DATA[INC+6:INC]." }, { col => 3, table => 0, text => "Mult = PIX_DATA[INC-1:0]." }, { col => 3, table => 0, text => "Base = LUT_BASE[LUT_INDEX]." }, { col => 3, table => 0, text => "Delta = LUT_DELTA[LUT_INDEX]." }, { col => 3, table => 0, text => "Output = Base + (Mult * Delta) / increment", }, { col => 3, table => 0, text => " 0=Red data increment = N/A " }, { col => 3, table => 0, text => " 1=Red data increment = 2 " }, { col => 3, table => 0, text => " 2=Red data increment = 4 " }, { col => 3, table => 0, text => " 3=Red data increment = 8 " }, { col => 3, table => 0, text => " 4=Red data increment = 16 " }, { col => 3, table => 0, text => " 5=Red data increment = 32 " }, { col => 3, table => 0, text => " 6=Red data increment = 64 " }, { col => 3, table => 0, text => " 7=Red data increment = 128 " }, { col => 3, table => 0, text => " 8=Red data increment = 256 " }, { col => 3, table => 0, text => " 9=Red data increment = 512 " }, { col => 0, table => 0, text => "DC_LUTB_DATA_R_SIGNED_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer red data signed enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Red data is unsigned " }, { col => 3, table => 0, text => " 1=Red data is signed " }, { col => 0, table => 0, text => "DC_LUTB_DATA_R_FLOAT_POINT_EN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Frame buffer red data float point enable for look-up table A.", }, { col => 3, table => 0, text => " 0=Red data is fix point " }, { col => 3, table => 0, text => " 1=Red data is float point " }, ], }, { num => 254, text => [ { col => undef, table => undef, text => "LUTB mode control" }, { col => "heading", table => 0, text => "DC_LUTB_BLACK_OFFSET_BLUE - RW - 32 bits - [GpuF0MMReg:0x6CC4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_LUTB_BLACK_OFFSET_BLUE" }, { col => 1, table => 0, text => "15:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of blue component for LUTB.", }, { col => undef, table => undef, text => "Black value offset of blue component for LUTB.", }, { col => "heading", table => 1, text => "DC_LUTB_BLACK_OFFSET_GREEN - RW - 32 bits - [GpuF0MMReg:0x6CC8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_LUTB_BLACK_OFFSET_GREEN" }, { col => 1, table => 1, text => "15:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of green component for LUTB.", }, { col => undef, table => undef, text => "Black value offset of green component for LUTB.", }, { col => "heading", table => 2, text => "DC_LUTB_BLACK_OFFSET_RED - RW - 32 bits - [GpuF0MMReg:0x6CCC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_LUTB_BLACK_OFFSET_RED" }, { col => 1, table => 2, text => "15:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Black value offset of red component for LUTB.", }, { col => undef, table => undef, text => "Black value offset of red component for LUTB.", }, { col => "heading", table => 3, text => "DC_LUTB_WHITE_OFFSET_BLUE - RW - 32 bits - [GpuF0MMReg:0x6CD0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_LUTB_WHITE_OFFSET_BLUE" }, { col => 1, table => 3, text => "15:0" }, { col => 2, table => 3, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of blue component for LUTB", }, { col => undef, table => undef, text => "White value offset of blue component for LUTB.", }, { col => "heading", table => 4, text => "DC_LUTB_WHITE_OFFSET_GREEN - RW - 32 bits - [GpuF0MMReg:0x6CD4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DC_LUTB_WHITE_OFFSET_GREEN" }, { col => 1, table => 4, text => "15:0" }, { col => 2, table => 4, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of green component for LUTB", }, { col => undef, table => undef, text => "White value offset of green component for LUTB", }, { col => "heading", table => 5, text => "DC_LUTB_WHITE_OFFSET_RED - RW - 32 bits - [GpuF0MMReg:0x6CD8]", }, { col => 0, table => 5, text => "Field Name" }, { col => 1, table => 5, text => "Bits" }, { col => 2, table => 5, text => "Default" }, { col => 3, table => 5, text => "Description" }, { col => 0, table => 5, text => "DC_LUTB_WHITE_OFFSET_RED" }, { col => 1, table => 5, text => "15:0" }, { col => 2, table => 5, text => "0xffff" }, { col => undef, table => undef, text => "White value offset of red component for LUTB", }, { col => undef, table => undef, text => "White value offset of red component for LUTB", }, ], }, { num => 255, text => [ { col => undef, table => undef, text => "2.7.26" }, { col => undef, table => undef, text => "Display Controller CRC Registers", }, { col => "heading", table => 0, text => "DCP_CRC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6C80]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DCP_CRC_ENABLE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable DCP CRC." }, { col => 0, table => 0, text => "DCP_CRC_DISPLAY_SEL" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select display number for DCP CRC." }, { col => 3, table => 0, text => " 0= from display 1 " }, { col => 3, table => 0, text => " 1= from display 2 " }, { col => 0, table => 0, text => "DCP_CRC_SOURCE_SEL" }, { col => 1, table => 0, text => "4:2" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select data source for DCP CRC." }, { col => 3, table => 0, text => " 0=DCP to LB pixel data " }, { col => 3, table => 0, text => " 1=Lower 32 bits of graphics input data to DCP from DMIF ", }, { col => 3, table => 0, text => " 2=Upper 32 bits of graphics input data to DCP from DMIF ", }, { col => 3, table => 0, text => " 3=Overlay input data to DCP from DMIF ", }, { col => undef, table => undef, text => " 4=DCP to LB control signals TAG[2:0] and end of chunk ", }, { col => undef, table => undef, text => "DCP CRC control" }, { col => "heading", table => 1, text => "DCP_CRC_MASK - RW - 32 bits - [GpuF0MMReg:0x6C84]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DCP_CRC_MASK" }, { col => 1, table => 1, text => "31:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Mask bits to apply to DCP CRC function. Allows CRC of ", }, { col => 3, table => 1, text => "only specific color and/or specific bits if wanted. Igore those ", }, { col => undef, table => undef, text => "bits with mask bits to be 0" }, { col => undef, table => undef, text => "Mask bits to apply to DCP CRC function.", }, { col => "heading", table => 2, text => "DCP_CRC_P0_CURRENT - RW - 32 bits - [GpuF0MMReg:0x6C88]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DCP_CRC_P0_CURRENT (R)" }, { col => 1, table => 2, text => "31:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Current value of CRC for current frame pipe 0.", }, { col => undef, table => undef, text => "Current value of CRC for current frame pipe 0.", }, { col => "heading", table => 3, text => "DCP_CRC_P1_CURRENT - RW - 32 bits - [GpuF0MMReg:0x6C8C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DCP_CRC_P1_CURRENT (R)" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Current value of CRC for current frame pipe 1.", }, { col => undef, table => undef, text => "Current value of CRC for current frame pipe 1.", }, { col => "heading", table => 4, text => "DCP_CRC_P0_LAST - RW - 32 bits - [GpuF0MMReg:0x6C90]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DCP_CRC_P0_LAST (R)" }, { col => 1, table => 4, text => "31:0" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "Final value of CRC for previous frame pipe 0.", }, { col => undef, table => undef, text => "Final value of CRC for previous frame pipe 0.", }, ], }, { num => 256, text => [ { col => undef, table => undef, text => "2.7.27" }, { col => undef, table => undef, text => " Display/Memory Interface Control and Status Registers", }, { col => "heading", table => 0, text => "DCP_CRC_P1_LAST - RW - 32 bits - [GpuF0MMReg:0x6C94]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DCP_CRC_P1_LAST (R)" }, { col => 1, table => 0, text => "31:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Final value of CRC for previous frame pipe 1.", }, { col => undef, table => undef, text => "Final value of CRC for previous frame pipe 1.", }, { col => undef, table => undef, text => "DCP_TILING_CONFIG - RW - 32 bits - [GpuF0MMReg:0x6CA0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "PIPE_TILING" }, { col => undef, table => undef, text => "3:1" }, { col => undef, table => undef, text => "0x3" }, { col => undef, table => undef, text => "This specifies the number of logical rendering pipes to use ", }, { col => undef, table => undef, text => "in the tiling pattern. Typically this should match the ", }, { col => undef, table => undef, text => "number of memory channels." }, { col => undef, table => undef, text => " 0=CONFIG_1_PIPE: 1 logical rendering pipe ", }, { col => undef, table => undef, text => " 1=CONFIG_2_PIPE: 2 logical rendering pipes ", }, { col => undef, table => undef, text => " 2=CONFIG_4_PIPE: 4 logical rendering pipes ", }, { col => undef, table => undef, text => " 3=CONFIG_8_PIPE: 8 logical rendering pipes ", }, { col => undef, table => undef, text => "BANK_TILING" }, { col => undef, table => undef, text => "5:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This specifies the number of logical banks to use in the tiling ", }, { col => undef, table => undef, text => "pattern. Typically this should match the number of ", }, { col => undef, table => undef, text => "physical banks in the DRAMs, though it can be smaller ", }, { col => undef, table => undef, text => "(e.g. for DRAMs that have more banks than the tiling ", }, { col => undef, table => undef, text => "supports) or larger (e.g. if rank selection is treated as a ", }, { col => undef, table => undef, text => "logical bank bit)." }, { col => undef, table => undef, text => " 0=CONFIG_4_BANK: 4 logical DRAM banks ", }, { col => undef, table => undef, text => " 1=CONFIG_8_BANK: 8 logical DRAM banks ", }, { col => undef, table => undef, text => "GROUP_SIZE" }, { col => undef, table => undef, text => "7:6" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This specifies the memory interleave group size. All ", }, { col => undef, table => undef, text => "surfaces must be aligned to start at a group interleave ", }, { col => undef, table => undef, text => "boundary. Sequential reads or writes in device address ", }, { col => undef, table => undef, text => "space access this many bytes from each memory channel ", }, { col => undef, table => undef, text => "in turn. Therefore this value determines the maximum ", }, { col => undef, table => undef, text => "DRAM burst size for sequential accesses.", }, { col => undef, table => undef, text => " 0=CONFIG_256B_GROUP: 256B memory interleve ", }, { col => undef, table => undef, text => "groups " }, { col => undef, table => undef, text => " 1=CONFIG_512B_GROUP: 512B memory interleve ", }, { col => undef, table => undef, text => "groups " }, { col => undef, table => undef, text => "ROW_TILING" }, { col => undef, table => undef, text => "10:8" }, { col => undef, table => undef, text => "0x2" }, { col => undef, table => undef, text => "This specifies a DRAM row size for use in tiling, within a ", }, { col => undef, table => undef, text => "given bank of a given memory channel. This may be ", }, { col => undef, table => undef, text => "smaller than the actual DRAM row size, but should not be ", }, { col => undef, table => undef, text => "larger. The tiling pattern switches banks at these row ", }, { col => undef, table => undef, text => "boundaries and clients may also use this field to determine ", }, { col => undef, table => undef, text => "whether two accesses might be in the same row. These ", }, { col => undef, table => undef, text => "strategies are not effective for scattered virtual memorty ", }, { col => undef, table => undef, text => "mappings." }, { col => undef, table => undef, text => " 0=CONFIG_1KB_ROW: Treat 1KB as DRAM row ", }, { col => undef, table => undef, text => "boundary " }, { col => undef, table => undef, text => " 1=CONFIG_2KB_ROW: Treat 2KB as DRAM row ", }, { col => undef, table => undef, text => "boundary " }, { col => undef, table => undef, text => " 2=CONFIG_4KB_ROW: Treat 4KB as DRAM row ", }, { col => undef, table => undef, text => "boundary " }, { col => undef, table => undef, text => " 3=CONFIG_8KB_ROW: Treat 8KB as DRAM row ", }, { col => undef, table => undef, text => "boundary " }, ], }, { num => 257, text => [ { col => 0, table => 0, text => "BANK_SWAPS" }, { col => 1, table => 0, text => "13:11" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "When performing display reads, this specifies the maximum ", }, { col => 3, table => 0, text => "number of bytes accessed per memory channel within ", }, { col => 3, table => 0, text => "each bank before switching banks. This affects the DRAM ", }, { col => 3, table => 0, text => "burst length for display accesses. The actual burst length ", }, { col => 3, table => 0, text => "may be less, depending on the row size above and on ", }, { col => 3, table => 0, text => "whether the display access starts in the middle of a bank ", }, { col => 3, table => 0, text => "swap sequence. This also ensures that crossing a ", }, { col => 3, table => 0, text => "DRAM row boundary switches banks, provided that the ", }, { col => 3, table => 0, text => "virtual page mapping is aligned properly.", }, { col => 3, table => 0, text => " 0=CONFIG_128B_SWAPS: Perform bank swap after ", }, { col => 3, table => 0, text => "128B " }, { col => 3, table => 0, text => " 1=CONFIG_256B_SWAPS: Perform bank swap after ", }, { col => 3, table => 0, text => "256B " }, { col => 3, table => 0, text => " 2=CONFIG_512B_SWAPS: Perform bank swap after ", }, { col => 3, table => 0, text => "512B " }, { col => 3, table => 0, text => " 3=CONFIG_1KB_SWAPS: Perform bank swap after 1KB ", }, { col => 0, table => 0, text => "SAMPLE_SPLIT" }, { col => 1, table => 0, text => "15:14" }, { col => 2, table => 0, text => "0x3" }, { col => 3, table => 0, text => "This controls the number of bytes per tile that may be used ", }, { col => 3, table => 0, text => "to store multiple samples of fragments. If multi-sample ", }, { col => 3, table => 0, text => "data requires more bytes than this per tile, it is split into ", }, { col => 3, table => 0, text => "multiple slices." }, { col => 3, table => 0, text => " 0=CONFIG_1KB_SPLIT: Split multi-sample tiles over 1KB ", }, { col => 3, table => 0, text => " 1=CONFIG_2KB_SPLIT: Split multi-sample tiles over 2KB ", }, { col => 3, table => 0, text => " 2=CONFIG_4KB_SPLIT: Split multi-sample tiles over 4KB ", }, { col => undef, table => undef, text => " 3=CONFIG_8KB_SPLIT: Split multi-sample tiles over 8KB ", }, { col => undef, table => undef, text => "This register is a copy of PDMA_TILING_CONFIG and may ONLY be written when the chip is idle, and MUST be matched by ", }, { col => undef, table => undef, text => "a write to GB_TILING_CONFIG, PDMA_TILING_CONFIG and all copies of *TILING_CONFIG. It affects the 2D tiling modes, ", }, { col => undef, table => undef, text => "so writing to it invalidates all 2D tiled surfaces.", }, { col => "heading", table => 1, text => "DCP_MULTI_CHIP_CNTL - RW - 32 bits - [GpuF0MMReg:0x6CA4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "LOG2_NUM_CHIPS" }, { col => 1, table => 1, text => "2:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Log2 of the number of chips in the multi-chip configuration.", }, { col => 0, table => 1, text => "MULTI_CHIP_TILE_SIZE" }, { col => 1, table => 1, text => "4:3" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Size of the tile per chip within each super-tile.", }, { col => 3, table => 1, text => " 0=16 x 16 pixel tile per chip. " }, { col => 3, table => 1, text => " 1=32 x 32 pixel tile per chip. " }, { col => 3, table => 1, text => " 2=64 x 64 pixel tile per chip. " }, { col => undef, table => undef, text => " 3=128x128 pixel tile per chip. ", }, { col => undef, table => undef, text => "Should be programmed with the same value as PA_SC_MULTI_CHIP_CNTL. Controls the Screen Divisioning for Multi-Chip ", }, { col => undef, table => undef, text => "Configurations" }, { col => "heading", table => 2, text => "DMIF_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6CB0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DMIF_BUFF_SIZE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "DMIF memory size." }, { col => 3, table => 2, text => "0x0 - full memory size, 384x256bits." }, { col => 3, table => 2, text => "0x1 - 2/3 memory size." }, { col => 3, table => 2, text => "0x2 - 1/3 memory size." }, { col => 3, table => 2, text => "0x3 - reserved" }, ], }, { num => 258, text => [ { col => undef, table => undef, text => "2.7.28" }, { col => undef, table => undef, text => "MCIF Control Registers" }, { col => 0, table => 0, text => "DMIF_D1_REQ_BURST_SIZE" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "DMIF request burst size for display 1." }, { col => 3, table => 0, text => "0x0 - 1 request." }, { col => 3, table => 0, text => "0x1 - 2 requests." }, { col => 3, table => 0, text => "0x2 - 4 requests." }, { col => 3, table => 0, text => "0x3 - 8 requests." }, { col => 3, table => 0, text => "0x4 - 16 requests." }, { col => 0, table => 0, text => "DMIF_D2_REQ_BURST_SIZE" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x2" }, { col => 3, table => 0, text => "DMIF request burst size for display 2." }, { col => 3, table => 0, text => "0x0 - 1 request." }, { col => 3, table => 0, text => "0x1 - 2 requests." }, { col => 3, table => 0, text => "0x2 - 4 requests." }, { col => 3, table => 0, text => "0x3 - 8 requests." }, { col => undef, table => undef, text => "0x4 - 16 requests." }, { col => undef, table => undef, text => "DMIF control register" }, { col => "heading", table => 1, text => "DMIF_STATUS - RW - 32 bits - [GpuF0MMReg:0x6CB4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DMIF_MC_SEND_ON_IDLE (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This register bit is set to 1 if MH returns data to DMIF when ", }, { col => 3, table => 1, text => "there is no pending request. It is sticky bit. Once this bit is ", }, { col => 3, table => 1, text => "set to high, it will stay high until it is cleared by writing 1 to ", }, { col => 3, table => 1, text => "register DMIF_CLEAR_MH_DATA_ON_IDLE" }, { col => 3, table => 1, text => " 0=MC does not send data to DMIF when there is no data ", }, { col => 3, table => 1, text => "request pending " }, { col => 3, table => 1, text => " 1=MH sends data to DMIF when there is no data pending ", }, { col => 3, table => 1, text => "request. " }, { col => 0, table => 1, text => "DMIF_CLEAR_MC_SEND_ON_IDLE (W)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "This register bit is used to clear register ", }, { col => 3, table => 1, text => "DMIF_MH_SEND_ON_IDLE" }, { col => 3, table => 1, text => " 0=No effect " }, { col => 3, table => 1, text => " 1=Clear register bit DMIF_MH_SEND_ON_IDLE ", }, { col => 0, table => 1, text => "DMIF_MC_LATENCY_COUNTER_ENAB" }, { col => 0, table => 1, text => "LE" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Disable MC latency counter " }, { col => undef, table => undef, text => " 1=Enable MC latency counter " }, { col => undef, table => undef, text => "This is a debug register. DMIF status.", }, { col => undef, table => undef, text => "MCIF_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6CB8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "MCIF_BUFF_SIZE" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "MCIF memory size." }, { col => undef, table => undef, text => "0x0 - full memory size, 16x143bits.", }, { col => undef, table => undef, text => "0x1 - 3/4 memory size." }, { col => undef, table => undef, text => "0x2 - 1/2 memory size." }, { col => undef, table => undef, text => "0x3 - 1/4 memory size." }, { col => undef, table => undef, text => "ADDRESS_TRANSLATION_ENABLE" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables address translation for vga, cursor and icon ", }, { col => undef, table => undef, text => "memory controller requests" }, { col => undef, table => undef, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "PRIVILEGED_ACCESS_ENABLE" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables privileged page access for vga, cursor and icon ", }, { col => undef, table => undef, text => "memory controller requests" }, { col => undef, table => undef, text => " 0=disable " }, { col => undef, table => undef, text => " 1=enable " }, { col => undef, table => undef, text => "LOW_READ_URG_LEVEL" }, { col => undef, table => undef, text => "23:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "This is the urgency level for vga, cursor, icon and vip reads ", }, { col => undef, table => undef, text => "when they are all in low priority", }, ], }, { num => 259, text => [ { col => undef, table => undef, text => "2.7.29" }, { col => undef, table => undef, text => " Display Controller to Line Buffer Control Registers", }, { col => undef, table => undef, text => "2.7.30" }, { col => undef, table => undef, text => "Multi VPU Control Registers" }, { col => 0, table => 0, text => "MC_CLEAN_DEASSERT_LATENCY" }, { col => 1, table => 0, text => "29:24" }, { col => 2, table => 0, text => "0x10" }, { col => 3, table => 0, text => "This is the number of cycles mcif will wait after a write is ", }, { col => 3, table => 0, text => "transfered to the memory controller and before looking at ", }, { col => undef, table => undef, text => "the clean signal from the memory controller", }, { col => undef, table => undef, text => "MCIF control register" }, { col => "heading", table => 1, text => "DCP_LB_DATA_GAP_BETWEEN_CHUNK - RW - 32 bits - [GpuF0MMReg:0x6CBC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DCP_LB_GAP_BETWEEN_CHUNK_20B" }, { col => 0, table => 1, text => "PP" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x5" }, { col => 3, table => 1, text => "This register is used to control gap between data chunks ", }, { col => 3, table => 1, text => "sent from DCP to LB when the next LB data chunk is in ", }, { col => 3, table => 1, text => "20bpp mode. The gap between current chunk and next ", }, { col => 3, table => 1, text => "chunk will be register value plus 1. The default value is 5. If ", }, { col => 3, table => 1, text => "any display has 32bpp digital output enabled, this valus ", }, { col => 3, table => 1, text => "should be set to 6." }, { col => 0, table => 1, text => "DCP_LB_GAP_BETWEEN_CHUNK_30B" }, { col => 0, table => 1, text => "PP" }, { col => 1, table => 1, text => "7:4" }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "This register is used to control gap between data chunks ", }, { col => 3, table => 1, text => "sent from DCP to LB when the next LB data chunk is in ", }, { col => 3, table => 1, text => "30bpp mode. The gap between current chunk and next ", }, { col => 3, table => 1, text => "chunk will be register value plus 1. The default value is 1. If ", }, { col => 3, table => 1, text => "any display has 32bpp digital output enabled, this valus ", }, { col => undef, table => undef, text => "should be set to 4" }, { col => undef, table => undef, text => "DCP LB chunk gap control" }, { col => "heading", table => 2, text => "DC_MVP_LB_CONTROL - RW - 32 bits - [GpuF0MMReg:0x65F4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1_MVP_SWAP_LOCK_IN_MODE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "01 - force input to 1, used for master GPU; 10 - use ", }, { col => 3, table => 2, text => "swap_lock_in, used for slave GPU or middle GPU; 01 is the ", }, { col => 3, table => 2, text => "default" }, { col => 0, table => 2, text => "D2_MVP_SWAP_LOCK_IN_MODE" }, { col => 1, table => 2, text => "5:4" }, { col => 2, table => 2, text => "0x2" }, { col => 3, table => 2, text => "01 - force input to 1, used for master GPU; 10 - use ", }, { col => 3, table => 2, text => "swap_lock_in, used for slave GPU or middle GPU; 10 is the ", }, { col => 3, table => 2, text => "default" }, { col => 0, table => 2, text => "DC_MVP_SWAP_LOCK_OUT_SEL" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 - use D1 swap out output, 1 - use D2 swap out output; ", }, { col => 3, table => 2, text => "default is D1 swap out" }, { col => 0, table => 2, text => "DC_MVP_SWAP_LOCK_OUT_FORCE_" }, { col => 0, table => 2, text => "ONE" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Force Swap_lock to be one" }, { col => 0, table => 2, text => "DC_MVP_SWAP_LOCK_OUT_FORCE_" }, { col => 0, table => 2, text => "ZERO" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Force Swap_lock to be zero" }, { col => 0, table => 2, text => "DC_MVP_D1_DFQ_EN" }, { col => 1, table => 2, text => 18 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable DFQ in multi-GPU mode to select update_pending ", }, { col => 3, table => 2, text => "from DFQ engine" }, { col => 0, table => 2, text => "DC_MVP_D2_DFQ_EN" }, { col => 1, table => 2, text => 19 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable DFQ in multi-GPU mode to select update_pending ", }, { col => 3, table => 2, text => "from DFQ engine" }, { col => 0, table => 2, text => "DC_MVP_D1_SWAP_LOCK_STATUS " }, { col => 0, table => 2, text => "(R)" }, { col => 1, table => 2, text => 20 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "D1 swap_lock status" }, { col => 0, table => 2, text => "DC_MVP_D2_SWAP_LOCK_STATUS " }, { col => 0, table => 2, text => "(R)" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "D2 swap_lock status" }, { col => 0, table => 2, text => "DC_MVP_SWAP_LOCK_IN_CAP (R)" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Capture swap_lock_in, used in diagnostic mode", }, { col => 0, table => 2, text => "DC_MVP_SPARE_FLOPS (R)" }, { col => 1, table => 2, text => 31 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "USED for keeping spare flops (ECO)", }, { col => undef, table => undef, text => "DC MVP LB control register" }, ], }, { num => 260, text => [ { col => undef, table => undef, text => "2.8" }, { col => undef, table => undef, text => "CRTC Control Registers " }, { col => undef, table => undef, text => "2.8.1" }, { col => undef, table => undef, text => "Primary Display CRTC Control Registers", }, { col => "heading", table => 0, text => "DC_CRTC_MASTER_EN - RW - 32 bits - [GpuF0MMReg:0x60F8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_MASTER_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Mirror of D1CRTC_MASTER_EN field in " }, { col => 3, table => 0, text => "D1CRTC_CONTROL register" }, { col => 0, table => 0, text => "D2CRTC_MASTER_EN" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Mirror of D2CRTC_MASTER_EN field in " }, { col => undef, table => undef, text => "D1CRTC_CONTROL register" }, { col => undef, table => undef, text => "Contains mirror of DxCRTC_MASTER_EN register field in DxCRTC_CONTROL registers", }, { col => "heading", table => 1, text => "DC_CRTC_TV_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60FC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "CRTC_TV_DATA_SOURCE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines source of pixel data and control signals to TV ", }, { col => 3, table => 1, text => "encoder" }, { col => 3, table => 1, text => "0 = CRTC1" }, { col => undef, table => undef, text => "1 = CRTC2" }, { col => undef, table => undef, text => "Controls source of pixel data and control signals to TV encoder", }, { col => "heading", table => 2, text => "D1CRTC_H_TOTAL - RW - 32 bits - [GpuF0MMReg:0x6000]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_H_TOTAL" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Horizontal total minus one. Sum of display width, overscan ", }, { col => 3, table => 2, text => "left and right, front and back porch and H sync width.", }, { col => 3, table => 2, text => "E.g. for 800 pixels set to 799 = 0x31F" }, { col => 3, table => 2, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal dimension of the display timing for CRTC1", }, { col => "heading", table => 3, text => "D1CRTC_H_BLANK_START_END - RW - 32 bits - [GpuF0MMReg:0x6004]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_H_BLANK_START" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Start of the horizontal blank. The location of the first pixel of ", }, { col => 3, table => 3, text => "horizontal blank, relative to pixel zero. If right overscan ", }, { col => 3, table => 3, text => "border, then blank starts after border ends.", }, { col => 3, table => 3, text => "Double-buffered with " }, { col => 3, table => 3, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 3, text => "D1CRTC_H_BLANK_END" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "End of the horizontal blank. The location of the next pixel ", }, { col => 3, table => 3, text => "after the last pixel of horizontal blank, relative to pixel zero.", }, { col => 3, table => 3, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal blank region of the display timing for CRTC1", }, ], }, { num => 261, text => [ { col => "heading", table => 0, text => "D1CRTC_H_SYNC_A - RW - 32 bits - [GpuF0MMReg:0x6008]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_H_SYNC_A_START" }, { col => 1, table => 0, text => "12:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "First pixel of horizontal sync A." }, { col => 3, table => 0, text => "In normal cases, it is set to 0. It is only set to non-zero ", }, { col => 3, table => 0, text => "value when we want to test the higher bits of the H counter.", }, { col => 3, table => 0, text => "This register should be ignored and set to 0x0 in VGA ", }, { col => 3, table => 0, text => "timing mode. Hardware does not support odd number ", }, { col => 3, table => 0, text => "value for this register." }, { col => 0, table => 0, text => "D1CRTC_H_SYNC_A_END" }, { col => 1, table => 0, text => "28:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Horizontal sync A end. Determines position of the next ", }, { col => 3, table => 0, text => "pixel after last pixel of horizontal sync A. The last pixel of ", }, { col => 3, table => 0, text => "horizontal sync A is D1CRTC_H_SYNC_A_END - 1. The ", }, { col => 3, table => 0, text => "first pixel of horizontal sync A is pixel 0. It should be ", }, { col => 3, table => 0, text => "programmed to a value one greater than the actual last ", }, { col => 3, table => 0, text => "pixel of horizontal sync A." }, { col => 3, table => 0, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal sync A position for CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_H_SYNC_A_CNTL - RW - 32 bits - [GpuF0MMReg:0x600C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_H_SYNC_A_POL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Polarity of H SYNC A" }, { col => 3, table => 1, text => "0 = active high" }, { col => 3, table => 1, text => "1 = active low" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => 3, table => 1, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 1, text => "D1CRTC_COMP_SYNC_A_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enables composite H sync A" }, { col => 3, table => 1, text => "0 = disabled" }, { col => 3, table => 1, text => "1 = enabled" }, { col => 0, table => 1, text => "D1CRTC_H_SYNC_A_CUTOFF" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Cutoff H sync A at end of H BLANK when end of H sync A is ", }, { col => 3, table => 1, text => "beyond H BLANK" }, { col => 3, table => 1, text => "0 = cutoff is enabled" }, { col => undef, table => undef, text => "1 = cutoff is disabled" }, { col => undef, table => undef, text => "Controls the H SYNC A for CRTC1" }, { col => "heading", table => 2, text => "D1CRTC_H_SYNC_B - RW - 32 bits - [GpuF0MMReg:0x6010]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_H_SYNC_B_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "First pixel of horizontal sync B" }, { col => 0, table => 2, text => "D1CRTC_H_SYNC_B_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Horizontal sync B end. Determines position of the next ", }, { col => 3, table => 2, text => "pixel after last pixel of horizontal sync B. The last pixel of ", }, { col => 3, table => 2, text => "horizontal sync B is D1CRTC_H_SYNC_B_END - 1. This ", }, { col => 3, table => 2, text => "register value is exclusive. It should be programmed to a ", }, { col => 3, table => 2, text => "value one greater than the actual last pixel of horizontal ", }, { col => undef, table => undef, text => "sync B" }, { col => undef, table => undef, text => "Defines the position of horizontal sync B for CRTC1", }, ], }, { num => 262, text => [ { col => "heading", table => 0, text => "D1CRTC_H_SYNC_B_CNTL - RW - 32 bits - [GpuF0MMReg:0x6014]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_H_SYNC_B_POL" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Polarity of H SYNC B" }, { col => 3, table => 0, text => "0 = active high" }, { col => 3, table => 0, text => "1 = active low" }, { col => 0, table => 0, text => "D1CRTC_COMP_SYNC_B_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables composite H SYNC B" }, { col => 3, table => 0, text => "0 = disabled" }, { col => 3, table => 0, text => "1 = enabled" }, { col => 0, table => 0, text => "D1CRTC_H_SYNC_B_CUTOFF" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Cutoff horizontal sync B at end of horizontal blank region ", }, { col => 3, table => 0, text => "when end of H SYNC B is beyond horizontal blank", }, { col => 3, table => 0, text => "0 = cutoff is enabled" }, { col => undef, table => undef, text => "1 = cutoff is disabled" }, { col => undef, table => undef, text => "Controls horizontal sync B for CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_V_TOTAL - RW - 32 bits - [GpuF0MMReg:0x6020]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_V_TOTAL" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Vertical total minus one. Sum of vertical active display, top ", }, { col => 3, table => 1, text => "and bottom overscan, front and back porch and vertical ", }, { col => 3, table => 1, text => "sync width." }, { col => 3, table => 1, text => "E.g. for 525 lines set to 524 = 0x20C" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the vertical dimension of display timing for CRTC1", }, { col => "heading", table => 2, text => "D1CRTC_V_BLANK_START_END - RW - 32 bits - [GpuF0MMReg:0x6024]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_V_BLANK_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical blank start. Determines the position of the first ", }, { col => 3, table => 2, text => "blank line in a frame. Line 0 is the first line of vertical sync ", }, { col => 3, table => 2, text => "A." }, { col => 3, table => 2, text => "Double-buffered with " }, { col => 3, table => 2, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 2, text => "D1CRTC_V_BLANK_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical blank end. Determines the position of the next line ", }, { col => 3, table => 2, text => "after the last line of vertical blank. The last line of vertical ", }, { col => 3, table => 2, text => "blank is D1CRTC_V_BLANK_END - 1." }, { col => 3, table => 2, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the vertical blank region of the display timing for CRTC1", }, { col => "heading", table => 3, text => "D1CRTC_V_SYNC_A - RW - 32 bits - [GpuF0MMReg:0x6028]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_V_SYNC_A_START" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "The first line of vertical sync A. In normal cases, it is set to ", }, { col => 3, table => 3, text => "0. It is set to non-zero value only when trying to test the ", }, { col => 3, table => 3, text => "higher bits of the vertical counter" }, ], }, { num => 263, text => [ { col => 0, table => 0, text => "D1CRTC_V_SYNC_A_END" }, { col => 1, table => 0, text => "28:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Vertical sync A end. Determines the position of the next ", }, { col => 3, table => 0, text => "line after the last line of vertical sync A. The last line of ", }, { col => 3, table => 0, text => "vertical sync A is D1CRTC_V_SYNC_A_END - 1. The first ", }, { col => 3, table => 0, text => "line of vertical sync A is line 0. This register value is ", }, { col => 3, table => 0, text => "exclusive. It should be programmed to a value one greater ", }, { col => 3, table => 0, text => "than the actual last line of vertical sync A", }, { col => 3, table => 0, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the position of vertical sync A for CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_V_SYNC_A_CNTL - RW - 32 bits - [GpuF0MMReg:0x602C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_V_SYNC_A_POL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Polarity of V SYNC A" }, { col => 3, table => 1, text => "0 = active high" }, { col => 3, table => 1, text => "1 = active low" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => undef, table => undef, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Controls V SYNC A for CRTC1" }, { col => "heading", table => 2, text => "D1CRTC_V_SYNC_B - RW - 32 bits - [GpuF0MMReg:0x6030]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_V_SYNC_B_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical sync B start. Determines the position of the first ", }, { col => 3, table => 2, text => "line of vertical sync B." }, { col => 0, table => 2, text => "D1CRTC_V_SYNC_B_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical sync B end. Determines the position of the next ", }, { col => 3, table => 2, text => "line after the last line of vertical sync B. Last line of vertical ", }, { col => 3, table => 2, text => "sync B is D1CRTC_V_SYNC_B_END - 1. This register ", }, { col => 3, table => 2, text => "value is exclusive. It should be programmed to a value one ", }, { col => undef, table => undef, text => "greater than the actual last line of vertical sync B", }, { col => undef, table => undef, text => "Defines the position of vertical sync B for CRTC1", }, { col => "heading", table => 3, text => "D1CRTC_V_SYNC_B_CNTL - RW - 32 bits - [GpuF0MMReg:0x6034]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_V_SYNC_B_POL" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Controls polarity of vertical sync B" }, { col => 3, table => 3, text => "0 = active high" }, { col => undef, table => undef, text => "1 = active low" }, { col => undef, table => undef, text => "Controls vertical sync B for CRTC1", }, { col => undef, table => undef, text => "D1CRTC_TRIGA_CNTL - RW - 32 bits - [GpuF0MMReg:0x6060]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 264, text => [ { col => 0, table => 0, text => "D1CRTC_TRIGA_SOURCE_SELECT" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select source of input signals for external trigger A", }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = VSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = HSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "3 = VSYNCB from another CRTC of the chip", }, { col => 3, table => 0, text => "4 = HSYNCB from another CRTC of the chip", }, { col => 3, table => 0, text => "5 = GENERICA pin" }, { col => 3, table => 0, text => "6 = GENERICB pin" }, { col => 3, table => 0, text => "7 = VSYNCA pin" }, { col => 3, table => 0, text => "8 = HSYNCA pin" }, { col => 3, table => 0, text => "9 = VSYNCB pin" }, { col => 3, table => 0, text => "10 = HSYNCB pin" }, { col => 3, table => 0, text => "11 = HPD1 pin" }, { col => 3, table => 0, text => "12 = HPD2 pin" }, { col => 3, table => 0, text => "13 = DVALID pin" }, { col => 3, table => 0, text => "14 = PSYNC pin" }, { col => 3, table => 0, text => "15 = Video capture complete signal from VIP", }, { col => 0, table => 0, text => "D1CRTC_TRIGA_POLARITY_SELECT" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects source of input signal from polarity of external ", }, { col => 3, table => 0, text => "trigger A" }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = interlace polarity from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = GENERICA pin" }, { col => 3, table => 0, text => "3 = GENERICB pin" }, { col => 3, table => 0, text => "4 = HSYNCA pin" }, { col => 3, table => 0, text => "5 = HSYNCB pin" }, { col => 3, table => 0, text => "6 = video capture polarity input from VIP", }, { col => 3, table => 0, text => "7 = DVALID pin" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_RESYNC_BYPASS_E" }, { col => 0, table => 0, text => "N" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bypass the resync logic for the external trigger A signal and ", }, { col => 3, table => 0, text => "its polarity input signal" }, { col => 3, table => 0, text => "0 = do not bypass" }, { col => 3, table => 0, text => "1 = bypass the resync logic" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_INPUT_STATUS (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read back the value of the external trigger A input signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_POLARITY_STATUS " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the value of the external trigger A polarity signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_OCCURRED (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports whether external trigger A has occurred. A sticky ", }, { col => 3, table => 0, text => "bit." }, { col => 3, table => 0, text => "0 = has not occurred" }, { col => 3, table => 0, text => "1 = has occurred" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_RISING_EDGE_DETE" }, { col => 0, table => 0, text => "CT_CNTL" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of rising edge of the external trigger ", }, { col => 3, table => 0, text => "A signal" }, { col => 3, table => 0, text => "00 = do not detect rising edge" }, { col => 3, table => 0, text => "01 = always detect rising edge" }, { col => 3, table => 0, text => "10 = detect rising edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect rising edge only when field polarity is high", }, { col => 0, table => 0, text => "D1CRTC_TRIGA_FALLING_EDGE_DET" }, { col => 0, table => 0, text => "ECT_CNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of falling edge of external trigger A ", }, { col => 3, table => 0, text => "signal" }, { col => 3, table => 0, text => "00 = do not detect falling edge" }, { col => 3, table => 0, text => "01 = always detect falling edge" }, { col => 3, table => 0, text => "10 = detect falling edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect falling edge only when field polarity is high", }, { col => 0, table => 0, text => "D1CRTC_TRIGA_FREQUENCY_SELEC" }, { col => 0, table => 0, text => "T" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines the frequency of the external trigger A signal", }, { col => 3, table => 0, text => "00 = send every signal" }, { col => 3, table => 0, text => "01 = send every 2 signals" }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = send every 4 signals" }, { col => 0, table => 0, text => "D1CRTC_TRIGA_DELAY" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "A programmable PCLK_CRTC1 delay to send external ", }, { col => 3, table => 0, text => "trigger A signal." }, { col => 0, table => 0, text => "D1CRTC_TRIGA_CLEAR (W)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the sticky bit D1CRTC_TRIGA_OCCURRED when ", }, { col => undef, table => undef, text => "written with '1'" }, { col => undef, table => undef, text => "Controls for external trigger A signal in CRTC1", }, ], }, { num => 265, text => [ { col => undef, table => undef, text => "D1CRTC_TRIGA_MANUAL_TRIG - RW - 32 bits - [GpuF0MMReg:0x6064]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1CRTC_TRIGA_MANUAL_TRIG (W)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "One shot trigger for external trigger A signal when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual trigger for external trigger A signal of CRTC1", }, { col => "heading", table => 0, text => "D1CRTC_TRIGB_CNTL - RW - 32 bits - [GpuF0MMReg:0x6068]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_SOURCE_SELECT" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select source of input signals for external trigger B", }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = VSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = HSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "3 = VSYNCB from another CRTC of the chip", }, { col => 3, table => 0, text => "4 = HSYNCB from another CR TC of the chip", }, { col => 3, table => 0, text => "5 = GENERICA pin" }, { col => 3, table => 0, text => "6 = GENERICB pin" }, { col => 3, table => 0, text => "7 = VSYNCA pin" }, { col => 3, table => 0, text => "8 = HSYNCA pin" }, { col => 3, table => 0, text => "9 = VSYNCB pin" }, { col => 3, table => 0, text => "10 = HSYNCB pin" }, { col => 3, table => 0, text => "11 = HPD1 pin" }, { col => 3, table => 0, text => "12 = HPD2 pin" }, { col => 3, table => 0, text => "13 = DVALID pin" }, { col => 3, table => 0, text => "14 = PSYNC pin" }, { col => 3, table => 0, text => "15 = Video capture complete signal from VIP", }, { col => 0, table => 0, text => "D1CRTC_TRIGB_POLARITY_SELECT" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects source of input signal from polarity of external ", }, { col => 3, table => 0, text => "trigger A" }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = interlace polarity from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = GENERICA pin" }, { col => 3, table => 0, text => "3 = GENERICB pin" }, { col => 3, table => 0, text => "4 = HSYNCA pin" }, { col => 3, table => 0, text => "5 = HSYNCB pin" }, { col => 3, table => 0, text => "6 = video capture polarity input from VIP", }, { col => 3, table => 0, text => "7 = DVALID pin" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_RESYNC_BYPASS_E" }, { col => 0, table => 0, text => "N" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bypass the resync logic for the external trigger A signal and ", }, { col => 3, table => 0, text => "its polarity input signal" }, { col => 3, table => 0, text => "0 = do not bypass" }, { col => 3, table => 0, text => "1 = bypass the resync logic" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_INPUT_STATUS (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read back the value of the external trigger B input signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_POLARITY_STATUS " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the value of the external trigger B polarity signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_OCCURRED (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports whether external trigger B has occurred. A sticky ", }, { col => 3, table => 0, text => "bit." }, { col => 3, table => 0, text => "0 = has not occurred" }, { col => 3, table => 0, text => "1 = has occurred" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_RISING_EDGE_DETE" }, { col => 0, table => 0, text => "CT_CNTL" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of rising edge of the external trigger ", }, { col => 3, table => 0, text => "B signal" }, { col => 3, table => 0, text => "00 = do not detect rising edge" }, { col => 3, table => 0, text => "01 = always detect rising edge" }, { col => 3, table => 0, text => "10 = detect rising edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect rising edge only when field polarity is high", }, ], }, { num => 266, text => [ { col => 0, table => 0, text => "D1CRTC_TRIGB_FALLING_EDGE_DET" }, { col => 0, table => 0, text => "ECT_CNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of falling edge of external trigger B ", }, { col => 3, table => 0, text => "signal" }, { col => 3, table => 0, text => "00 = do not detect falling edge" }, { col => 3, table => 0, text => "01 = always detect falling edge" }, { col => 3, table => 0, text => "10 = detect falling edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect falling edge only when field polarity is high", }, { col => 0, table => 0, text => "D1CRTC_TRIGB_FREQUENCY_SELEC" }, { col => 0, table => 0, text => "T" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines the frequency of the external trigger B signal", }, { col => 3, table => 0, text => "00 = send every signal" }, { col => 3, table => 0, text => "01 = send every 2 signals" }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = send every 4 signals" }, { col => 0, table => 0, text => "D1CRTC_TRIGB_DELAY" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "A programmable delay to send external trigger B signal", }, { col => 0, table => 0, text => "D1CRTC_TRIGB_CLEAR (W)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the sticky bit D1CRTC_TRIGB_OCCURRED when ", }, { col => undef, table => undef, text => "written with '1'" }, { col => undef, table => undef, text => "Control for external trigger B signal of CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_TRIGB_MANUAL_TRIG - RW - 32 bits - [GpuF0MMReg:0x606C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_TRIGB_MANUAL_TRIG (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "One shot trigger for external trigger B signal when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual trigger for external trigger B signal for CRTC1", }, { col => "heading", table => 2, text => "D1CRTC_FORCE_COUNT_NOW_CNTL - RW - 32 bits - [GpuF0MMReg:0x6070]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_MODE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls which timing counter is forced" }, { col => 3, table => 2, text => "0 = force counter now mode is disabled" }, { col => 3, table => 2, text => "1 = force H count now to H_TOTAL only" }, { col => 3, table => 2, text => "2 = force H count to H_TOTAL and V count to V_TOTAL in ", }, { col => 3, table => 2, text => "progressive mode and V_TOTAL-1 in interlaced mode", }, { col => 3, table => 2, text => "3 = reserved" }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_TRIG_" }, { col => 0, table => 2, text => "SEL" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Selects the trigger signal as force count now trigger", }, { col => 3, table => 2, text => "0 = selects CRTC_TRIG_A and CRTC_TRIG_A_POL", }, { col => 3, table => 2, text => "1 = selects CRTC_TRIG_B and CRTC_TRIG_B_POL", }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_OCCU" }, { col => 0, table => 2, text => "RRED (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of force count now, a sticky bit.", }, { col => 3, table => 2, text => "0 = CRTC force count now has not occurred", }, { col => 3, table => 2, text => "1 = CRTC force count now has occurred" }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_CLEA" }, { col => 0, table => 2, text => "R (W)" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Resets D1CRTC_FORCE_COUNT_NOW_OCCURRED " }, { col => undef, table => undef, text => "when written with '1'" }, { col => undef, table => undef, text => "Controls CRTC1 force count now logic", }, { col => "heading", table => 3, text => "D1CRTC_FLOW_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6074]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 267, text => [ { col => 0, table => 0, text => "D1CRTC_FLOW_CONTROL_SOURCE_" }, { col => 0, table => 0, text => "SELECT" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects the signal used for flow control in CRTC1", }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = GENERICA pin" }, { col => 3, table => 0, text => "2 = GENERICB pin" }, { col => 3, table => 0, text => "3 = HPD1 pin" }, { col => 3, table => 0, text => "4 = HPD2 pin" }, { col => 3, table => 0, text => "5 = DDC1DATA pin" }, { col => 3, table => 0, text => "6 = DDC1CLK pin" }, { col => 3, table => 0, text => "7 = DDC2DATA pin" }, { col => 3, table => 0, text => "8 = DDC2CLK pin" }, { col => 3, table => 0, text => "9 = DVOCLK pin" }, { col => 3, table => 0, text => "10 = VHAD(0] pin" }, { col => 3, table => 0, text => "11 = VHAD[1] pin" }, { col => 3, table => 0, text => "12 = VPHCTL pin" }, { col => 3, table => 0, text => "13 = VIPCLK pin" }, { col => 3, table => 0, text => "14 = DVALID pin" }, { col => 3, table => 0, text => "15 = PSYNC pin" }, { col => 3, table => 0, text => "16 = a GPIO pin for dual-GPU, TBD" }, { col => 0, table => 0, text => "D1CRTC_FLOW_CONTROL_POLARITY" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the polarity of the flow control input signal", }, { col => 3, table => 0, text => "0 = keep the signal the same polarity" }, { col => 3, table => 0, text => "1 = invert the polartiy of the input signal", }, { col => 0, table => 0, text => "D1CRTC_FLOW_CONTROL_GRANULA" }, { col => 0, table => 0, text => "RITY" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls at which pixel position flow control can start to ", }, { col => 3, table => 0, text => "happen" }, { col => 3, table => 0, text => "0 = flow control only start to happen on odd-even pixel ", }, { col => 3, table => 0, text => "boundary" }, { col => 3, table => 0, text => "1 = flow control can start at any pixel position", }, { col => 0, table => 0, text => "D1CRTC_FLOW_CONTROL_INPUT_ST" }, { col => 0, table => 0, text => "ATUS (R)" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the value of the flow control input signal", }, { col => 3, table => 0, text => "0 = output of source mux of flow control signal is low", }, { col => undef, table => undef, text => "1 = output of source mux of flow control signal is high", }, { col => undef, table => undef, text => "Controls flow control of CRTC1" }, { col => "heading", table => 1, text => "D1CRTC_PIXEL_DATA_READBACK - RW - 32 bits - [GpuF0MMReg:0x6078]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_PIXEL_DATA_BLUE_CB (R)" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "B/Cb component sent to DISPOUT" }, { col => 0, table => 1, text => "D1CRTC_PIXEL_DATA_GREEN_Y (R)" }, { col => 1, table => 1, text => "19:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "G/Y component sent to DISPOUT" }, { col => 0, table => 1, text => "D1CRTC_PIXEL_DATA_RED_CR (R)" }, { col => 1, table => 1, text => "29:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "R/Cr component sent to DISPOUT" }, { col => undef, table => undef, text => "Read back of the CRTC1 pixel data sent to DISPOUT. This is a debug register. Intended for use in one shot clocking mode.", }, { col => "heading", table => 2, text => "D1CRTC_STEREO_FORCE_NEXT_EYE - RW - 32 bits - [GpuF0MMReg:0x607C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_STEREO_FORCE_NEXT_EYE " }, { col => 0, table => 2, text => "(W)" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Force next frame eye view - One shot." }, { col => 3, table => 2, text => "00: No force - next eye opposite of current eye", }, { col => 3, table => 2, text => "01: Right eye force - force right eye next field/frame", }, { col => 3, table => 2, text => "10: Left eye force - force right eye next field/frame", }, { col => 3, table => 2, text => "11: Reserved" }, { col => 3, table => 2, text => " After a force has occured, readback of this register will be ", }, { col => undef, table => undef, text => "00" }, { col => undef, table => undef, text => "Force Next Eye register" }, ], }, { num => 268, text => [ { col => "heading", table => 0, text => "D1CRTC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6080]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_MASTER_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables/Disables CRTC1. H counter is at H_TOTAL and V ", }, { col => 3, table => 0, text => "counter is at first line of blank when CRTC is disabled.", }, { col => 3, table => 0, text => "0 = Disabled" }, { col => 3, table => 0, text => "1 = Enabled" }, { col => 0, table => 0, text => "D1CRTC_SYNC_RESET_SEL" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Allows power management to lower CRTC1 enable.", }, { col => 0, table => 0, text => "D1CRTC_DISABLE_POINT_CNTL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "When D1CRTC_MASTER_EN is set to 0, delay the ", }, { col => 3, table => 0, text => "disabling of CRTC1 until certain point within the frame", }, { col => 3, table => 0, text => "00 = disable CRTC immediately" }, { col => 3, table => 0, text => "01 = delay disable CRTC until the end of the current line", }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = delay disable CRTC until end of the first line in the ", }, { col => 3, table => 0, text => "vertical blank region" }, { col => 0, table => 0, text => "D1CRTC_CURRENT_MASTER_EN_STA" }, { col => 0, table => 0, text => "TE (R)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read-only field indicates the current status of the timing ", }, { col => 3, table => 0, text => "generator. Can be used to poll for when a delayed disable ", }, { col => 3, table => 0, text => "takes effect." }, { col => 3, table => 0, text => "0 = CRTC is disabled" }, { col => 3, table => 0, text => "1 = CRTC is enabled" }, { col => 0, table => 0, text => "D1CRTC_DISP_READ_REQUEST_DISA" }, { col => 0, table => 0, text => "BLE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disables data read request from the display controller. Can ", }, { col => 3, table => 0, text => "be used to stop display reads from system memory but ", }, { col => 3, table => 0, text => "keep display timing generation running. Has no effect if ", }, { col => 3, table => 0, text => "CRTC is disabled." }, { col => 3, table => 0, text => "0 = do not disable data read request" }, { col => 3, table => 0, text => "1 = disable data read request" }, { col => 0, table => 0, text => "D1CRTC_PREFETCH_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Double bufferred. Enable data prefetch for display 1", }, { col => 3, table => 0, text => "0 = do not enable prefetch" }, { col => 3, table => 0, text => "1 = enable data prefetch" }, { col => 0, table => 0, text => "D1CRTC_SOF_PULL_EN" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "At SOF, LB level can be set a a programmable value ", }, { col => 3, table => 0, text => "(D1MODE_SOF_READ_PT), which is the point LB can ", }, { col => 3, table => 0, text => "make requests to. Between SOF to active line, CRTC ", }, { col => 3, table => 0, text => "needs to pull scaler/LB so that LB can make data requests ", }, { col => 3, table => 0, text => "beyond that programmable point. " }, { col => 3, table => 0, text => "0 = do not enable pulling" }, { col => undef, table => undef, text => "1 = enable pulling" }, { col => undef, table => undef, text => "Controls CRTC1 timing generator and data read request to display1", }, { col => undef, table => undef, text => "D1CRTC_BLANK_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6084]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1CRTC_CURRENT_BLANK_STATE (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read only status indicating current state of display ", }, { col => undef, table => undef, text => "blanking." }, { col => undef, table => undef, text => "0 = screen not blanked" }, { col => undef, table => undef, text => "1 = screen is blanked" }, { col => undef, table => undef, text => "D1CRTC_BLANK_DATA_EN" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable for blanking active display area. The active area of ", }, { col => undef, table => undef, text => "display that is forced will use the ", }, { col => undef, table => undef, text => "D1CRTC_BLACK_COLOR value." }, { col => undef, table => undef, text => "This field is optionally double buffered with ", }, { col => undef, table => undef, text => "D1CRTC_BLANK_DATA_DOUBLE_BUFFER_EN.", }, { col => undef, table => undef, text => "0 = disable blanking" }, { col => undef, table => undef, text => "1 = enable blanking" }, ], }, { num => 269, text => [ { col => 0, table => 0, text => "D1CRTC_BLANK_DE_MODE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether BLANK and DATA_ACTIVE signal ", }, { col => 3, table => 0, text => "keeps toggling when screen is blank" }, { col => 3, table => 0, text => "0 = toggles BLANK and DATA_ACTIVE" }, { col => undef, table => undef, text => "1 = keep BLANK active and DATA_ACTIVE inactive", }, { col => undef, table => undef, text => "Controls forced blanking of active area of display timing. Useful for display mode switches when corrupted image may be ", }, { col => undef, table => undef, text => "generated for a frame or two." }, { col => undef, table => undef, text => "D1CRTC_INTERLACE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6088]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1CRTC_INTERLACE_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables interlaced timing" }, { col => undef, table => undef, text => "0 = Progressive timing" }, { col => undef, table => undef, text => "1 = Interlaced timing" }, { col => undef, table => undef, text => "D1CRTC_INTERLACE_FORCE_NEXT_F" }, { col => undef, table => undef, text => "IELD (W)" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "One shot force next field polarity when written", }, { col => undef, table => undef, text => "00 = does not force next field" }, { col => undef, table => undef, text => "01 = force only next field to odd", }, { col => undef, table => undef, text => "10 = force only next field to even", }, { col => undef, table => undef, text => "11 = does not force next field" }, { col => undef, table => undef, text => "Interlaced timing control for CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_INTERLACE_STATUS - RW - 32 bits - [GpuF0MMReg:0x608C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_INTERLACE_CURRENT_FIEL" }, { col => 0, table => 1, text => "D (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports the polarity of current field" }, { col => 3, table => 1, text => "0 = even" }, { col => 3, table => 1, text => "1 = odd" }, { col => 0, table => 1, text => "D1CRTC_INTERLACE_NEXT_FIELD (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports the polarity of the next field. Normally the opposite ", }, { col => 3, table => 1, text => "of the current field. When " }, { col => 3, table => 1, text => "D1CRTC_INTERLACE_FORCE_NEXT_FIELD is used to ", }, { col => 3, table => 1, text => "force polarity of next field, then next field can match current ", }, { col => 3, table => 1, text => "field." }, { col => 3, table => 1, text => "0 = even" }, { col => undef, table => undef, text => "1 = odd" }, { col => undef, table => undef, text => "Read-only register reports the polarity of the current and next field for interlaced timing", }, { col => "heading", table => 2, text => "D1CRTC_BLANK_DATA_COLOR - RW - 32 bits - [GpuF0MMReg:0x6090]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_BLANK_DATA_COLOR_BLUE" }, { col => 0, table => 2, text => "_CB" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "B / Cb component" }, { col => 0, table => 2, text => "D1CRTC_BLANK_DATA_COLOR_GREE" }, { col => 0, table => 2, text => "N_Y" }, { col => 1, table => 2, text => "19:10" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "G / Y component" }, { col => 0, table => 2, text => "D1CRTC_BLANK_DATA_COLOR_RED_" }, { col => 0, table => 2, text => "CR" }, { col => 1, table => 2, text => "29:20" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "R / Cr component" }, { col => undef, table => undef, text => "Set the color for pixels in blank region", }, ], }, { num => 270, text => [ { col => "heading", table => 0, text => "D1CRTC_OVERSCAN_COLOR - RW - 32 bits - [GpuF0MMReg:0x6094]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_OVERSCAN_COLOR_BLUE" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "B or Cb component" }, { col => 0, table => 0, text => "D1CRTC_OVERSCAN_COLOR_GREEN" }, { col => 1, table => 0, text => "19:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "G or Y component" }, { col => 0, table => 0, text => "D1CRTC_OVERSCAN_COLOR_RED" }, { col => 1, table => 0, text => "29:20" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "R or Cr component" }, { col => undef, table => undef, text => "Defines color of the overscan region for CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_BLACK_COLOR - RW - 32 bits - [GpuF0MMReg:0x6098]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_BLACK_COLOR_B_CB" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "B / Cb component of the black color" }, { col => 0, table => 1, text => "D1CRTC_BLACK_COLOR_G_Y" }, { col => 1, table => 1, text => "19:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "G / Y component of the black color" }, { col => 0, table => 1, text => "D1CRTC_BLACK_COLOR_R_CR" }, { col => 1, table => 1, text => "29:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "R / Cr component of the black color", }, { col => undef, table => undef, text => "Black color applied to the active display region when blanking the screen", }, { col => "heading", table => 2, text => "D1CRTC_STATUS - RW - 32 bits - [GpuF0MMReg:0x609C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_V_BLANK (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside vertical blank region" }, { col => 3, table => 2, text => "1 = within vertical blank region" }, { col => 0, table => 2, text => "D1CRTC_V_ACTIVE_DISP (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside vertical active display region", }, { col => 3, table => 2, text => "1 = within vertical active display region", }, { col => 0, table => 2, text => "D1CRTC_V_SYNC_A (R)" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside VSYNC" }, { col => 3, table => 2, text => "1 = within VSYNC" }, { col => 0, table => 2, text => "D1CRTC_V_UPDATE (R)" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside the V_UPDATE region" }, { col => 3, table => 2, text => "1 = within the V_UPDATE region (between end of vertical ", }, { col => 3, table => 2, text => "active display and start_line)" }, { col => 0, table => 2, text => "D1CRTC_V_START_LINE (R)" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside start_line region" }, { col => 3, table => 2, text => "1 = within start_line region" }, { col => 0, table => 2, text => "D1CRTC_H_BLANK (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal position" }, { col => 3, table => 2, text => "0 = outside horizontal blank region" }, { col => 3, table => 2, text => "1 = within horizontal blank region" }, { col => 0, table => 2, text => "D1CRTC_H_ACTIVE_DISP (R)" }, { col => 1, table => 2, text => 17 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal region" }, { col => 3, table => 2, text => "0 = outside horizontal active display region", }, { col => 3, table => 2, text => "1 = within horizontal active display region", }, { col => 0, table => 2, text => "D1CRTC_H_SYNC_A (R)" }, { col => 1, table => 2, text => 18 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal position" }, { col => 3, table => 2, text => "0 = outside horizontal sync" }, { col => undef, table => undef, text => "1 = within horizontal sync" }, { col => undef, table => undef, text => "Reports the position of CRTC1" }, { col => "heading", table => 3, text => "D1CRTC_STATUS_POSITION - RW - 32 bits - [GpuF0MMReg:0x60A0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_VERT_COUNT (R)" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Reports current vertical count" }, { col => 0, table => 3, text => "D1CRTC_HORZ_COUNT (R)" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Reports current horizontal count", }, { col => undef, table => undef, text => "Current horizontal and vertical count of CRTC1", }, ], }, { num => 271, text => [ { col => "heading", table => 0, text => "D1CRTC_STATUS_FRAME_COUNT - RW - 32 bits - [GpuF0MMReg:0x60A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_FRAME_COUNT (R)" }, { col => 1, table => 0, text => "23:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Reports current frame count" }, { col => undef, table => undef, text => "Current frame count for CRTC1" }, { col => "heading", table => 1, text => "D1CRTC_STATUS_VF_COUNT - RW - 32 bits - [GpuF0MMReg:0x60A8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_VF_COUNT (R)" }, { col => 1, table => 1, text => "28:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Reports current vertical and frame count", }, { col => undef, table => undef, text => "Current composite vertical and frame count for CRTC1", }, { col => "heading", table => 2, text => "D1CRTC_STATUS_HV_COUNT - RW - 32 bits - [GpuF0MMReg:0x60AC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_HV_COUNT (R)" }, { col => 1, table => 2, text => "28:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Reports current horizontal and vertical count", }, { col => undef, table => undef, text => "Current composite H/V count of CRTC1", }, { col => undef, table => undef, text => "D1CRTC_COUNT_RESET - RW - 32 bits - [GpuF0MMReg:0x60B0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1CRTC_RESET_FRAME_COUNT (W)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "One-shot reset of frame counter of CRTC1 when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Resets CRTC1 counters" }, { col => "heading", table => 3, text => "D1CRTC_COUNT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60B4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_HORZ_COUNT_BY2_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Set to 1 for DVI 30bpp mode only, set to 0 otherwise", }, { col => 0, table => 3, text => "D1CRTC_HORZ_REPETITION_COUNT" }, { col => 1, table => 3, text => "4:1" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable horizontal repetition. CRTC increments the H ", }, { col => 3, table => 3, text => "counter every (COUNT+1) pixel clocks" }, { col => 3, table => 3, text => "0 = every clock" }, { col => 3, table => 3, text => "1 = every 2 clocks" }, { col => 3, table => 3, text => "2 = every 3 clocks" }, { col => undef, table => undef, text => "etc" }, { col => undef, table => undef, text => "Controls the counters in CRTC1" }, ], }, { num => 272, text => [ { col => "heading", table => 0, text => "D1CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE - RW - 32 bits - [GpuF0MMReg:0x60B8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_MANUAL_FORCE_VSYNC_NE" }, { col => 0, table => 0, text => "XT_LINE (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "One shot force VSYNCA to happen next line when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual force of VSYNC to happen next line", }, { col => "heading", table => 1, text => "D1CRTC_VERT_SYNC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60BC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether force vsync next line event has occurred. ", }, { col => 3, table => 1, text => "Sticky bit." }, { col => 3, table => 1, text => "0 = event has not occurred" }, { col => 3, table => 1, text => "1 = event has occurred" }, { col => 0, table => 1, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "CLEAR (W)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "One shot clear to the sticky bit " }, { col => 3, table => 1, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED " }, { col => 3, table => 1, text => "when written with '1'" }, { col => 0, table => 1, text => "D1CRTC_AUTO_FORCE_VSYNC_MOD" }, { col => 0, table => 1, text => "E" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selection of auto mode for forcing vsync next line", }, { col => 3, table => 1, text => "00 = disables auto mode" }, { col => 3, table => 1, text => "01 = force VSYNC next line on CRTC trigger A signal", }, { col => 3, table => 1, text => "10 = force VSYNC next line on CRTC trigger B signal", }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls the feature to force VSYNC next line for CRTC1", }, { col => "heading", table => 2, text => "D1CRTC_STEREO_STATUS - RW - 32 bits - [GpuF0MMReg:0x60C0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_STEREO_CURRENT_EYE (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the polarity of the current frame/field", }, { col => 3, table => 2, text => "0 = right eye image" }, { col => 3, table => 2, text => "1 = left eye image" }, { col => 0, table => 2, text => "D1CRTC_STEREO_SYNC_OUTPUT (R)" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports current value of STEREOSYNC signal ", }, { col => 3, table => 2, text => "(STEREOSYNC sent to the DISPOUT block)" }, { col => 0, table => 2, text => "D1CRTC_STEREO_SYNC_SELECT (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports current value of SYNC_SELECT signal ", }, { col => 3, table => 2, text => "(SYNC_SELECT sent to the SCL block)" }, { col => 0, table => 2, text => "D1CRTC_STEREO_FORCE_NEXT_EYE" }, { col => 0, table => 2, text => "_PENDING (R)" }, { col => 1, table => 2, text => "25:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of " }, { col => 3, table => 2, text => "D1CRTC_STEREO_FORCE_NEXT_EYE write." }, { col => 3, table => 2, text => "00: No force pending" }, { col => 3, table => 2, text => "01: Right force pending" }, { col => 3, table => 2, text => "10: Left force pending" }, { col => undef, table => undef, text => "11: Reserved" }, { col => undef, table => undef, text => "Reports CRTC1 status in stereoscopic display", }, { col => "heading", table => 3, text => "D1CRTC_STEREO_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60C4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_STEREO_SYNC_OUTPUT_PO" }, { col => 0, table => 3, text => "LARITY" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Controls polarity of the stereosync signal", }, { col => 3, table => 3, text => "0 = 0 means right eye image and 1 means left eye image", }, { col => 3, table => 3, text => "1 = 0 means left eye image and 1 means right eye image", }, ], }, { num => 273, text => [ { col => 0, table => 0, text => "D1CRTC_STEREO_SYNC_SELECT_PO" }, { col => 0, table => 0, text => "LARITY" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls polarity of STEREO_SELECT signal sent to scaler", }, { col => 3, table => 0, text => "0 = 0 means right eye image and 1 means left eye image", }, { col => 3, table => 0, text => "1 = 0 means left eye image and 1 means right eye image", }, { col => 0, table => 0, text => "D1CRTC_STEREO_EN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables toggling of STEREOSYNC and STEREO_SELECT ", }, { col => 3, table => 0, text => "signals" }, { col => 3, table => 0, text => "0 = disable toggling." }, { col => 3, table => 0, text => "1 = enable toggling at every frame (progressive) or every ", }, { col => undef, table => undef, text => "field (interlace) at leading edge of VSYNCA", }, { col => undef, table => undef, text => "Stereosync control for CRTC1" }, { col => "heading", table => 1, text => "D1CRTC_SNAPSHOT_STATUS - RW - 32 bits - [GpuF0MMReg:0x60C8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_SNAPSHOT_OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports status of snapshot. A sticky bit to be cleared by ", }, { col => 3, table => 1, text => "writing 1 to D1CRTC_SNAPSHOT_CLEAR" }, { col => 3, table => 1, text => "0 = snapshot has not occurred" }, { col => 3, table => 1, text => "1 = snapshot has occurred" }, { col => 0, table => 1, text => "D1CRTC_SNAPSHOT_CLEAR (W)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Clears the D1CRTC_SNAPSHOT_OCCURRED sticky bit ", }, { col => 3, table => 1, text => "when written with '1'" }, { col => 0, table => 1, text => "D1CRTC_SNAPSHOT_MANUAL_TRIGG" }, { col => 0, table => 1, text => "ER (W)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "One shot trigger to perform snapshot when written with '1'", }, { col => undef, table => undef, text => "Controls CRTC1 snapshot" }, { col => "heading", table => 2, text => "D1CRTC_SNAPSHOT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60CC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_AUTO_SNAPSHOT_TRIG_SE" }, { col => 0, table => 2, text => "L" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Determines signal source for auto-snapshot", }, { col => 3, table => 2, text => "00 = auto-snapshot is disabled" }, { col => 3, table => 2, text => "01 = uses CRTC trigger A as trigger event in auto-snapshot ", }, { col => 3, table => 2, text => "mode" }, { col => 3, table => 2, text => "10 = uses CRTC trigger B as trigger event in auto-snapshot ", }, { col => 3, table => 2, text => "mode" }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls snapshot mode for CRTC1", }, { col => "heading", table => 3, text => "D1CRTC_SNAPSHOT_POSITION - RW - 32 bits - [GpuF0MMReg:0x60D0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1CRTC_SNAPSHOT_VERT_COUNT " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Reads back the snapshoted vertical count", }, { col => 0, table => 3, text => "D1CRTC_SNAPSHOT_HORZ_COUNT " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Reads back the snapshoted horizontal count", }, { col => undef, table => undef, text => "Snapshot H and V count for CRTC1", }, { col => undef, table => undef, text => "D1CRTC_SNAPSHOT_FRAME - RW - 32 bits - [GpuF0MMReg:0x60D4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 274, text => [ { col => 0, table => 0, text => "D1CRTC_SNAPSHOT_FRAME_COUNT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => "23:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Reports the snapshoted frame count", }, { col => undef, table => undef, text => "Snapshot frame count of CRTC1" }, { col => "heading", table => 1, text => "D1CRTC_START_LINE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60D8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_PROGRESSIVE_START_LINE" }, { col => 0, table => 1, text => "_EARLY" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "move start_line signal by 1 line eariler in progressive mode", }, { col => 0, table => 1, text => "D1CRTC_INTERLACE_START_LINE_EA" }, { col => 0, table => 1, text => "RLY" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "move start_line signal by 1 line earlier in interlaced timing ", }, { col => undef, table => undef, text => "mode" }, { col => undef, table => undef, text => "move start_line signal earlier by 1 line in CRTC1", }, { col => "heading", table => 2, text => "D1CRTC_INTERRUPT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60DC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_SNAPSHOT_INT_MSK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for CRTC snapshot event" }, { col => 3, table => 2, text => "0 = disables interrupt" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_SNAPSHOT_INT_TYPE" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 2, text => "D1CRTC_V_UPDATE_INT_MSK" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for falling edge of V_UPDATE ^M", }, { col => 3, table => 2, text => "0 = disables interrupt^M" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_V_UPDATE_INT_TYPE" }, { col => 1, table => 2, text => 5 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_INT_M" }, { col => 0, table => 2, text => "SK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for force count now event", }, { col => 3, table => 2, text => "0 = disables interrupt" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_FORCE_COUNT_NOW_INT_T" }, { col => 0, table => 2, text => "YPE" }, { col => 1, table => 2, text => 9 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 2, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 2, text => "INT_MSK" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for force VSYNC next line event", }, { col => 3, table => 2, text => "0 = disables interrupt" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 2, text => "INT_TYPE" }, { col => 1, table => 2, text => 17 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 2, text => "D1CRTC_TRIGA_INT_MSK" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for CRTC external trigger A", }, { col => 3, table => 2, text => "0 = disables interrupt" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_TRIGB_INT_MSK" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Interrupt mask for CRTC external trigger B", }, { col => 3, table => 2, text => "0 = disables interrupt" }, { col => 3, table => 2, text => "1 = enables interrupt" }, { col => 0, table => 2, text => "D1CRTC_TRIGA_INT_TYPE" }, { col => 1, table => 2, text => 26 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 2, text => "D1CRTC_TRIGB_INT_TYPE" }, { col => 1, table => 2, text => 27 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => undef, table => undef, text => "Interrupt mask for CRTC1 events" }, { col => "heading", table => 3, text => "D1MODE_MASTER_UPDATE_LOCK - RW - 32 bits - [GpuF0MMReg:0x60E0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D1MODE_MASTER_UPDATE_LOCK" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Set the master update lock for V_UPDATE signal", }, { col => 3, table => 3, text => "0 = no master lock, V_UPDATE signal will occur", }, { col => 3, table => 3, text => "1 = set master lock to prevent V_UPDATE signal occuring, ", }, { col => undef, table => undef, text => "thus prevent double buffering of display registers", }, { col => undef, table => undef, text => "Master update lock for CRTC1 V_UPDATE signal", }, ], }, { num => 275, text => [ { col => "heading", table => 0, text => "D1MODE_MASTER_UPDATE_MODE - RW - 32 bits - [GpuF0MMReg:0x60E4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1MODE_MASTER_UPDATE_MODE" }, { col => 1, table => 0, text => "2:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the position of the V_UPDATE signal", }, { col => 3, table => 0, text => "000 = V_UPDATE occurs between end of active display ", }, { col => 3, table => 0, text => "region and start line signal" }, { col => 3, table => 0, text => "001 = V_UPDATE occurs at first leading edge of HSYNCA ", }, { col => 3, table => 0, text => "after leading edge of VSYNCA" }, { col => 3, table => 0, text => "010 = V_UPDATE occurs at the leading edge of VSYNC_A", }, { col => 3, table => 0, text => "011 = V_UPDATE occurs at the beginning of the first line of ", }, { col => 3, table => 0, text => "vertical front porch" }, { col => 3, table => 0, text => "100 = V_UPDATE occurs at end of the line before start line ", }, { col => 3, table => 0, text => "Others = Reserved" }, { col => 0, table => 0, text => "D1MODE_MASTER_UPDATE_INTERLA" }, { col => 0, table => 0, text => "CED_MODE" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls generation of V_UPDATE signal in interlaced ", }, { col => 3, table => 0, text => "mode" }, { col => 3, table => 0, text => "00 = generates V_UPDATE at both even and odd field", }, { col => 3, table => 0, text => "01 = generates V_UPDATE only at even field. when ", }, { col => 3, table => 0, text => "D1MODE_MASTER_UPDATE_MODE = 00, V_UPDATE ", }, { col => 3, table => 0, text => "starts at odd field and ends at even field", }, { col => 3, table => 0, text => "10 = generates V_UPDATE only at odd field. when ", }, { col => 3, table => 0, text => "D1MODE_MASTER_UPDATE_MODE = 00, V_UPDATE ", }, { col => 3, table => 0, text => "starts at even field and ends at odd field", }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls the generation of the V_UPDATE signal in CRTC1", }, { col => "heading", table => 1, text => "D1CRTC_UPDATE_LOCK - RW - 32 bits - [GpuF0MMReg:0x60E8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D1CRTC_UPDATE_LOCK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set the lock for CRTC timing registers" }, { col => 3, table => 1, text => "0 = no lock, double buffering can occur" }, { col => undef, table => undef, text => "1 = set lock to prevent double buffering", }, { col => undef, table => undef, text => "Update lock for CRTC1 timing registers", }, { col => "heading", table => 2, text => "D1CRTC_DOUBLE_BUFFER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x60EC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D1CRTC_UPDATE_PENDING (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of double-buffered timing registers in ", }, { col => 3, table => 2, text => "CRTC1" }, { col => 3, table => 2, text => "0 = update has completed" }, { col => 3, table => 2, text => "1 = update is still pending" }, { col => 0, table => 2, text => "D1CRTC_UPDATE_INSTANTLY" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Disables double buffering of CRTC1 timing registers", }, { col => 3, table => 2, text => "0 = enables double buffering" }, { col => 3, table => 2, text => "1 = disables double buffering" }, { col => 0, table => 2, text => "D1CRTC_BLANK_DATA_DOUBLE_BUF" }, { col => 0, table => 2, text => "FER_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the double buffering of " }, { col => 3, table => 2, text => "D1CRTC_BLANK_DATA_EN" }, { col => 3, table => 2, text => "0 = disables double buffering. D1CRTC_BLANK_DATA_EN ", }, { col => 3, table => 2, text => "is updated immediately" }, { col => 3, table => 2, text => "1 = enables double buffering of " }, { col => undef, table => undef, text => "D1CRTC_BLANK_DATA_EN when V_UPDATE is active", }, { col => undef, table => undef, text => "Controls double buffering of CRTC1 registers", }, ], }, { num => 276, text => [ { col => undef, table => undef, text => "2.8.2" }, { col => undef, table => undef, text => "Secondary Display CRTC Control Registers", }, { col => "heading", table => 0, text => "D1CRTC_VGA_PARAMETER_CAPTURE_MODE - RW - 32 bits - [GpuF0MMReg:0x60F0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D1CRTC_VGA_PARAMETER_CAPTUR" }, { col => 0, table => 0, text => "E_MODE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls how VGA timing parameters are captured.", }, { col => 3, table => 0, text => "0: CRTC1 will continuously latch in timing parameters from ", }, { col => 3, table => 0, text => "VGA" }, { col => 3, table => 0, text => "1: CRTC1 will continuously latch in timing parameters from ", }, { col => undef, table => undef, text => "VGA except during VGA parameter recalculated window", }, { col => undef, table => undef, text => "Controls how VGA timing parameters are captured", }, { col => "heading", table => 1, text => "D2CRTC_H_TOTAL - RW - 32 bits - [GpuF0MMReg:0x6800]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_H_TOTAL" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Horizontal total minus one. Sum of display width, overscan ", }, { col => 3, table => 1, text => "left and right, front and back porch and H sync width.", }, { col => 3, table => 1, text => "E.g. for 800 pixels set to 799 = 0x31F" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal dimension of the display timing for CRTC2", }, { col => "heading", table => 2, text => "D2CRTC_H_BLANK_START_END - RW - 32 bits - [GpuF0MMReg:0x6804]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_H_BLANK_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Start of the horizontal blank. The location of the first pixel of ", }, { col => 3, table => 2, text => "horizontal blank, relative to pixel zero. If right overscan ", }, { col => 3, table => 2, text => "border, then blank starts after border ends.", }, { col => 3, table => 2, text => "Double-buffered with " }, { col => 3, table => 2, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 2, text => "D2CRTC_H_BLANK_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "End of the horizontal blank. The location of the next pixel ", }, { col => 3, table => 2, text => "after the last pixel of horizontal blank, relative to pixel zero.", }, { col => 3, table => 2, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal blank region of the display timing for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_H_SYNC_A - RW - 32 bits - [GpuF0MMReg:0x6808]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_H_SYNC_A_START" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "First pixel of horizontal sync A." }, { col => 3, table => 3, text => "In normal cases, it is set to 0. It is only set to non-zero ", }, { col => 3, table => 3, text => "value when we want to test the higher bits of the H counter.", }, { col => 3, table => 3, text => "This register should be ignored and set to 0x0 in VGA ", }, { col => 3, table => 3, text => "timing mode. Hardware does not support odd number ", }, { col => 3, table => 3, text => "value for this register." }, ], }, { num => 277, text => [ { col => 0, table => 0, text => "D2CRTC_H_SYNC_A_END" }, { col => 1, table => 0, text => "28:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Horizontal sync A end. Determines position of the next ", }, { col => 3, table => 0, text => "pixel after last pixel of horizontal sync A. The last pixel of ", }, { col => 3, table => 0, text => "horizontal sync A is D2CRTC_H_SYNC_A_END - 1. The ", }, { col => 3, table => 0, text => "first pixel of horizontal sync A is pixel 0. It should be ", }, { col => 3, table => 0, text => "programmed to a value one greater than the actual last ", }, { col => 3, table => 0, text => "pixel of horizontal sync A." }, { col => 3, table => 0, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines horizontal sync A position for CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_H_SYNC_A_CNTL - RW - 32 bits - [GpuF0MMReg:0x680C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_H_SYNC_A_POL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Polarity of H SYNC A" }, { col => 3, table => 1, text => "0 = active high" }, { col => 3, table => 1, text => "1 = active low" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => 3, table => 1, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 1, text => "D2CRTC_COMP_SYNC_A_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enables composite H sync A" }, { col => 3, table => 1, text => "0 = disabled" }, { col => 3, table => 1, text => "1 = enabled" }, { col => 0, table => 1, text => "D2CRTC_H_SYNC_A_CUTOFF" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Cutoff H sync A at end of H BLANK when end of H sync A is ", }, { col => 3, table => 1, text => "beyond H BLANK" }, { col => 3, table => 1, text => "0 = cutoff is enabled" }, { col => undef, table => undef, text => "1 = cutoff is disabled" }, { col => undef, table => undef, text => "Controls the H SYNC A for CRTC1" }, { col => "heading", table => 2, text => "D2CRTC_H_SYNC_B - RW - 32 bits - [GpuF0MMReg:0x6810]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_H_SYNC_B_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "First pixel of horizontal sync B" }, { col => 0, table => 2, text => "D2CRTC_H_SYNC_B_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Horizontal sync B end. Determines position of the next ", }, { col => 3, table => 2, text => "pixel after last pixel of horizontal sync B. The last pixel of ", }, { col => 3, table => 2, text => "horizontal sync B is D2CRTC_H_SYNC_B_END - 1. This ", }, { col => 3, table => 2, text => "register value is exclusive. It should be programmed to a ", }, { col => 3, table => 2, text => "value one greater than the actual last pixel of horizontal ", }, { col => undef, table => undef, text => "sync B" }, { col => undef, table => undef, text => "Defines the position of horizontal sync B for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_H_SYNC_B_CNTL - RW - 32 bits - [GpuF0MMReg:0x6814]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_H_SYNC_B_POL" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Polarity of H SYNC B" }, { col => 3, table => 3, text => "0 = active high" }, { col => 3, table => 3, text => "1 = active low" }, { col => 0, table => 3, text => "D2CRTC_COMP_SYNC_B_EN" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enables composite H SYNC B" }, { col => 3, table => 3, text => "0 = disabled" }, { col => 3, table => 3, text => "1 = enabled" }, ], }, { num => 278, text => [ { col => 0, table => 0, text => "D2CRTC_H_SYNC_B_CUTOFF" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Cutoff horizontal sync B at end of horizontal blank region ", }, { col => 3, table => 0, text => "when end of H SYNC B is beyond horizontal blank", }, { col => 3, table => 0, text => "0 = cutoff is enabled" }, { col => undef, table => undef, text => "1 = cutoff is disabled" }, { col => undef, table => undef, text => "Controls horizontal sync B for CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_VBI_END - RW - 32 bits - [GpuF0MMReg:0x6818]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_VBI_V_END" }, { col => 1, table => 1, text => "12:0" }, { col => 2, table => 1, text => "0x3" }, { col => 3, table => 1, text => "VBI drops when this number of complete horizontal line ", }, { col => 3, table => 1, text => "remains before the start of v active and ", }, { col => 3, table => 1, text => "D2CRTC_VBI_H_END reached" }, { col => 0, table => 1, text => "D2CRTC_VBI_H_END" }, { col => 1, table => 1, text => "28:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "VBI drops when this number of H pixel remains before the ", }, { col => undef, table => undef, text => "start of v active and D2CRTC_VBI_V_END reached", }, { col => undef, table => undef, text => "VBI goes to CG to tell CG when crtc is in non v active region (i.e. is asserted during VBLANK region + vertical overscan) and is ", }, { col => undef, table => undef, text => "safe to change mclk, VBI can be programmed to be de-asserted earlier than start of v active to prevent CG from changing mclk ", }, { col => undef, table => undef, text => "close to the start v active" }, { col => "heading", table => 2, text => "D2CRTC_V_TOTAL - RW - 32 bits - [GpuF0MMReg:0x6820]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_V_TOTAL" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical total minus one. Sum of vertical active display, top ", }, { col => 3, table => 2, text => "and bottom overscan, front and back porch and vertical ", }, { col => 3, table => 2, text => "sync width." }, { col => 3, table => 2, text => "E.g. for 525 lines set to 524 = 0x20C" }, { col => 3, table => 2, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the vertical dimension of display timing for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_V_BLANK_START_END - RW - 32 bits - [GpuF0MMReg:0x6824]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_V_BLANK_START" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Vertical blank start. Determines the position of the first ", }, { col => 3, table => 3, text => "blank line in a frame. Line 0 is the first line of vertical sync ", }, { col => 3, table => 3, text => "A." }, { col => 3, table => 3, text => "Double-buffered with " }, { col => 3, table => 3, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => 0, table => 3, text => "D2CRTC_V_BLANK_END" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Vertical blank end. Determines the position of the next line ", }, { col => 3, table => 3, text => "after the last line of vertical blank. The last line of vertical ", }, { col => 3, table => 3, text => "blank is D2CRTC_V_BLANK_END - 1." }, { col => 3, table => 3, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the position of the vertical blank region for CRTC2", }, { col => "heading", table => 4, text => "D2CRTC_V_SYNC_A - RW - 32 bits - [GpuF0MMReg:0x6828]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 279, text => [ { col => 0, table => 0, text => "D2CRTC_V_SYNC_A_START" }, { col => 1, table => 0, text => "12:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "The first line of vertical sync A. In normal cases, it is set to ", }, { col => 3, table => 0, text => "0. It is set to non-zero value only when trying to test the ", }, { col => 3, table => 0, text => "higher bits of the vertical counter" }, { col => 0, table => 0, text => "D2CRTC_V_SYNC_A_END" }, { col => 1, table => 0, text => "28:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Vertical sync A end. Determines the position of the next ", }, { col => 3, table => 0, text => "line after the last line of vertical sync A. The last line of ", }, { col => 3, table => 0, text => "vertical sync A is D2CRTC_V_SYNC_A_END - 1. The first ", }, { col => 3, table => 0, text => "line of vertical sync A is line 0. This register value is ", }, { col => 3, table => 0, text => "exclusive. It should be programmed to a value one greater ", }, { col => 3, table => 0, text => "than the actual last line of vertical sync A", }, { col => 3, table => 0, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Defines the position of vertical sync A for CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_V_SYNC_A_CNTL - RW - 32 bits - [GpuF0MMReg:0x682C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_V_SYNC_A_POL" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Polarity of V SYNC A" }, { col => 3, table => 1, text => "0 = active high" }, { col => 3, table => 1, text => "1 = active low" }, { col => 3, table => 1, text => "Double-buffered with " }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => undef, table => undef, text => "Controls V SYNC A for CRTC2" }, { col => "heading", table => 2, text => "D2CRTC_V_SYNC_B - RW - 32 bits - [GpuF0MMReg:0x6830]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_V_SYNC_B_START" }, { col => 1, table => 2, text => "12:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical sync B start. Determines the position of the first ", }, { col => 3, table => 2, text => "line of vertical sync B." }, { col => 0, table => 2, text => "D2CRTC_V_SYNC_B_END" }, { col => 1, table => 2, text => "28:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Vertical sync B end. Determines the position of the next ", }, { col => 3, table => 2, text => "line after the last line of vertical sync B. Last line of vertical ", }, { col => 3, table => 2, text => "sync B is D2CRTC_V_SYNC_B_END - 1. This register ", }, { col => 3, table => 2, text => "value is exclusive. It should be programmed to a value one ", }, { col => undef, table => undef, text => "greater than the actual last line of vertical sync B", }, { col => undef, table => undef, text => "Defines the position of vertical sync B for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_V_SYNC_B_CNTL - RW - 32 bits - [GpuF0MMReg:0x6834]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_V_SYNC_B_POL" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Controls polarity of vertical sync B" }, { col => 3, table => 3, text => "0 = active high" }, { col => undef, table => undef, text => "1 = active low" }, { col => undef, table => undef, text => "Controls vertical sync B for CRTC2", }, { col => "heading", table => 4, text => "D2CRTC_TRIGA_CNTL - RW - 32 bits - [GpuF0MMReg:0x6860]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, ], }, { num => 280, text => [ { col => 0, table => 0, text => "D2CRTC_TRIGA_SOURCE_SELECT" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select source of input signals for external trigger A", }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = VSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = HSYNCA from another CRTC of the chip", }, { col => 3, table => 0, text => "3 = VSYNCB from another CRTC of the chip", }, { col => 3, table => 0, text => "4 = HSYNCB from another CRTC of the chip", }, { col => 3, table => 0, text => "5 = GENERICA pin" }, { col => 3, table => 0, text => "6 = GENERICB pin" }, { col => 3, table => 0, text => "7 = VSYNCA pin" }, { col => 3, table => 0, text => "8 = HSYNCA pin" }, { col => 3, table => 0, text => "9 = VSYNCB pin" }, { col => 3, table => 0, text => "10 = HSYNCB pin" }, { col => 3, table => 0, text => "11 = HPD1 pin" }, { col => 3, table => 0, text => "12 = HPD2 pin" }, { col => 3, table => 0, text => "13 = DVALID pin" }, { col => 3, table => 0, text => "14 = PSYNC pin" }, { col => 3, table => 0, text => "15 = Video capture complete signal from VIP", }, { col => 0, table => 0, text => "D2CRTC_TRIGA_POLARITY_SELECT" }, { col => 1, table => 0, text => "6:4" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects source of input signal from polarity of external ", }, { col => 3, table => 0, text => "trigger A" }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = interlace polarity from another CRTC of the chip", }, { col => 3, table => 0, text => "2 = GENERICA pin" }, { col => 3, table => 0, text => "3 = GENERICB pin" }, { col => 3, table => 0, text => "4 = HSYNCA pin" }, { col => 3, table => 0, text => "5 = HSYNCB pin" }, { col => 3, table => 0, text => "6 = video capture polarity input from VIP", }, { col => 3, table => 0, text => "7 = DVALID pin" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_RESYNC_BYPASS_E" }, { col => 0, table => 0, text => "N" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Bypass the resync logic for the external trigger A signal and ", }, { col => 3, table => 0, text => "its polarity input signal" }, { col => 3, table => 0, text => "0 = do not bypass" }, { col => 3, table => 0, text => "1 = bypass the resync logic" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_INPUT_STATUS (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read back the value of the external trigger A input signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_POLARITY_STATUS " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the value of the external trigger A polarity signal ", }, { col => 3, table => 0, text => "after the mux" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_OCCURRED (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports whether external trigger A has occurred. A sticky ", }, { col => 3, table => 0, text => "bit." }, { col => 3, table => 0, text => "0 = has not occurred" }, { col => 3, table => 0, text => "1 = has occurred" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_RISING_EDGE_DETE" }, { col => 0, table => 0, text => "CT_CNTL" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of rising edge of the external trigger ", }, { col => 3, table => 0, text => "A signal" }, { col => 3, table => 0, text => "00 = do not detect rising edge" }, { col => 3, table => 0, text => "01 = always detect rising edge" }, { col => 3, table => 0, text => "10 = detect rising edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect rising edge only when field polarity is high", }, { col => 0, table => 0, text => "D2CRTC_TRIGA_FALLING_EDGE_DET" }, { col => 0, table => 0, text => "ECT_CNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of falling edge of external trigger A ", }, { col => 3, table => 0, text => "signal" }, { col => 3, table => 0, text => "00 = do not detect falling edge" }, { col => 3, table => 0, text => "01 = always detect falling edge" }, { col => 3, table => 0, text => "10 = detect falling edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect falling edge only when field polarity is high", }, { col => 0, table => 0, text => "D2CRTC_TRIGA_FREQUENCY_SELEC" }, { col => 0, table => 0, text => "T" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines the frequency of the external trigger A signal", }, { col => 3, table => 0, text => "00 = send every signal" }, { col => 3, table => 0, text => "01 = send every 2 signals" }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = send every 4 signals" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_DELAY" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "A programmable delay to send external trigger A signal", }, { col => 0, table => 0, text => "D2CRTC_TRIGA_CLEAR (W)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the sticky bit D2CRTC_TRIGA_OCCURRED when ", }, { col => undef, table => undef, text => "written with '1'" }, { col => undef, table => undef, text => "Controls for external trigger A signal in CRTC2", }, ], }, { num => 281, text => [ { col => "heading", table => 0, text => "D2CRTC_TRIGA_MANUAL_TRIG - RW - 32 bits - [GpuF0MMReg:0x6864]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CRTC_TRIGA_MANUAL_TRIG (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "One shot trigger for external trigger A signal when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual trigger for external trigger A signal of CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_TRIGB_CNTL - RW - 32 bits - [GpuF0MMReg:0x6868]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_SOURCE_SELECT" }, { col => 1, table => 1, text => "3:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select source of input signals for external trigger B", }, { col => 3, table => 1, text => "0 = logic 0" }, { col => 3, table => 1, text => "1 = VSYNCA from another CRTC of the chip", }, { col => 3, table => 1, text => "2 = HSYNCA from another CRTC of the chip", }, { col => 3, table => 1, text => "3 = VSYNCB from another CRTC of the chip", }, { col => 3, table => 1, text => "4 = HSYNCB from another CRTC of the chip", }, { col => 3, table => 1, text => "5 = GENERICA pin" }, { col => 3, table => 1, text => "6 = GENERICB pin" }, { col => 3, table => 1, text => "7 = VSYNCA pin" }, { col => 3, table => 1, text => "8 = HSYNCA pin" }, { col => 3, table => 1, text => "9 = VSYNCB pin" }, { col => 3, table => 1, text => "10 = HSYNCB pin" }, { col => 3, table => 1, text => "11 = HPD1 pin" }, { col => 3, table => 1, text => "12 = HPD2 pin" }, { col => 3, table => 1, text => "13 = DVALID pin" }, { col => 3, table => 1, text => "14 = PSYNC pin" }, { col => 3, table => 1, text => "15 = Video capture complete signal from VIP", }, { col => 0, table => 1, text => "D2CRTC_TRIGB_POLARITY_SELECT" }, { col => 1, table => 1, text => "6:4" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selects source of input signal from polarity of external ", }, { col => 3, table => 1, text => "trigger B" }, { col => 3, table => 1, text => "0 = logic 0" }, { col => 3, table => 1, text => "1 = interlace polarity from another CRTC of the chip", }, { col => 3, table => 1, text => "2 = GENERICA pin" }, { col => 3, table => 1, text => "3 = GENERICB pin" }, { col => 3, table => 1, text => "4 = HSYNCA pin" }, { col => 3, table => 1, text => "5 = HSYNCB pin" }, { col => 3, table => 1, text => "6 = video capture polarity input from VIP", }, { col => 3, table => 1, text => "7 = DVALID pin" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_RESYNC_BYPASS_E" }, { col => 0, table => 1, text => "N" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bypass the resync logic for the external trigger B signal and ", }, { col => 3, table => 1, text => "its polarity input signal" }, { col => 3, table => 1, text => "0 = do not bypass" }, { col => 3, table => 1, text => "1 = bypass the resync logic" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_INPUT_STATUS (R)" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Read back the value of the external trigger B input signal ", }, { col => 3, table => 1, text => "after the mux" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_POLARITY_STATUS " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 10 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports the value of the external trigger B polarity signal ", }, { col => 3, table => 1, text => "after the mux" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_OCCURRED (R)" }, { col => 1, table => 1, text => 11 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether external trigger B has occurred. A sticky ", }, { col => 3, table => 1, text => "bit." }, { col => 3, table => 1, text => "0 = has not occurred" }, { col => 3, table => 1, text => "1 = has occurred" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_RISING_EDGE_DETE" }, { col => 0, table => 1, text => "CT_CNTL" }, { col => 1, table => 1, text => "13:12" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls the detection of rising edge of the external trigger ", }, { col => 3, table => 1, text => "B signal" }, { col => 3, table => 1, text => "00 = do not detect rising edge" }, { col => 3, table => 1, text => "01 = always detect rising edge" }, { col => 3, table => 1, text => "10 = detect rising edge only when field polarity is low", }, { col => 3, table => 1, text => "11 = detect rising edge only when field polarity is high", }, ], }, { num => 282, text => [ { col => 0, table => 0, text => "D2CRTC_TRIGB_FALLING_EDGE_DET" }, { col => 0, table => 0, text => "ECT_CNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls the detection of falling edge of external trigger B ", }, { col => 3, table => 0, text => "signal" }, { col => 3, table => 0, text => "00 = do not detect falling edge" }, { col => 3, table => 0, text => "01 = always detect falling edge" }, { col => 3, table => 0, text => "10 = detect falling edge only when field polarity is low", }, { col => 3, table => 0, text => "11 = detect falling edge only when field polarity is high", }, { col => 0, table => 0, text => "D2CRTC_TRIGB_FREQUENCY_SELEC" }, { col => 0, table => 0, text => "T" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines the frequency of the external trigger B signal", }, { col => 3, table => 0, text => "00 = send every signal" }, { col => 3, table => 0, text => "01 = send every 2 signals" }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = send every 4 signals" }, { col => 0, table => 0, text => "D2CRTC_TRIGB_DELAY" }, { col => 1, table => 0, text => "28:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "A programmable delay to send external trigger B signal", }, { col => 0, table => 0, text => "D2CRTC_TRIGB_CLEAR (W)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Clears the sticky bit D2CRTC_TRIGB_OCCURRED when ", }, { col => undef, table => undef, text => "written with '1'" }, { col => undef, table => undef, text => "Control for external trigger B signal of CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_TRIGB_MANUAL_TRIG - RW - 32 bits - [GpuF0MMReg:0x686C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_MANUAL_TRIG (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "One shot trigger for external trigger B signal when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual trigger for external trigger B signal of CRTC2", }, { col => "heading", table => 2, text => "D2CRTC_FORCE_COUNT_NOW_CNTL - RW - 32 bits - [GpuF0MMReg:0x6870]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_FORCE_COUNT_NOW_MODE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls which timing counter is forced" }, { col => 3, table => 2, text => "0 = force counter now mode is disabled" }, { col => 3, table => 2, text => "1 = force H count now to H_TOTAL only" }, { col => 3, table => 2, text => "2 = force H count to H_TOTAL and V count to V_TOTAL in ", }, { col => 3, table => 2, text => "progressive mode and V_TOTAL-1 in interlaced mode", }, { col => 3, table => 2, text => "3 = reserved" }, { col => 0, table => 2, text => "D2CRTC_FORCE_COUNT_NOW_TRIG_" }, { col => 0, table => 2, text => "SEL" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Selects the trigger signal as force count now trigger", }, { col => 3, table => 2, text => "0 = selects CRTC_TRIG_A and CRTC_TRIG_A_POL", }, { col => 3, table => 2, text => "1 = selects CRTC_TRIG_B and CRTC_TRIG_B_POL", }, { col => 0, table => 2, text => "D2CRTC_FORCE_COUNT_NOW_OCCU" }, { col => 0, table => 2, text => "RRED (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of force count now, a sticky bit.", }, { col => 3, table => 2, text => "0 = CRTC force count now has not occurred", }, { col => 3, table => 2, text => "1 = CRTC force count now has occurred" }, { col => 0, table => 2, text => "D2CRTC_FORCE_COUNT_NOW_CLEA" }, { col => 0, table => 2, text => "R (W)" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Resets D2CRTC_FORCE_COUNT_NOW_OCCURRED " }, { col => undef, table => undef, text => "when written with '1'" }, { col => undef, table => undef, text => "Controls CRTC2 force count now logic", }, { col => "heading", table => 3, text => "D2CRTC_FLOW_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6874]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, ], }, { num => 283, text => [ { col => 0, table => 0, text => "D2CRTC_FLOW_CONTROL_SOURCE_" }, { col => 0, table => 0, text => "SELECT" }, { col => 1, table => 0, text => "4:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Selects the signal used for flow control in CRTC2", }, { col => 3, table => 0, text => "0 = logic 0" }, { col => 3, table => 0, text => "1 = GENERICA pin" }, { col => 3, table => 0, text => "2 = GENERICB pin" }, { col => 3, table => 0, text => "3 = HPD1 pin" }, { col => 3, table => 0, text => "4 = HPD2 pin" }, { col => 3, table => 0, text => "5 = DDC1DATA pin" }, { col => 3, table => 0, text => "6 = DDC1CLK pin" }, { col => 3, table => 0, text => "7 = DDC2DATA pin" }, { col => 3, table => 0, text => "8 = DDC2CLK pin" }, { col => 3, table => 0, text => "9 = DVOCLK(1) pin" }, { col => 3, table => 0, text => "10 = VHAD(0] pin" }, { col => 3, table => 0, text => "11 = VHAD[1] pin" }, { col => 3, table => 0, text => "12 = VPHCTL pin" }, { col => 3, table => 0, text => "13 = VIPCLK pin" }, { col => 3, table => 0, text => "14 = DVALID pin" }, { col => 3, table => 0, text => "15 = PSYNC pin" }, { col => 3, table => 0, text => "16 = a GPIO pin for dual-GPU, TBD" }, { col => 0, table => 0, text => "D2CRTC_FLOW_CONTROL_POLARITY" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the status of force count now, a sticky bit.", }, { col => 3, table => 0, text => "0 = CRTC force count now has not occurred", }, { col => 3, table => 0, text => "1 = CRTC force count now has occurred" }, { col => 0, table => 0, text => "D2CRTC_FLOW_CONTROL_GRANULA" }, { col => 0, table => 0, text => "RITY" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls at which pixel position flow control can start to ", }, { col => 3, table => 0, text => "happen" }, { col => 3, table => 0, text => "0 = flow control only start to happen on odd-even pixel ", }, { col => 3, table => 0, text => "boundary" }, { col => 3, table => 0, text => "1 = flow control can start at any pixel position", }, { col => 0, table => 0, text => "D2CRTC_FLOW_CONTROL_INPUT_ST" }, { col => 0, table => 0, text => "ATUS (R)" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reports the value of the flow control input signal", }, { col => 3, table => 0, text => "0 = output of source mux of flow control signal is low", }, { col => undef, table => undef, text => "1 = output of source mux of flow control signal is high", }, { col => undef, table => undef, text => "Controls flow control of CRTC2" }, { col => "heading", table => 1, text => "D2CRTC_PIXEL_DATA_READBACK - RW - 32 bits - [GpuF0MMReg:0x6878]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_PIXEL_DATA_BLUE_CB (R)" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "B/Cb component sent to DISPOUT" }, { col => 0, table => 1, text => "D2CRTC_PIXEL_DATA_GREEN_Y (R)" }, { col => 1, table => 1, text => "19:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "G/Y component sent to DISPOUT" }, { col => 0, table => 1, text => "D2CRTC_PIXEL_DATA_RED_CR (R)" }, { col => 1, table => 1, text => "29:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "R/Cr component sent to DISPOUT" }, { col => undef, table => undef, text => "Read back of the CRTC2 pixel data sent to DISPOUT. This is a debug register. Intended for use in one shot clocking mode.", }, { col => "heading", table => 2, text => "D2CRTC_STEREO_FORCE_NEXT_EYE - RW - 32 bits - [GpuF0MMReg:0x687C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_STEREO_FORCE_NEXT_EYE " }, { col => 0, table => 2, text => "(W)" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Force next frame eye view - One shot." }, { col => 3, table => 2, text => "00: No force - next eye opposite of current eye", }, { col => 3, table => 2, text => "01: Right eye force - force right eye next field/frame", }, { col => 3, table => 2, text => "10: Left eye force - force right eye next field/frame", }, { col => 3, table => 2, text => "11: Reserved" }, { col => 3, table => 2, text => " After a force has occured, readback of this register will be ", }, { col => undef, table => undef, text => "00" }, { col => undef, table => undef, text => "Force Next Eye register" }, ], }, { num => 284, text => [ { col => "heading", table => 0, text => "D2CRTC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6880]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CRTC_MASTER_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables/Disables CRTC2. H counter is at H_TOTAL and V ", }, { col => 3, table => 0, text => "counter is at first line of blank when CRTC is disabled.", }, { col => 3, table => 0, text => "0 = disabled" }, { col => 3, table => 0, text => "1 = enabled" }, { col => 0, table => 0, text => "D2CRTC_SYNC_RESET_SEL" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Allows power management to lower CRTC2 enable.", }, { col => 0, table => 0, text => "D2CRTC_DISABLE_POINT_CNTL" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "When D2CRTC_MASTER_EN is set to 0, delay the ", }, { col => 3, table => 0, text => "disabling of CRTC2 until certain point within the frame", }, { col => 3, table => 0, text => "00 = disable CRTC immediately" }, { col => 3, table => 0, text => "01 = delay disable CRTC until the end of the current line", }, { col => 3, table => 0, text => "10 = reserved" }, { col => 3, table => 0, text => "11 = delay disable CRTC until end of the first line in the ", }, { col => 3, table => 0, text => "vertical blank region" }, { col => 0, table => 0, text => "D2CRTC_CURRENT_MASTER_EN_STA" }, { col => 0, table => 0, text => "TE (R)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Read-only field indicates the current status of the timing ", }, { col => 3, table => 0, text => "generator. Can be used to poll for when a delayed disable ", }, { col => 3, table => 0, text => "takes effect." }, { col => 3, table => 0, text => "0 = CRTC is disabled" }, { col => 3, table => 0, text => "1 = CRTC is enabled" }, { col => 0, table => 0, text => "D2CRTC_DISP_READ_REQUEST_DISA" }, { col => 0, table => 0, text => "BLE" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Disables data read request from the display controller. Can ", }, { col => 3, table => 0, text => "be used to stop display reads from system memory but ", }, { col => 3, table => 0, text => "keep display timing generation running. Has no effect if ", }, { col => 3, table => 0, text => "CRTC is disabled." }, { col => 3, table => 0, text => "0 = do not disable data read request" }, { col => 3, table => 0, text => "1 = disable data read request" }, { col => 0, table => 0, text => "D2CRTC_PREFETCH_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Double buffered. Enable data prefetch for display 1", }, { col => 3, table => 0, text => "0 = do not enable prefetch" }, { col => 3, table => 0, text => "1 = enable data prefetch" }, { col => 0, table => 0, text => "D2CRTC_SOF_PULL_EN" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "At SOF, LB level can be set a a programmable value ", }, { col => 3, table => 0, text => "(D2MODE_SOF_READ_PT), which is the point LB can ", }, { col => 3, table => 0, text => "make requests to. Between SOF to active line, CRTC ", }, { col => 3, table => 0, text => "needs to pull scaler/LB so that LB can make data requests ", }, { col => 3, table => 0, text => "beyond that programmable point. " }, { col => 3, table => 0, text => "0 = do not enable pulling" }, { col => undef, table => undef, text => "1 = enable pulling" }, { col => undef, table => undef, text => "Controls CRTC2 timing generator and data read request to display2", }, { col => undef, table => undef, text => "D2CRTC_BLANK_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6884]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_CURRENT_BLANK_STATE (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Read only status indicating current state of display ", }, { col => undef, table => undef, text => "blanking." }, { col => undef, table => undef, text => "0 = screen not blanked" }, { col => undef, table => undef, text => "1 = screen is blanked" }, { col => undef, table => undef, text => "D2CRTC_BLANK_DATA_EN" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable for blanking active display area. The active area of ", }, { col => undef, table => undef, text => "display that is forced will use the ", }, { col => undef, table => undef, text => "D2CRTC_BLACK_COLOR value." }, { col => undef, table => undef, text => "This field is optionally double buffered with ", }, { col => undef, table => undef, text => "D2CRTC_BLANK_DATA_DOUBLE_BUFFER_EN.", }, { col => undef, table => undef, text => "0 = disable blanking" }, { col => undef, table => undef, text => "1 = enable blanking" }, ], }, { num => 285, text => [ { col => 0, table => 0, text => "D2CRTC_BLANK_DE_MODE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether BLANK and DATA_ACTIVE signal ", }, { col => 3, table => 0, text => "keeps toggling when screen is blank" }, { col => 3, table => 0, text => "0 = toggles BLANK and DATA_ACTIVE" }, { col => undef, table => undef, text => "1 = keep BLANK active and DATA_ACTIVE inactive", }, { col => undef, table => undef, text => "Controls forced blanking of active area of display timing. Useful for display mode switches when corrupted image may be ", }, { col => undef, table => undef, text => "generated for a frame or two." }, { col => undef, table => undef, text => "D2CRTC_INTERLACE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x6888]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_INTERLACE_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables interlaced timing" }, { col => undef, table => undef, text => "0 = Progressive timing" }, { col => undef, table => undef, text => "1 = Interlaced timing" }, { col => undef, table => undef, text => "D2CRTC_INTERLACE_FORCE_NEXT_F" }, { col => undef, table => undef, text => "IELD (W)" }, { col => undef, table => undef, text => "17:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "One shot force next field polarity when written", }, { col => undef, table => undef, text => "00 = does not force next field" }, { col => undef, table => undef, text => "01 = force only next field to odd", }, { col => undef, table => undef, text => "10 = force only next field to even", }, { col => undef, table => undef, text => "11 = does not force next field" }, { col => undef, table => undef, text => "Interlaced timing control for CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_INTERLACE_STATUS - RW - 32 bits - [GpuF0MMReg:0x688C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_INTERLACE_CURRENT_FIEL" }, { col => 0, table => 1, text => "D (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports the polarity of current field" }, { col => 3, table => 1, text => "0 = even" }, { col => 3, table => 1, text => "1 = odd" }, { col => 0, table => 1, text => "D2CRTC_INTERLACE_NEXT_FIELD (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports the polarity of the next field. Normally the opposite ", }, { col => 3, table => 1, text => "of the current field. When " }, { col => 3, table => 1, text => "D2CRTC_INTERLACE_FORCE_NEXT_FIELD is used to ", }, { col => 3, table => 1, text => "force polarity of next field, then next field can match current ", }, { col => 3, table => 1, text => "field." }, { col => 3, table => 1, text => "0 = even" }, { col => undef, table => undef, text => "1 = odd" }, { col => undef, table => undef, text => "Read-only register reports the polarity of the current and next field for interlaced timing", }, { col => "heading", table => 2, text => "D2CRTC_BLANK_DATA_COLOR - RW - 32 bits - [GpuF0MMReg:0x6890]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_BLANK_DATA_COLOR_BLUE" }, { col => 0, table => 2, text => "_CB" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "B / Cb component" }, { col => 0, table => 2, text => "D2CRTC_BLANK_DATA_COLOR_GREE" }, { col => 0, table => 2, text => "N_Y" }, { col => 1, table => 2, text => "19:10" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "G / Y component" }, { col => 0, table => 2, text => "D2CRTC_BLANK_DATA_COLOR_RED_" }, { col => 0, table => 2, text => "CR" }, { col => 1, table => 2, text => "29:20" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "R / Cr component" }, { col => undef, table => undef, text => "Set the color for pixels in blank region", }, ], }, { num => 286, text => [ { col => "heading", table => 0, text => "D2CRTC_OVERSCAN_COLOR - RW - 32 bits - [GpuF0MMReg:0x6894]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CRTC_OVERSCAN_COLOR_BLUE" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "B or Cb component" }, { col => 0, table => 0, text => "D2CRTC_OVERSCAN_COLOR_GREEN" }, { col => 1, table => 0, text => "19:10" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "G or Y component" }, { col => 0, table => 0, text => "D2CRTC_OVERSCAN_COLOR_RED" }, { col => 1, table => 0, text => "29:20" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "R or Cr component" }, { col => undef, table => undef, text => "Defines color of the overscan region for CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_BLACK_COLOR - RW - 32 bits - [GpuF0MMReg:0x6898]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_BLACK_COLOR_B_CB" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "B / Cb component of the black color" }, { col => 0, table => 1, text => "D2CRTC_BLACK_COLOR_G_Y" }, { col => 1, table => 1, text => "19:10" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "G / Y component of the black color" }, { col => 0, table => 1, text => "D2CRTC_BLACK_COLOR_R_CR" }, { col => 1, table => 1, text => "29:20" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "R / Cr component of the black color", }, { col => undef, table => undef, text => "Black color applied to the active display region when blanking the screen", }, { col => "heading", table => 2, text => "D2CRTC_STATUS - RW - 32 bits - [GpuF0MMReg:0x689C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_V_BLANK (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside vertical blank region" }, { col => 3, table => 2, text => "1 = within vertical blank region" }, { col => 0, table => 2, text => "D2CRTC_V_ACTIVE_DISP (R)" }, { col => 1, table => 2, text => 1 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside vertical active display region", }, { col => 3, table => 2, text => "1 = within vertical active display region", }, { col => 0, table => 2, text => "D2CRTC_V_SYNC_A (R)" }, { col => 1, table => 2, text => 2 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside VSYNC" }, { col => 3, table => 2, text => "1 = within VSYNC" }, { col => 0, table => 2, text => "D2CRTC_V_UPDATE (R)" }, { col => 1, table => 2, text => 3 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside the V_UPDATE region" }, { col => 3, table => 2, text => "1 = within the V_UPDATE region (between end of vertical ", }, { col => 3, table => 2, text => "active display and start_line]" }, { col => 0, table => 2, text => "D2CRTC_V_START_LINE (R)" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current vertical position" }, { col => 3, table => 2, text => "0 = outside start_line region" }, { col => 3, table => 2, text => "1 = within start_line region" }, { col => 0, table => 2, text => "D2CRTC_H_BLANK (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal position" }, { col => 3, table => 2, text => "0 = outside horizontal blank region" }, { col => 3, table => 2, text => "1 = within horizontal blank region" }, { col => 0, table => 2, text => "D2CRTC_H_ACTIVE_DISP (R)" }, { col => 1, table => 2, text => 17 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal region" }, { col => 3, table => 2, text => "0 = outside horizontal active display region", }, { col => 3, table => 2, text => "1 = within horizontal active display region", }, { col => 0, table => 2, text => "D2CRTC_H_SYNC_A (R)" }, { col => 1, table => 2, text => 18 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Current horizontal position" }, { col => 3, table => 2, text => "0 = outside horizontal sync" }, { col => undef, table => undef, text => "1 = within horizontal sync" }, { col => undef, table => undef, text => "Reports the position of CRTC2" }, { col => "heading", table => 3, text => "D2CRTC_STATUS_POSITION - RW - 32 bits - [GpuF0MMReg:0x68A0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_VERT_COUNT (R)" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Reports current vertical count" }, { col => 0, table => 3, text => "D2CRTC_HORZ_COUNT (R)" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Reports current horizontal count", }, { col => undef, table => undef, text => "Current horizontal and vertical count of CRTC2", }, ], }, { num => 287, text => [ { col => "heading", table => 0, text => "D2CRTC_STATUS_FRAME_COUNT - RW - 32 bits - [GpuF0MMReg:0x68A4]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CRTC_FRAME_COUNT (R)" }, { col => 1, table => 0, text => "23:0" }, { col => 2, table => 0, text => "0x0" }, { col => undef, table => undef, text => "Reports current frame count" }, { col => undef, table => undef, text => "Current frame count for CRTC2" }, { col => "heading", table => 1, text => "D2CRTC_STATUS_VF_COUNT - RW - 32 bits - [GpuF0MMReg:0x68A8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_VF_COUNT (R)" }, { col => 1, table => 1, text => "28:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Reports current vertical and frame count", }, { col => undef, table => undef, text => "Current composite vertical and frame count for CRTC2", }, { col => "heading", table => 2, text => "D2CRTC_STATUS_HV_COUNT - RW - 32 bits - [GpuF0MMReg:0x68AC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_HV_COUNT (R)" }, { col => 1, table => 2, text => "28:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Reports current horizontal and vertical count", }, { col => undef, table => undef, text => "Current composite H/V count of CRTC2", }, { col => undef, table => undef, text => "D2CRTC_COUNT_RESET - RW - 32 bits - [GpuF0MMReg:0x68B0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_RESET_FRAME_COUNT (W)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "One-shot reset of frame counter of CRTC2 when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Resets CRTC2 counters" }, { col => "heading", table => 3, text => "D2CRTC_COUNT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68B4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_HORZ_COUNT_BY2_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Set to 1 for DVI 30bpp mode only, set to 0 otherwise", }, { col => 0, table => 3, text => "D2CRTC_HORZ_REPETITION_COUNT" }, { col => 1, table => 3, text => "7:4" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Enable horizontal repetition. CRTC increments the H ", }, { col => 3, table => 3, text => "counter every (COUNT+1) pixel clocks" }, { col => 3, table => 3, text => "0 = every clock" }, { col => 3, table => 3, text => "1 = every 2 clocks" }, { col => 3, table => 3, text => "2 = every 3 clocks" }, { col => undef, table => undef, text => "etc" }, { col => undef, table => undef, text => "Controls the counters in CRTC2" }, ], }, { num => 288, text => [ { col => "heading", table => 0, text => "D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE - RW - 32 bits - [GpuF0MMReg:0x68B8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "D2CRTC_MANUAL_FORCE_VSYNC_NE" }, { col => 0, table => 0, text => "XT_LINE (W)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "One shot force VSYNCA to happen next line when written ", }, { col => undef, table => undef, text => "with '1'" }, { col => undef, table => undef, text => "Manual force of VSYNC to happen next line", }, { col => "heading", table => 1, text => "D2CRTC_VERT_SYNC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68BC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports whether force vsync next line event has occurred. ", }, { col => 3, table => 1, text => "Sticky bit." }, { col => 3, table => 1, text => "0 = event has not occurred" }, { col => 3, table => 1, text => "1 = event has occurred" }, { col => 0, table => 1, text => "D2CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "CLEAR (W)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "One shot clear to the sticky bit " }, { col => 3, table => 1, text => "D1CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED " }, { col => 3, table => 1, text => "when written with '1'" }, { col => 0, table => 1, text => "D2CRTC_AUTO_FORCE_VSYNC_MOD" }, { col => 0, table => 1, text => "E" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selection of auto mode for forcing vsync next line", }, { col => 3, table => 1, text => "00 = disables auto mode" }, { col => 3, table => 1, text => "01 = force VSYNC next line on CRTC trigger A signal", }, { col => 3, table => 1, text => "10 = force VSYNC next line on CRTC trigger B signal", }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls the feature to force VSYNC next line for CRTC2", }, { col => "heading", table => 2, text => "D2CRTC_STEREO_STATUS - RW - 32 bits - [GpuF0MMReg:0x68C0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_STEREO_CURRENT_EYE (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the polarity of the current frame/field", }, { col => 3, table => 2, text => "0 = right eye image" }, { col => 3, table => 2, text => "1 = left eye image" }, { col => 0, table => 2, text => "D2CRTC_STEREO_SYNC_OUTPUT (R)" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports current value of STEREOSYNC signal", }, { col => 0, table => 2, text => "D2CRTC_STEREO_SYNC_SELECT (R)" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports current value of SYNC_SELECT signal", }, { col => 0, table => 2, text => "D2CRTC_STEREO_FORCE_NEXT_EYE" }, { col => 0, table => 2, text => "_PENDING (R)" }, { col => 1, table => 2, text => "25:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of " }, { col => 3, table => 2, text => "D2CRTC_STEREO_FORCE_NEXT_EYE write." }, { col => 3, table => 2, text => "00: No force pending" }, { col => 3, table => 2, text => "01: Right force pending" }, { col => 3, table => 2, text => "10: Left force pending" }, { col => undef, table => undef, text => "11: Reserved" }, { col => undef, table => undef, text => "Reports CRTC2 status in stereoscopic display", }, { col => undef, table => undef, text => "D2CRTC_STEREO_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68C4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_STEREO_SYNC_OUTPUT_PO" }, { col => undef, table => undef, text => "LARITY" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls polarity of the stereosync signal", }, { col => undef, table => undef, text => "0 = 0 means right eye image and 1 means left eye image", }, { col => undef, table => undef, text => "1 = 0 means left eye image and 1 means right eye image", }, { col => undef, table => undef, text => "D2CRTC_STEREO_SYNC_SELECT_PO" }, { col => undef, table => undef, text => "LARITY" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls polarity of STEREO_SELECT signal sent to scaler", }, { col => undef, table => undef, text => "0 = 0 means right eye image and 1 means left eye image", }, { col => undef, table => undef, text => "1 = 0 means left eye image and 1 means right eye image", }, ], }, { num => 289, text => [ { col => 0, table => 0, text => "D2CRTC_STEREO_EN" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables toggling of STEREOSYNC and STEREO_SELECT ", }, { col => 3, table => 0, text => "signals" }, { col => 3, table => 0, text => "0 = disable toggling." }, { col => 3, table => 0, text => "1 = enable toggling at every frame (progressive) or every ", }, { col => undef, table => undef, text => "field (interlace) at leading edge of VSYNCA", }, { col => undef, table => undef, text => "Stereosync control for CRTC2" }, { col => "heading", table => 1, text => "D2CRTC_SNAPSHOT_STATUS - RW - 32 bits - [GpuF0MMReg:0x68C8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_SNAPSHOT_OCCURRED (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reports status of snapshot. A sticky bit to be cleared by ", }, { col => 3, table => 1, text => "writing 1 to D2CRTC_SNAPSHOT_CLEAR" }, { col => 3, table => 1, text => "0 = snapshot has not occurred" }, { col => 3, table => 1, text => "1 = snapshot has occurred" }, { col => 0, table => 1, text => "D2CRTC_SNAPSHOT_CLEAR (W)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Clears the D2CRTC_SNAPSHOT_OCCURRED sticky bit ", }, { col => 3, table => 1, text => "when written with '1'" }, { col => 0, table => 1, text => "D2CRTC_SNAPSHOT_MANUAL_TRIGG" }, { col => 0, table => 1, text => "ER (W)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "One shot trigger to perform snapshot when written with '1'", }, { col => undef, table => undef, text => "Controls CRTC2 snapshot" }, { col => "heading", table => 2, text => "D2CRTC_SNAPSHOT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68CC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_AUTO_SNAPSHOT_TRIG_SE" }, { col => 0, table => 2, text => "L" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Determines signal source for auto-snapshot", }, { col => 3, table => 2, text => "00 = auto-snapshot is disabled" }, { col => 3, table => 2, text => "01 = uses CRTC trigger A as trigger event in auto-snapshot ", }, { col => 3, table => 2, text => "mode" }, { col => 3, table => 2, text => "10 = uses CRTC trigger B as trigger event in auto-snapshot ", }, { col => 3, table => 2, text => "mode" }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls snapshot mode for CRTC2", }, { col => "heading", table => 3, text => "D2CRTC_SNAPSHOT_POSITION - RW - 32 bits - [GpuF0MMReg:0x68D0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_SNAPSHOT_VERT_COUNT " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => "12:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Reads back the snapshoted vertical count", }, { col => 0, table => 3, text => "D2CRTC_SNAPSHOT_HORZ_COUNT " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => "28:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Reads back the snapshoted horizontal count", }, { col => undef, table => undef, text => "Snapshot H and V count for CRTC2", }, { col => undef, table => undef, text => "D2CRTC_SNAPSHOT_FRAME - RW - 32 bits - [GpuF0MMReg:0x68D4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_SNAPSHOT_FRAME_COUNT " }, { col => undef, table => undef, text => "(R)" }, { col => undef, table => undef, text => "23:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Reports the snapshoted frame count", }, { col => undef, table => undef, text => "Snapshot frame count of CRTC2" }, { col => undef, table => undef, text => "D2CRTC_START_LINE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68D8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2CRTC_PROGRESSIVE_START_LINE" }, { col => undef, table => undef, text => "_EARLY" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "move start_line signal by 1 line eariler in progressive mode", }, ], }, { num => 290, text => [ { col => 0, table => 0, text => "D2CRTC_INTERLACE_START_LINE_EA" }, { col => 0, table => 0, text => "RLY" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "move start_line signal by 1 line earlier in interlaced timing ", }, { col => undef, table => undef, text => "mode" }, { col => undef, table => undef, text => "move start_line signal earlier by 1 line in CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_INTERRUPT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68DC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_SNAPSHOT_INT_MSK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for CRTC snapshot event" }, { col => 3, table => 1, text => "0 = disables interrupt" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_SNAPSHOT_INT_TYPE" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 1, text => "D2CRTC_V_UPDATE_INT_MSK" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for falling edge of V_UPDATE ^M", }, { col => 3, table => 1, text => "0 = disables interrupt^M" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_V_UPDATE_INT_TYPE" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 1, text => "D2CRTC_FORCE_COUNT_NOW_INT_M" }, { col => 0, table => 1, text => "SK" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for force count now event", }, { col => 3, table => 1, text => "0 = disables interrupt" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_FORCE_COUNT_NOW_INT_T" }, { col => 0, table => 1, text => "YPE" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 1, text => "D2CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "INT_MSK" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for force VSYNC next line event", }, { col => 3, table => 1, text => "0 = disables interrupt" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_FORCE_VSYNC_NEXT_LINE_" }, { col => 0, table => 1, text => "INT_TYPE" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 1, text => "D2CRTC_TRIGA_INT_MSK" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for CRTC external trigger A", }, { col => 3, table => 1, text => "0 = disables interrupt" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_TRIGB_INT_MSK" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt mask for CRTC external trigger B", }, { col => 3, table => 1, text => "0 = disables interrupt" }, { col => 3, table => 1, text => "1 = enables interrupt" }, { col => 0, table => 1, text => "D2CRTC_TRIGA_INT_TYPE" }, { col => 1, table => 1, text => 26 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => 0, table => 1, text => "D2CRTC_TRIGB_INT_TYPE" }, { col => 1, table => 1, text => 27 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "0 is legacy level based interrupt, 1 is pulse based interrupt", }, { col => undef, table => undef, text => "Interrupt mask for CRTC2 events" }, { col => "heading", table => 2, text => "D2MODE_MASTER_UPDATE_LOCK - RW - 32 bits - [GpuF0MMReg:0x68E0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2MODE_MASTER_UPDATE_LOCK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set the master update lock for V_UPDATE signal", }, { col => 3, table => 2, text => "0 = no master lock, V_UPDATE signal will occur", }, { col => 3, table => 2, text => "1 = set master lock to prevent V_UPDATE signal occuring, ", }, { col => undef, table => undef, text => "thus prevent double buffering of display registers", }, { col => undef, table => undef, text => "Master update lock for CRTC2 V_UPDATE signal", }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_MODE - RW - 32 bits - [GpuF0MMReg:0x68E4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D2MODE_MASTER_UPDATE_MODE" }, { col => undef, table => undef, text => "2:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls the position of the V_UPDATE signal", }, { col => undef, table => undef, text => "000 = V_UPDATE occurs between end of active display ", }, { col => undef, table => undef, text => "region and start line signal" }, { col => undef, table => undef, text => "001 = V_UPDATE occurs when leading edge of HSYNCA ", }, { col => undef, table => undef, text => "meets leading edge of VSYNCA" }, { col => undef, table => undef, text => "010 = V_UPDATE occurs at the leading edge of VSYNC_A", }, { col => undef, table => undef, text => "011 = V_UPDATE occurs at the beginning of the first line of ", }, { col => undef, table => undef, text => "vertical front porch" }, { col => undef, table => undef, text => "100 = V_UPDATE occurs at end of the line before start line ", }, { col => undef, table => undef, text => "Others = Reserved" }, ], }, { num => 291, text => [ { col => 0, table => 0, text => "D2MODE_MASTER_UPDATE_INTERLA" }, { col => 0, table => 0, text => "CED_MODE" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls generation of V_UPDATE signal in interlaced ", }, { col => 3, table => 0, text => "mode" }, { col => 3, table => 0, text => "00 = generates V_UPDATE at both even and odd field", }, { col => 3, table => 0, text => "01 = generates V_UPDATE only at even field. when ", }, { col => 3, table => 0, text => "D1MODE_MASTER_UPDATE_MODE = 00, V_UPDATE ", }, { col => 3, table => 0, text => "starts at odd field and ends at even field", }, { col => 3, table => 0, text => "10 = generates V_UPDATE only at odd field. when ", }, { col => 3, table => 0, text => "D1MODE_MASTER_UPDATE_MODE = 00, V_UPDATE ", }, { col => 3, table => 0, text => "starts at even field and ends at odd field", }, { col => undef, table => undef, text => "11 = reserved" }, { col => undef, table => undef, text => "Controls the generation of the V_UPDATE signal in CRTC2", }, { col => "heading", table => 1, text => "D2CRTC_UPDATE_LOCK - RW - 32 bits - [GpuF0MMReg:0x68E8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "D2CRTC_UPDATE_LOCK" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set the lock for CRTC timing registers" }, { col => 3, table => 1, text => "0 = no lock, double buffering can occur" }, { col => undef, table => undef, text => "1 = set lock to prevent double buffering", }, { col => undef, table => undef, text => "Update lock for CRTC2 timing registers", }, { col => "heading", table => 2, text => "D2CRTC_DOUBLE_BUFFER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x68EC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "D2CRTC_UPDATE_PENDING (R)" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Reports the status of double-buffered timing registers in ", }, { col => 3, table => 2, text => "CRTC2" }, { col => 3, table => 2, text => "0 = update has completed" }, { col => 3, table => 2, text => "1 = update is still pending" }, { col => 0, table => 2, text => "D2CRTC_UPDATE_INSTANTLY" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Disables double buffering of CRTC2 timing registers", }, { col => 3, table => 2, text => "0 = enables double buffering" }, { col => 3, table => 2, text => "1 = disables double buffering" }, { col => 0, table => 2, text => "D2CRTC_BLANK_DATA_DOUBLE_BUF" }, { col => 0, table => 2, text => "FER_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables the double buffering of " }, { col => 3, table => 2, text => "D2CRTC_BLANK_DATA_EN" }, { col => 3, table => 2, text => "0 = disables double buffering. D2CRTC_BLANK_DATA_EN ", }, { col => 3, table => 2, text => "is updated immediately" }, { col => 3, table => 2, text => "1 = enables double buffering of " }, { col => undef, table => undef, text => "D2CRTC_BLANK_DATA_EN when V_UPDATE is active", }, { col => undef, table => undef, text => "Controls double buffering of CRTC2 registers", }, { col => "heading", table => 3, text => "D2CRTC_VGA_PARAMETER_CAPTURE_MODE - RW - 32 bits - [GpuF0MMReg:0x68F0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "D2CRTC_VGA_PARAMETER_CAPTUR" }, { col => 0, table => 3, text => "E_MODE" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Controls how VGA timing parameters are captured.", }, { col => 3, table => 3, text => "0: CRTC2 will continuously latch in timing parameters from ", }, { col => 3, table => 3, text => "VGA" }, { col => 3, table => 3, text => "1: CRTC2 will continuously latch in timing parameters from ", }, { col => undef, table => undef, text => "VGA except during VGA parameter recalculated window", }, { col => undef, table => undef, text => "Controls how VGA timing parameters are captured", }, ], }, { num => 292, text => [ { col => undef, table => undef, text => "2.9" }, { col => undef, table => undef, text => "Display Output Registers" }, { col => undef, table => undef, text => "2.9.1" }, { col => undef, table => undef, text => "Digital to Analog Converter (DAC) Registers", }, { col => undef, table => undef, text => " DAC A Registers" }, { col => "heading", table => 0, text => "DACA_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7800]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACA_ENABLE" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Turn on/off DACA" }, { col => "heading", table => 1, text => "DACA_SOURCE_SELECT - RW - 32 bits - [GpuF0MMReg:0x7804]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_SOURCE_SELECT" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Source is CRTC1 " }, { col => 3, table => 1, text => " 1=Source is CRTC2 " }, { col => 3, table => 1, text => " 2=Source is TV Encoder " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "Select between 1st display, 2nd display & TV encoder streams", }, { col => "heading", table => 2, text => "DACA_CRC_EN - RW - 32 bits - [GpuF0MMReg:0x7808]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_CRC_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable signal for DACA CRC" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DACA_CRC_CONT_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Determines whether CRC is calculated continuously or for ", }, { col => 3, table => 2, text => "one frame (one shot)" }, { col => 3, table => 2, text => " 0=CRC is calculated over 1 frame " }, { col => undef, table => undef, text => " 1=CRC is continuously calculated for every frame ", }, { col => undef, table => undef, text => "DACA CRC enable signals" }, { col => undef, table => undef, text => "DACA_CRC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x780C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACA_CRC_FIELD" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Controls which field polarity starts the DACA CRC block ", }, { col => undef, table => undef, text => "after DACA_CRC_EN is set high. Used only for interlaced ", }, { col => undef, table => undef, text => "mode CRCs" }, { col => undef, table => undef, text => " 0=Even field begins CRC calculation ", }, { col => undef, table => undef, text => " 1=Odd field begins CRC calculation ", }, { col => undef, table => undef, text => "DACA_CRC_ONLY_BLANKb" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Determines whether CRC is calculated for the whole frame ", }, { col => undef, table => undef, text => "or only during non-blank period for DACA", }, { col => undef, table => undef, text => " 0=CRC calculated over entire field ", }, { col => undef, table => undef, text => " 1=CRC calculated only during BLANKb ", }, ], }, { num => 293, text => [ { col => undef, table => undef, text => "DACA CRC controls signals" }, { col => "heading", table => 0, text => "DACA_CRC_SIG_RGB_MASK - RW - 32 bits - [GpuF0MMReg:0x7810]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACA_CRC_SIG_BLUE_MASK" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x3ff" }, { col => 3, table => 0, text => "Mask bits for DACA B channel CRC" }, { col => 0, table => 0, text => "DACA_CRC_SIG_GREEN_MASK" }, { col => 1, table => 0, text => "19:10" }, { col => 2, table => 0, text => "0x3ff" }, { col => 3, table => 0, text => "Mask bits for DACA G channel CRC" }, { col => 0, table => 0, text => "DACA_CRC_SIG_RED_MASK" }, { col => 1, table => 0, text => "29:20" }, { col => 2, table => 0, text => "0x3ff" }, { col => undef, table => undef, text => "Mask bits for DACA R channel CRC", }, { col => undef, table => undef, text => "Mask bits for R, G & B CRC calculations", }, { col => "heading", table => 1, text => "DACA_CRC_SIG_CONTROL_MASK - RW - 32 bits - [GpuF0MMReg:0x7814]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_CRC_SIG_CONTROL_MASK" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x3f" }, { col => undef, table => undef, text => "Mask bits for DACA control signal CRC", }, { col => undef, table => undef, text => "Mask bits for DACA control signal CRC", }, { col => "heading", table => 2, text => "DACA_CRC_SIG_RGB - RW - 32 bits - [GpuF0MMReg:0x7818]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_CRC_SIG_BLUE (R)" }, { col => 1, table => 2, text => "9:0" }, { col => 2, table => 2, text => "0x3ff" }, { col => 3, table => 2, text => "CRC signature value for DACA blue component", }, { col => 0, table => 2, text => "DACA_CRC_SIG_GREEN (R)" }, { col => 1, table => 2, text => "19:10" }, { col => 2, table => 2, text => "0x3ff" }, { col => 3, table => 2, text => "CRC signature value for DACA green component", }, { col => 0, table => 2, text => "DACA_CRC_SIG_RED (R)" }, { col => 1, table => 2, text => "29:20" }, { col => 2, table => 2, text => "0x3ff" }, { col => undef, table => undef, text => "CRC signature value for DACA red component", }, { col => undef, table => undef, text => "DACA CRC R, G & B results" }, { col => "heading", table => 3, text => "DACA_CRC_SIG_CONTROL - RW - 32 bits - [GpuF0MMReg:0x781C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACA_CRC_SIG_CONTROL (R)" }, { col => 1, table => 3, text => "5:0" }, { col => 2, table => 3, text => "0x3f" }, { col => undef, table => undef, text => "CRC signature value for DACA control signals", }, { col => undef, table => undef, text => "CRC signature value for DACA control signals", }, { col => "heading", table => 4, text => "DACA_SYNC_TRISTATE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7820]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DACA_HSYNCA_TRISTATE" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "DACA hsync tristate. Used to determine hsynca enable", }, { col => 0, table => 4, text => "DACA_VSYNCA_TRISTATE" }, { col => 1, table => 4, text => 8 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "DACA vsync tristate. Used to determine vsynca enable", }, { col => 0, table => 4, text => "DACA_SYNCA_TRISTATE" }, { col => 1, table => 4, text => 16 }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "DACA sync tristate. Used to determine sync enables", }, { col => undef, table => undef, text => "DACA SYNC Tristate control" }, { col => undef, table => undef, text => "DACA_SYNC_SELECT - RW - 32 bits - [GpuF0MMReg:0x7824]", }, ], }, { num => 294, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACA_SYNC_SELECT" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0: selects sync_a" }, { col => 3, table => 0, text => "1: selects sync_b." }, { col => 3, table => 0, text => "Used in conjunction with DACA_SOURCE_SEL(0).", }, { col => 3, table => 0, text => " 0=DACA uses HSYNC_A & VSYNC_A " }, { col => 3, table => 0, text => " 1=DACA used HSYNC_B & VSYNC_B " }, { col => 0, table => 0, text => "DACA_STEREOSYNC_SELECT" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0: selects crtc1 stereosync" }, { col => 3, table => 0, text => "1: selects crtc2 stereosync" }, { col => 3, table => 0, text => " 0=DACA uses CRTC1 STEREOSYNC " }, { col => undef, table => undef, text => " 1=DACA uses CRTC2 STEREOSYNC ", }, { col => undef, table => undef, text => "DACA ...SYNC selection" }, { col => "heading", table => 1, text => "DACA_AUTODETECT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7828]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_AUTODETECT_MODE" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Operation control of DACA Autodetect logic:", }, { col => 3, table => 1, text => "0: No checking" }, { col => 3, table => 1, text => "1: Connection checking" }, { col => 3, table => 1, text => "2: Disconnection checking" }, { col => 0, table => 1, text => "DACA_AUTODETECT_FRAME_TIME_C" }, { col => 0, table => 1, text => "OUNTER" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "If an enabled display pipe is connected to DACA, ", }, { col => 3, table => 1, text => "autodetect logic will count number of frames before DACA ", }, { col => 3, table => 1, text => "comparator enabled.Otherwise, the autodetect logic will ", }, { col => 3, table => 1, text => "count number of 0.1-second units." }, { col => 0, table => 1, text => "DACA_AUTODETECT_CHECK_MASK" }, { col => 1, table => 1, text => "18:16" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "Mask to select which of the 3 RGB channels will be checked ", }, { col => 3, table => 1, text => "for connection or disconnection." }, { col => 3, table => 1, text => "Bit 18: Check R/C channel if bit set to 1.", }, { col => 3, table => 1, text => "Bit 17: Check G/Y channel if bit set to 1.", }, { col => 3, table => 1, text => "Bit 16: Check B/Comp channel if bit set to 1.", }, { col => "heading", table => 2, text => "DACA_AUTODETECT_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x782C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_AUTODETECT_POWERUP_COU" }, { col => 0, table => 2, text => "NTER" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xb" }, { col => 3, table => 2, text => "DACA macro Bandgap voltage reference power up time. ", }, { col => 3, table => 2, text => "Default = 11 microseconds." }, { col => 0, table => 2, text => "DACA_AUTODETECT_TESTMODE" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "0: Normal operation" }, { col => 3, table => 2, text => " 1: Test mode - count in 1us units" }, { col => "heading", table => 3, text => "DACA_AUTODETECT_CONTROL3 - RW - 32 bits - [GpuF0MMReg:0x7830]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACA_AUTODET_COMPARATOR_IN_D" }, { col => 0, table => 3, text => "ELAY" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x19" }, { col => 3, table => 3, text => "DACA comparator delay for inputs to settle in autodetect ", }, { col => 3, table => 3, text => "mode. Default = 25us" }, { col => 0, table => 3, text => "DACA_AUTODET_COMPARATOR_OUT" }, { col => 0, table => 3, text => "_DELAY" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x5" }, { col => 3, table => 3, text => "DACA comparator delay for outputs to settle in autodetect ", }, { col => 3, table => 3, text => "mode. Default = 5us" }, ], }, { num => 295, text => [ { col => "heading", table => 0, text => "DACA_AUTODETECT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7834]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACA_AUTODETECT_STATUS (R)" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Result from autodetect logic sequence:" }, { col => 3, table => 0, text => "0: DACA was looking for a connection and has yet found a ", }, { col => 3, table => 0, text => "connection or DACA was looking for a disconnection has ", }, { col => 3, table => 0, text => "not yet found a disconnection" }, { col => 3, table => 0, text => "1: DACA was looking for a connection and found a ", }, { col => 3, table => 0, text => "connection or DACA was looking for a disconnection and ", }, { col => 3, table => 0, text => "found a disconnection" }, { col => 0, table => 0, text => "DACA_AUTODETECT_CONNECT (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "1: At least one channel has a properly terminated device ", }, { col => 3, table => 0, text => "connected." }, { col => 3, table => 0, text => "0: No devices are connected" }, { col => 0, table => 0, text => "DACA_AUTODETECT_RED_SENSE (R)" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Two bit result from last Red/C compare:" }, { col => 3, table => 0, text => "0: Channel is disconnected" }, { col => 3, table => 0, text => "1: Channel is connected" }, { col => 3, table => 0, text => "2: Channel is not checked" }, { col => 3, table => 0, text => "3: Reserved" }, { col => 0, table => 0, text => "DACA_AUTODETECT_GREEN_SENSE " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Two bit result from last Green/Y compare:", }, { col => 3, table => 0, text => "0: Channel is disconnected" }, { col => 3, table => 0, text => "1: Channel is connected" }, { col => 3, table => 0, text => "2: Channel is not checked" }, { col => 3, table => 0, text => "3: Reserved" }, { col => 0, table => 0, text => "DACA_AUTODETECT_BLUE_SENSE " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Two bit result from last Blue/Comp compare:", }, { col => 3, table => 0, text => "0: Channel is disconnected" }, { col => 3, table => 0, text => "1: Channel is connected" }, { col => 3, table => 0, text => "2: Channel is not checked" }, { col => 3, table => 0, text => "3: Reserved" }, { col => "heading", table => 1, text => "DACA_AUTODETECT_INT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7838]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_AUTODETECT_ACK (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Auto detect interrupt acknowledge and clear ", }, { col => 3, table => 1, text => "DACA_AUTODETECT_STATUS bit." }, { col => 0, table => 1, text => "DACA_AUTODETECT_INT_ENABLE" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable for auto detect interrupt" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => "heading", table => 2, text => "DACA_FORCE_OUTPUT_CNTL - RW - 32 bits - [GpuF0MMReg:0x783C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_FORCE_DATA_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable synchronous force option on DACA.", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DACA_FORCE_DATA_SEL" }, { col => 1, table => 2, text => "10:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select which DACA channels have data forced", }, { col => 3, table => 2, text => "0=Don't Force, 1=ForceBit" }, { col => 3, table => 2, text => "0: Blue channelBit" }, { col => 3, table => 2, text => "1: Green channelBit" }, { col => 3, table => 2, text => "2: Red channel" }, { col => 0, table => 2, text => "DACA_FORCE_DATA_ON_BLANKb_ON" }, { col => 0, table => 2, text => "LY" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Data is force only during active region.", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, ], }, { num => 296, text => [ { col => undef, table => undef, text => "Data Force Control" }, { col => "heading", table => 0, text => "DACA_FORCE_DATA - RW - 32 bits - [GpuF0MMReg:0x7840]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACA_FORCE_DATA" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Data to be forced on R, G & B channels. When auto detect ", }, { col => 3, table => 0, text => "logic is enabled, this must be programmed to 0x000 ", }, { col => 3, table => 0, text => "(Default)." }, { col => "heading", table => 1, text => "DACA_POWERDOWN - RW - 32 bits - [GpuF0MMReg:0x7850]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_POWERDOWN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Bandgap Voltage Reference Power down enable ", }, { col => 3, table => 1, text => "(BGSLEEP)" }, { col => 0, table => 1, text => "DACA_POWERDOWN_BLUE" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Blue channel power down enable (BDACPD)" }, { col => 0, table => 1, text => "DACA_POWERDOWN_GREEN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Green channel power down enable (GDACPD)", }, { col => 0, table => 1, text => "DACA_POWERDOWN_RED" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Red channel power down enable (RDACPD)", }, { col => undef, table => undef, text => "Controls for DACA Start-Up & Power-Down sequences", }, { col => "heading", table => 2, text => "DACA_CONTROL1 - RW - 32 bits - [GpuF0MMReg:0x7854]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_WHITE_LEVEL" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Video Standard Select bits - STD(1:0)" }, { col => 3, table => 2, text => "0x0: PAL" }, { col => 3, table => 2, text => "0x1: NTSC" }, { col => 3, table => 2, text => "PS2 (VGA)" }, { col => 3, table => 2, text => "0x3 HDTV (Component Video)" }, { col => 0, table => 2, text => "DACA_WHITE_FINE_CONTROL" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x20" }, { col => 3, table => 2, text => "Full-scale Output Adjustment - DACADJ(4:0)", }, { col => 0, table => 2, text => "DACA_BANDGAP_ADJUSTMENT" }, { col => 1, table => 2, text => "21:16" }, { col => 2, table => 2, text => "0x20" }, { col => 3, table => 2, text => "Bandgap Reference Voltage Adjustment - BGADJ(3:0)", }, { col => 0, table => 2, text => "DACA_ANALOG_MONITOR" }, { col => 1, table => 2, text => "27:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Analog test mux select - MON(3:0)" }, { col => 0, table => 2, text => "DACA_COREMON" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Core voltage monitor input port" }, { col => "heading", table => 3, text => "DACA_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x7858]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACA_DFORCE_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "DACA asynchronous data force enable. Can be used for ", }, { col => 3, table => 3, text => "sync force as well but DACA_FORCE_OUTPUT_CNTL ", }, { col => 3, table => 3, text => "achieves the same goal with a more complete feature set. ", }, { col => 3, table => 3, text => "Asynchronous force requires DACA_x_ASYNC_ENABLE in ", }, { col => 3, table => 3, text => "DACA_COMPARATOR_ENABLE to be set as well. Drives ", }, { col => 3, table => 3, text => "DFORCE_EN pin on macro. Forces all DACA channels to ", }, { col => 3, table => 3, text => "DACA_FORCE_DATA value. Overrides " }, { col => 3, table => 3, text => "DACA_FORCE_OUTPUT_CNTL/DACA_FORCE_DATA_E", }, { col => 3, table => 3, text => "N control." }, { col => 0, table => 3, text => "DACA_TV_ENABLE" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 297, text => [ { col => 0, table => 0, text => "DACA_ZSCALE_SHIFT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACA zero scale shift enable. Causes DACA to add a ", }, { col => 3, table => 0, text => "small offset to the levels of all outputs. Drives DACA ", }, { col => 3, table => 0, text => "ZSCALE_SHIFT pin." }, { col => undef, table => undef, text => "DACA_COMPARATOR_ENABLE - RW - 32 bits - [GpuF0MMReg:0x785C]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACA_COMP_DDET_REF_EN" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables DACA comparators for analog termination ", }, { col => undef, table => undef, text => "checking with DDETECT_REF as the reference. The ", }, { col => undef, table => undef, text => "DDETECT reference level is lower than SDETECT_REF to ", }, { col => undef, table => undef, text => "allow termination checking on an active channel while the ", }, { col => undef, table => undef, text => "data being driven is the ZSCALE_SHIFT offset.Must be ", }, { col => undef, table => undef, text => "used in conjunction with ZSCALE_SHIFT=1 and with some ", }, { col => undef, table => undef, text => "forced data on the DAC inputs. Only one of ", }, { col => undef, table => undef, text => "COMP_DDET_REF_EN and COMP_SDET_REF_EN ", }, { col => undef, table => undef, text => "should be active at a time.Used in conjunction with core ", }, { col => undef, table => undef, text => "logic to drive the DAC DDETECT pin.", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACA_COMP_SDET_REF_EN" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enables DACA comparators for analog termination ", }, { col => undef, table => undef, text => "checking with SDETECT_REF as the reference. The data ", }, { col => undef, table => undef, text => "must be forced to a sufficiently high value using one of the ", }, { col => undef, table => undef, text => "DAC force features. Only one of COMP_DDET_REF_EN ", }, { col => undef, table => undef, text => "and COMP_SDET_REF_EN should be active at a ", }, { col => undef, table => undef, text => "time.Goes directly to the DAC SDETECT pin.", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACA_R_ASYNC_ENABLE" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACA red channel asynchronous mode enable.Allows DAC ", }, { col => undef, table => undef, text => "outputs to be updated without a clock.Used in conjunction ", }, { col => undef, table => undef, text => "with core logic to drive the DAC R_ASYNC_EN pin.", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACA_G_ASYNC_ENABLE" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACA green channel asynchronous mode enable.Used in ", }, { col => undef, table => undef, text => "conjunction with core logic to drive the DAC G_ASYNC_EN ", }, { col => undef, table => undef, text => "pin." }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACA_B_ASYNC_ENABLE" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACA blue channel asynchronous mode enable.Used in ", }, { col => undef, table => undef, text => "conjunction with core logic to drive the DAC B_ASYNC_EN ", }, { col => undef, table => undef, text => "pin." }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACA_COMPARATOR_OUTPUT - RW - 32 bits - [GpuF0MMReg:0x7860]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACA_COMPARATOR_OUTPUT (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Monitor Detect Output. This signal is an AND of 3 DAC ", }, { col => undef, table => undef, text => "macro signals: R_CDET, G_YDET & B_COMPDET.", }, { col => undef, table => undef, text => "DACA_COMPARATOR_OUTPUT_BLUE " }, { col => undef, table => undef, text => "(R)" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACA blue channel comparator output ? value comes from ", }, { col => undef, table => undef, text => "DAC R_CDET pin" }, { col => undef, table => undef, text => "DACA_COMPARATOR_OUTPUT_GREE" }, { col => undef, table => undef, text => "N (R)" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACA green channel comparator output ? value comes ", }, { col => undef, table => undef, text => "from DAC G_YDET pin" }, ], }, { num => 298, text => [ { col => undef, table => undef, text => " DAC B Registers" }, { col => 0, table => 0, text => "DACA_COMPARATOR_OUTPUT_RED " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACA red channel comparator output ? value comes from ", }, { col => 3, table => 0, text => "DAC B_COMPDET pin" }, { col => "heading", table => 1, text => "DACA_TEST_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7864]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_TEST_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACATEST Enable" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => "heading", table => 2, text => "DACA_PWR_CNTL - RW - 32 bits - [GpuF0MMReg:0x7868]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACA_BG_MODE" }, { col => 1, table => 2, text => "1:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Bandgap macro configuration - BGMODE(1:0)", }, { col => 0, table => 2, text => "DACA_PWRCNTL" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Macro bias current level control - PWRCNTL(1:0)", }, { col => "heading", table => 3, text => "DACA_DFT_CONFIG - RW - 32 bits - [GpuF0MMReg:0x786C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACA_DFT_CONFIG" }, { col => 1, table => 3, text => "31:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Configuration for DACA DFT block" }, { col => "heading", table => 4, text => "DACB_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7A00]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DACB_ENABLE" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Turn on/off DACB" }, { col => undef, table => undef, text => "DACB_SOURCE_SELECT - RW - 32 bits - [GpuF0MMReg:0x7A04]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 299, text => [ { col => 0, table => 0, text => "DACB_SOURCE_SELECT" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Source is CRTC1 " }, { col => 3, table => 0, text => " 1=Source is CRTC2 " }, { col => 3, table => 0, text => " 2=Source is TV Encoder " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "Select between 1st display, 2nd display & TV encoder streams", }, { col => "heading", table => 1, text => "DACB_CRC_EN - RW - 32 bits - [GpuF0MMReg:0x7A08]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_CRC_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable signal for DACB CRC" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DACB_CRC_CONT_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Determines whether CRC is calculated for the whole frame ", }, { col => 3, table => 1, text => "or only during non-blank period for DACB", }, { col => 3, table => 1, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACB CRC enable signals" }, { col => "heading", table => 2, text => "DACB_CRC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7A0C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACB_CRC_FIELD" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Controls which field polarity starts the DACB CRC block ", }, { col => 3, table => 2, text => "after DACA_CRC_EN is set high. Used only for interlaced ", }, { col => 3, table => 2, text => "mode CRCs." }, { col => 3, table => 2, text => " 0=Even field begins CRC calculation " }, { col => 3, table => 2, text => " 1=Odd field begins CRC calculation " }, { col => 0, table => 2, text => "DACB_CRC_ONLY_BLANKb" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "CRC only during the Non-blank region" }, { col => 3, table => 2, text => " 0=CRC calculated over entire field " }, { col => undef, table => undef, text => " 1=CRC calculated only during BLANKb ", }, { col => undef, table => undef, text => "DACB CRC controls signals" }, { col => "heading", table => 3, text => "DACB_CRC_SIG_RGB_MASK - RW - 32 bits - [GpuF0MMReg:0x7A10]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACB_CRC_SIG_BLUE_MASK" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x3ff" }, { col => 3, table => 3, text => "Mask bits for DACB B channel CRC" }, { col => 0, table => 3, text => "DACB_CRC_SIG_GREEN_MASK" }, { col => 1, table => 3, text => "19:10" }, { col => 2, table => 3, text => "0x3ff" }, { col => 3, table => 3, text => "Mask bits for DACB G channel CRC" }, { col => 0, table => 3, text => "DACB_CRC_SIG_RED_MASK" }, { col => 1, table => 3, text => "29:20" }, { col => 2, table => 3, text => "0x3ff" }, { col => undef, table => undef, text => "Mask bits for DACB R channel CRC", }, { col => undef, table => undef, text => "Mask bits for R, G & B CRC calculations", }, { col => "heading", table => 4, text => "DACB_CRC_SIG_CONTROL_MASK - RW - 32 bits - [GpuF0MMReg:0x7A14]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DACB_CRC_SIG_CONTROL_MASK" }, { col => 1, table => 4, text => "5:0" }, { col => 2, table => 4, text => "0x3f" }, { col => undef, table => undef, text => "Mask bits for DACB control signal CRC", }, { col => undef, table => undef, text => "Mask bits for DACB control signal CRC", }, ], }, { num => 300, text => [ { col => "heading", table => 0, text => "DACB_CRC_SIG_RGB - RW - 32 bits - [GpuF0MMReg:0x7A18]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACB_CRC_SIG_BLUE (R)" }, { col => 1, table => 0, text => "9:0" }, { col => 2, table => 0, text => "0x3ff" }, { col => 3, table => 0, text => "CRC signature value for DACB blue component", }, { col => 0, table => 0, text => "DACB_CRC_SIG_GREEN (R)" }, { col => 1, table => 0, text => "19:10" }, { col => 2, table => 0, text => "0x3ff" }, { col => 3, table => 0, text => "CRC signature value for DACB green component", }, { col => 0, table => 0, text => "DACB_CRC_SIG_RED (R)" }, { col => 1, table => 0, text => "29:20" }, { col => 2, table => 0, text => "0x3ff" }, { col => undef, table => undef, text => "CRC signature value for DACB red component", }, { col => undef, table => undef, text => "DACB CRC R, G & B results" }, { col => "heading", table => 1, text => "DACB_CRC_SIG_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7A1C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_CRC_SIG_CONTROL (R)" }, { col => 1, table => 1, text => "5:0" }, { col => 2, table => 1, text => "0x3f" }, { col => undef, table => undef, text => "CRC signature value for DACB control signals", }, { col => undef, table => undef, text => "CRC signature value for DACB control signals", }, { col => "heading", table => 2, text => "DACB_SYNC_TRISTATE_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7A20]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACB_HSYNCB_TRISTATE" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "DACB hsync tristate. Used to determine hsyncb enable", }, { col => 0, table => 2, text => "DACB_VSYNCB_TRISTATE" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "DACB vsync tristate. Used to determine vsyncb enable", }, { col => 0, table => 2, text => "DACB_SYNCB_TRISTATE" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "DACB sync tristate. Used to determine sync enables", }, { col => undef, table => undef, text => "DACB SYNC Tristate control" }, { col => "heading", table => 3, text => "DACB_SYNC_SELECT - RW - 32 bits - [GpuF0MMReg:0x7A24]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACB_SYNC_SELECT" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=DACB uses HSYNC_A & VSYNC_A " }, { col => 3, table => 3, text => " 1=DACB used HSYNC_B & VSYNC_B " }, { col => 0, table => 3, text => "DACB_STEREOSYNC_SELECT" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=DACB uses CRTC1 STEREOSYNC " }, { col => 3, table => 3, text => " 1=DACB uses CRTC2 STEREOSYNC " }, { col => undef, table => undef, text => "DACB_AUTODETECT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7A28]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACB_AUTODETECT_MODE" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Operation control of DACB Autodetect logic:", }, { col => undef, table => undef, text => "0: No checking" }, { col => undef, table => undef, text => "1: Connection checking" }, { col => undef, table => undef, text => "2: Disconnection checking" }, { col => undef, table => undef, text => "DACB_AUTODETECT_FRAME_TIME_C" }, { col => undef, table => undef, text => "OUNTER" }, { col => undef, table => undef, text => "15:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "If an enabled display pipe is connected to DACB, ", }, { col => undef, table => undef, text => "autodetect logic will count number of frames before DACB ", }, { col => undef, table => undef, text => "comparator enabled.Otherwise, the autodetect logic will ", }, { col => undef, table => undef, text => "count number of 0.1-second units.", }, ], }, { num => 301, text => [ { col => 0, table => 0, text => "DACB_AUTODETECT_CHECK_MASK" }, { col => 1, table => 0, text => "18:16" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Mask to select which of the 3 RGB channels will be checked ", }, { col => 3, table => 0, text => "for connection or disconnection." }, { col => 3, table => 0, text => "Bit 18: Check R/C channel if bit set to 1.", }, { col => 3, table => 0, text => "Bit 17: Check G/Y channel if bit set to 1.", }, { col => 3, table => 0, text => "Bit 16: Check B/Comp channel if bit set to 1.", }, { col => "heading", table => 1, text => "DACB_AUTODETECT_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x7A2C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_AUTODETECT_POWERUP_COU" }, { col => 0, table => 1, text => "NTER" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0xb" }, { col => 3, table => 1, text => "DACB macro Bandgap voltage reference power up time. ", }, { col => 3, table => 1, text => "Default = 11 microseconds." }, { col => 0, table => 1, text => "DACB_AUTODETECT_TESTMODE8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0: Normal operation" }, { col => 3, table => 1, text => "1: Test mode - count in 1us units" }, { col => "heading", table => 2, text => "DACB_AUTODETECT_CONTROL3 - RW - 32 bits - [GpuF0MMReg:0x7A30]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACB_AUTODET_COMPARATOR_IN_D" }, { col => 0, table => 2, text => "ELAY" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x19" }, { col => 3, table => 2, text => "DACB comparator delay for inputs to settle in autodetect ", }, { col => 3, table => 2, text => "mode. Default = 25us" }, { col => 0, table => 2, text => "DACB_AUTODET_COMPARATOR_OUT" }, { col => 0, table => 2, text => "_DELAY" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x5" }, { col => 3, table => 2, text => "DACB comparator delay for outputs to settle in autodetect ", }, { col => 3, table => 2, text => "mode. Default = 5us" }, { col => "heading", table => 3, text => "DACB_AUTODETECT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7A34]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACB_AUTODETECT_STATUS (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Result from autodetect logic sequence:" }, { col => 3, table => 3, text => "0: DACB was looking for a connection and has yet found a ", }, { col => 3, table => 3, text => "connection or DACB was looking for a disconnection has ", }, { col => 3, table => 3, text => "not yet found a disconnection" }, { col => 3, table => 3, text => "1: DACB was looking for a connection and found a ", }, { col => 3, table => 3, text => "connection or DACB was looking for a disconnection and ", }, { col => 3, table => 3, text => "did not find a disconnection" }, { col => 0, table => 3, text => "DACB_AUTODETECT_CONNECT (R)" }, { col => 1, table => 3, text => 4 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=No devices are connected " }, { col => 3, table => 3, text => " 1=At least one channel has a properly terminated device ", }, { col => 3, table => 3, text => "connected " }, { col => 0, table => 3, text => "DACB_AUTODETECT_RED_SENSE (R)" }, { col => 1, table => 3, text => "9:8" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Two bit result from last Red/C compare:" }, { col => 3, table => 3, text => "0: Channel is disconnected" }, { col => 3, table => 3, text => "1: Channel is connected" }, { col => 3, table => 3, text => "2: Channel is not checked" }, { col => 3, table => 3, text => "3: Reserved" }, { col => 0, table => 3, text => "DACB_AUTODETECT_GREEN_SENSE " }, { col => 0, table => 3, text => "(R)" }, { col => 1, table => 3, text => "17:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Two bit result from last Green/Y compare:", }, { col => 3, table => 3, text => "0: Channel is disconnected" }, { col => 3, table => 3, text => "1: Channel is connected" }, { col => 3, table => 3, text => "2: Channel is not checked" }, { col => 3, table => 3, text => "3: Reserved" }, ], }, { num => 302, text => [ { col => 0, table => 0, text => "DACB_AUTODETECT_BLUE_SENSE " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Two bit result from last Blue/Comp compare:", }, { col => 3, table => 0, text => "0: Channel is disconnected" }, { col => 3, table => 0, text => "1: Channel is connected" }, { col => 3, table => 0, text => "2: Channel is not checked" }, { col => 3, table => 0, text => "3: Reserved" }, { col => "heading", table => 1, text => "DACB_AUTODETECT_INT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7A38]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_AUTODETECT_ACK (W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Auto detect interrupt acknowledge and clear ", }, { col => 3, table => 1, text => "DACB_AUTODETECT_STATUS bit." }, { col => 0, table => 1, text => "DACB_AUTODETECT_INT_ENABLE" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable for auto detect interrupt" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => "heading", table => 2, text => "DACB_FORCE_OUTPUT_CNTL - RW - 32 bits - [GpuF0MMReg:0x7A3C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACB_FORCE_DATA_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable synchronous force option on DACB" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DACB_FORCE_DATA_SEL" }, { col => 1, table => 2, text => "10:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select which DACB channels have data forced", }, { col => 3, table => 2, text => "0=Don't Force, 1=Force" }, { col => 3, table => 2, text => "Bit 0: Blue channel" }, { col => 3, table => 2, text => "Bit 1: Green channel" }, { col => 3, table => 2, text => "Bit 2: Red channel" }, { col => 0, table => 2, text => "DACB_FORCE_DATA_ON_BLANKb_ON" }, { col => 0, table => 2, text => "LY" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Data is force only during active region.", }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Data Force Control" }, { col => "heading", table => 3, text => "DACB_FORCE_DATA - RW - 32 bits - [GpuF0MMReg:0x7A40]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DACB_FORCE_DATA" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Data to be forced on R, G & B channels" }, { col => undef, table => undef, text => "DACB_POWERDOWN - RW - 32 bits - [GpuF0MMReg:0x7A50]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACB_POWERDOWN" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Bandgap Voltage Reference Power down enable ", }, { col => undef, table => undef, text => "(BGSLEEP)ANDed with controls from power management ", }, { col => undef, table => undef, text => "and TMDS2A power sequencer." }, { col => undef, table => undef, text => "DACB_POWERDOWN_BLUE" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Blue channel power-down enable - BDACPD", }, { col => undef, table => undef, text => "DACB_POWERDOWN_GREEN" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Green channel power-down enable - GDACPD", }, { col => undef, table => undef, text => "DACB_POWERDOWN_RED" }, { col => undef, table => undef, text => 24 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Red channel power-down enable - RDACPD", }, ], }, { num => 303, text => [ { col => undef, table => undef, text => "Controls for DACB Start-Up & Power-Down sequences", }, { col => "heading", table => 0, text => "DACB_CONTROL1 - RW - 32 bits - [GpuF0MMReg:0x7A54]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DACB_WHITE_LEVEL" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Video Standard Select bits - STD(1:0)" }, { col => 3, table => 0, text => "0x0: PAL" }, { col => 3, table => 0, text => "0x1: NTSC" }, { col => 3, table => 0, text => "PS2 (VGA)" }, { col => 3, table => 0, text => "0x3 HDTV (Component Video)" }, { col => 0, table => 0, text => "DACB_WHITE_FINE_CONTROL" }, { col => 1, table => 0, text => "13:8" }, { col => 2, table => 0, text => "0x20" }, { col => 3, table => 0, text => "Full-scale Output Adjustment - DACADJ(4:0)", }, { col => 0, table => 0, text => "DACB_BANDGAP_ADJUSTMENT" }, { col => 1, table => 0, text => "21:16" }, { col => 2, table => 0, text => "0x20" }, { col => 3, table => 0, text => "Bandgap Reference Voltage Adjustment - BGADJ(3:0)", }, { col => 0, table => 0, text => "DACB_ANALOG_MONITOR" }, { col => 1, table => 0, text => "27:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Analog test mux select - MON(3:0)" }, { col => 0, table => 0, text => "DACB_COREMON" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Core voltage monitor input port" }, { col => "heading", table => 1, text => "DACB_CONTROL2 - RW - 32 bits - [GpuF0MMReg:0x7A58]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_DFORCE_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB asynchronous data force enable. Can be used for ", }, { col => 3, table => 1, text => "sync force as well but DACB_FORCE_OUTPUT_CNTL ", }, { col => 3, table => 1, text => "achieves the same goal with a more complete feature set. ", }, { col => 3, table => 1, text => "Async force requires async bits in " }, { col => 3, table => 1, text => "DACB_COMPARATOR_ENABLE to be set as well. Drives ", }, { col => 3, table => 1, text => "DFORCE_EN pin on macro. Forces all DACB channels to ", }, { col => 3, table => 1, text => "DACB_FORCE_DATA value. Overrides " }, { col => 3, table => 1, text => "DACB_FORCE_OUTPUT_CNTL/DACB_FORCE_DATA_E", }, { col => 3, table => 1, text => "N control." }, { col => 0, table => 1, text => "DACB_TV_ENABLE" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB tv enable. Controls DACB output demux. R/G/B is ", }, { col => 3, table => 1, text => "selected when TV_ENABLE=0, Y/C/Comp when ", }, { col => 3, table => 1, text => "TV_ENABLE=1. Drives DAC TVENABLE input.", }, { col => 0, table => 1, text => "DACB_ZSCALE_SHIFT" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB zero scale shift enable. Causes DAC to add a small ", }, { col => 3, table => 1, text => "offset to the levels of all outputs. Drives DAC ", }, { col => 3, table => 1, text => "ZSCALE_SHIFT pin." }, { col => "heading", table => 2, text => "DACB_COMPARATOR_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7A5C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DACB_COMP_DDET_REF_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enables DACB comparators for analog termination ", }, { col => 3, table => 2, text => "checking with DDETECT_REF as the reference. The ", }, { col => 3, table => 2, text => "DDETECT reference level is lower than SDETECT_REF to ", }, { col => 3, table => 2, text => "allow termination checking on an active channel while the ", }, { col => 3, table => 2, text => "data being driven is the ZSCALE_SHIFT offset.Must be ", }, { col => 3, table => 2, text => "used in conjunction with ZSCALE_SHIFT=1 or with some ", }, { col => 3, table => 2, text => "forced data on the DAC inputs. Only one of ", }, { col => 3, table => 2, text => "COMP_DDET_REF_EN and COMP_SDET_REF_EN " }, { col => 3, table => 2, text => "should be active at a time.Used in conjunction with core ", }, { col => 3, table => 2, text => "logic to drive the DAC DDETECT pin." }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, ], }, { num => 304, text => [ { col => 0, table => 0, text => "DACB_COMP_SDET_REF_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enables DACB comparators for analog termination ", }, { col => 3, table => 0, text => "checking with SDETECT_REF as the reference. The data ", }, { col => 3, table => 0, text => "must be forced to a sufficiently high value using one of the ", }, { col => 3, table => 0, text => "DAC force features. Only one of COMP_DDET_REF_EN ", }, { col => 3, table => 0, text => "and COMP_SDET_REF_EN should be active at a ", }, { col => 3, table => 0, text => "time.Goes directly to the DAC SDETECT pin.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DACB_R_ASYNC_ENABLE" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACB red channel asynchronous mode enable.Allows DAC ", }, { col => 3, table => 0, text => "outputs to be updated without a clock.Used in conjunction ", }, { col => 3, table => 0, text => "with core logic to drive the DAC R_ASYNC_EN pin.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DACB_G_ASYNC_ENABLE" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACB green channel asynchronous mode enable.Used in ", }, { col => 3, table => 0, text => "conjunction with core logic to drive the DAC G_ASYNC_EN ", }, { col => 3, table => 0, text => "pin." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DACB_B_ASYNC_ENABLE" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACB blue channel asynchronous mode enable.Used in ", }, { col => 3, table => 0, text => "conjunction with core logic to drive the DAC B_ASYNC_EN ", }, { col => 3, table => 0, text => "pin." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => "heading", table => 1, text => "DACB_COMPARATOR_OUTPUT - RW - 32 bits - [GpuF0MMReg:0x7A60]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACB_COMPARATOR_OUTPUT (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Monitor Detect Output. This signal is an AND of 4 dac ", }, { col => 3, table => 1, text => "macro signals: DETECT, RDACDET, GDACDET & ", }, { col => 3, table => 1, text => "BDACDET." }, { col => 0, table => 1, text => "DACB_COMPARATOR_OUTPUT_BLUE " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB blue channel comparator output ? value comes from ", }, { col => 3, table => 1, text => "DAC BDACDET pin" }, { col => 0, table => 1, text => "DACB_COMPARATOR_OUTPUT_GREE" }, { col => 0, table => 1, text => "N (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB green channel comparator output ? value comes ", }, { col => 3, table => 1, text => "from DAC GDACDET pin" }, { col => 0, table => 1, text => "DACB_COMPARATOR_OUTPUT_RED " }, { col => 0, table => 1, text => "(R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "DACB red channel comparator output ? value comes from ", }, { col => 3, table => 1, text => "DAC RDACDET pin" }, { col => undef, table => undef, text => "DACB_TEST_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7A64]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACB_TEST_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DACBTEST Enable. Use for DAC test only. Drives DAC", }, { col => undef, table => undef, text => "DACB_PWR_CNTL - RW - 32 bits - [GpuF0MMReg:0x7A68]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DACB_BG_MODE" }, { col => undef, table => undef, text => "1:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "DACB bandgap macro configuration. Allows bandgap ", }, { col => undef, table => undef, text => "macro to be configured to optimize performance.Goes ", }, { col => undef, table => undef, text => "directly to DAC BG_MODE[1:0] input.", }, ], }, { num => 305, text => [ { col => undef, table => undef, text => " Transition-Minimized Digital Stream (TMDS) Registers", }, { col => 0, table => 0, text => "DACB_PWRCNTL" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "DACB bias current level control. Allows analog bias current ", }, { col => 3, table => 0, text => "levels to be adjusted for performance vs. power ", }, { col => 3, table => 0, text => "consumption tradeoff.Goes directly to DAC PWRCNTL[1:0] ", }, { col => 3, table => 0, text => "input." }, { col => "heading", table => 1, text => "TMDSA_CNTL - RW - 32 bits - [GpuF0MMReg:0x7880]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable for the reduction/encoding logic" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "TMDSA_HDMI_EN" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select DVI or HDMI mode" }, { col => 3, table => 1, text => " 0=DVI " }, { col => 3, table => 1, text => " 1=HDMI " }, { col => 0, table => 1, text => "TMDSA_ENABLE_HPD_MASK" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "0:Disallow" }, { col => 3, table => 1, text => "1:Allow override of TMDSA_ENABLE by HPD on ", }, { col => 3, table => 1, text => "disconnect" }, { col => 3, table => 1, text => " 0=Result from HPD circuit can not override ", }, { col => 3, table => 1, text => "TMDSA_ENABLE " }, { col => 3, table => 1, text => " 1=Result from HPD circuit can override TMDSA_ENABLE ", }, { col => 3, table => 1, text => "on disconnect " }, { col => 0, table => 1, text => "TMDSA_HPD_SELECT" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select which hot plug detect unit to use for TMDSA. This ", }, { col => 3, table => 1, text => "selection is only relevant if one of the HPD mask bits in this ", }, { col => 3, table => 1, text => "and other other registers is enabled." }, { col => 3, table => 1, text => " 0=Use HPD1 " }, { col => 3, table => 1, text => " 1=Use HPD2 " }, { col => 3, table => 1, text => " 2=use HPD3 " }, { col => 0, table => 1, text => "TMDSA_SYNC_PHASE" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Determine whether to reset phase signal on frame pulse", }, { col => 3, table => 1, text => "0: don't reset" }, { col => 3, table => 1, text => "1: reset" }, { col => 0, table => 1, text => "TMDSA_PIXEL_ENCODING" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=RGB 4:4:4 or YCBCR 4:4:4 " }, { col => 3, table => 1, text => " 1=YCbCr 4:2:2 " }, { col => 0, table => 1, text => "TMDSA_DUAL_LINK_ENABLE" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable dual-link" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "TMDSA_SWAP" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Swap upper and lower data channels" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => undef, table => undef, text => "TMDSA_SOURCE_SELECT - RW - 32 bits - [GpuF0MMReg:0x7884]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_SOURCE_SELECT" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select between display stream 1 & display stream 2", }, { col => undef, table => undef, text => " 0=CRTC1 data is used " }, { col => undef, table => undef, text => " 1=CRTC2 data is used " }, ], }, { num => 306, text => [ { col => 0, table => 0, text => "TMDSA_SYNC_SELECT" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select between SYNCA and SYNCB signals" }, { col => 3, table => 0, text => " 0=HSYNC_A & VSYNC_A from the selected CRTC are ", }, { col => 3, table => 0, text => "used " }, { col => 3, table => 0, text => " 1=HSYNC_B & VSYNC_B from the selected CRTC are ", }, { col => 3, table => 0, text => "used " }, { col => 0, table => 0, text => "TMDSA_STEREOSYNC_SELECT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select between CRTC1 and CRTC2 sterosync signals", }, { col => 3, table => 0, text => " 0=CRTC1 STEREOSYNC used " }, { col => undef, table => undef, text => " 1=CRTC2 STEREOSYNC used " }, { col => undef, table => undef, text => "Source Select control for Data, H/VSYNC & Stereosync", }, { col => "heading", table => 1, text => "TMDSA_COLOR_FORMAT - RW - 32 bits - [GpuF0MMReg:0x7888]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_COLOR_FORMAT" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls TMDSA output colour format. Formats 0 and 1 ", }, { col => 3, table => 1, text => "work in single or dual link. Format 2 requires dual link ", }, { col => 3, table => 1, text => "(MSBs on primary link, LSBs on secondary link).", }, { col => 3, table => 1, text => " 0=Normal (24bpp), Twin-Single 30bpp (8 MSBs of each ", }, { col => 3, table => 1, text => "component), or Dual-Link 48bpp " }, { col => 3, table => 1, text => " 1=Twin-Link 30bpp (2 LSB of each component) ", }, { col => 3, table => 1, text => " 2=Dual-Link 30bpp " }, { col => 3, table => 1, text => " 3=Reserved " }, { col => "heading", table => 2, text => "TMDSA_FORCE_OUTPUT_CNTL - RW - 32 bits - [GpuF0MMReg:0x788C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_FORCE_DATA_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable force option on TMDSA" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "TMDSA_FORCE_DATA_SEL" }, { col => 1, table => 2, text => "10:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Select TMDSA channels that have data forced0=Don't ", }, { col => 3, table => 2, text => "Force, 1=Force" }, { col => 3, table => 2, text => "Bit 0: Blue channeli" }, { col => 3, table => 2, text => "Bit 1: Green channel" }, { col => 3, table => 2, text => "Bit 2: Red channel" }, { col => 0, table => 2, text => "TMDSA_FORCE_DATA_ON_BLANKb_O" }, { col => 0, table => 2, text => "NLY" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Data is forced only during active region.", }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Data Force Control" }, { col => "heading", table => 3, text => "TMDSA_FORCE_DATA - RW - 32 bits - [GpuF0MMReg:0x7890]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TMDSA_FORCE_DATA" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "8 bit Data put on TMDS output data channels accordinging ", }, { col => 3, table => 3, text => "to TMDSA_FORCE_DATA_SEL when Force feature ", }, { col => 3, table => 3, text => "enabled (TMDSA_FORCE_DATA_EN = 1)" }, ], }, { num => 307, text => [ { col => "heading", table => 0, text => "TMDSA_BIT_DEPTH_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7894]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TMDSA_TRUNCATE_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable bit reduction by truncation" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_TRUNCATE_DEPTH" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls bits per pixel" }, { col => 3, table => 0, text => " 0=18bpp " }, { col => 3, table => 0, text => " 1=24bpp " }, { col => 0, table => 0, text => "TMDSA_SPATIAL_DITHER_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable bit reduction by spatial (random) dither", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_SPATIAL_DITHER_MODE" }, { col => 1, table => 0, text => "10:9" }, { col => 2, table => 0, text => "0x0LFSR seed selection. 0: Seed pattern A(a,a), 1: seed ", }, { col => 3, table => 0, text => "pattern A(a, ~a), 2: seed pattern AABB(a, ~a, b, ~b), 3: ", }, { col => 3, table => 0, text => "seed pattern AABBCC(a, ~a, b, ~b, c, ~c)", }, { col => 0, table => 0, text => "TMDSA_SPATIAL_DITHER_DEPTH" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0Controls bits per pixel" }, { col => 3, table => 0, text => " 0=18bpp " }, { col => 3, table => 0, text => " 1=24bpp " }, { col => 0, table => 0, text => "TMDSA_FRAME_RANDOM_ENABLE" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Control the LFSR reset, every frame or once at startup", }, { col => 3, table => 0, text => " 0=0: RGB LFSR are reset every frame, 1: reset once at ", }, { col => 3, table => 0, text => "startup/no reset on every frame " }, { col => 0, table => 0, text => "TMDSA_RGB_RANDOM_ENABLE" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Control the pseudo-random number to be dithered on RGB", }, { col => 3, table => 0, text => " 0=0: RGB use x^28+x^3+1 random number ", }, { col => 3, table => 0, text => " 1=1: R dithered with x^28+x^3+1, G dithered with ", }, { col => 3, table => 0, text => "x^28+x^9+1 and B dithered with x^28+x^13+1 ", }, { col => 0, table => 0, text => "TMDSA_HIGHPASS_RANDOM_ENABLE" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Highpass filter on RGB dithered channels", }, { col => 3, table => 0, text => " 0=0: highpass filter is disable, 1: highpass filter is enable ", }, { col => 3, table => 0, text => "on RGB " }, { col => 0, table => 0, text => "TMDSA_TEMPORAL_DITHER_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable bit reduction by temporal dither (frame mod.)", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_TEMPORAL_DITHER_DEPTH" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls bits per pixel" }, { col => 3, table => 0, text => " 0=18bpp " }, { col => 3, table => 0, text => " 1=24bpp " }, { col => 0, table => 0, text => "TMDSA_TEMPORAL_DITHER_OFFSET" }, { col => 1, table => 0, text => "22:21" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Add offset to RGB channel before temporal dithering ", }, { col => 3, table => 0, text => "operation" }, { col => 3, table => 0, text => " 0=For 24bpp: add offset[1:0] to RGB channels ", }, { col => 3, table => 0, text => " 1=For 18bpp: Add offset[1:0]x4 to RGB channels ", }, { col => 0, table => 0, text => "TMDSA_TEMPORAL_LEVEL" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Gray level select (2 or 4 levels)" }, { col => 3, table => 0, text => " 0=Gray level 2(1 bit - LSB) " }, { col => 3, table => 0, text => " 1=Gray level 4(2 bits - 2 LSBs) " }, { col => 0, table => 0, text => "TMDSA_TEMPORAL_DITHER_RESET" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reset temporal dither (frame modulation)", }, { col => 3, table => 0, text => " 0=Temporal Dither Ready " }, { col => undef, table => undef, text => " 1=Reset Temporal Dither Circuit ", }, { col => undef, table => undef, text => "Control the method in which the data input into the TMDS block is reduced and the length it is reduced to.", }, { col => "heading", table => 1, text => "TMDSA_CONTROL_CHAR - RW - 32 bits - [GpuF0MMReg:0x7898]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_CONTROL_CHAR0_OUT_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Programmable sync character 0 enable" }, { col => 0, table => 1, text => "TMDSA_CONTROL_CHAR1_OUT_EN" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Programmable sync character 1 enable" }, { col => 0, table => 1, text => "TMDSA_CONTROL_CHAR2_OUT_EN" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Programmable sync character 2 enable" }, { col => 0, table => 1, text => "TMDSA_CONTROL_CHAR3_OUT_EN" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Programmable sync character 3 enable", }, { col => undef, table => undef, text => "SYNC Character Enable. Each bit represents the use of register defined sync character.", }, ], }, { num => 308, text => [ { col => "heading", table => 0, text => "TMDSA_CONTROL0_FEEDBACK - RW - 32 bits - [GpuF0MMReg:0x789C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TMDSA_CONTROL0_FEEDBACK_SELE" }, { col => 0, table => 0, text => "CT" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select input of CTL0 for TMDSA" }, { col => 0, table => 0, text => "TMDSA_CONTROL0_FEEDBACK_DELA" }, { col => 0, table => 0, text => "Y" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select delay of CTL0 for TMDSA" }, { col => "heading", table => 1, text => "TMDSA_STEREOSYNC_CTL_SEL - RW - 32 bits - [GpuF0MMReg:0x78A0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_STEREOSYNC_CTL_SEL" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls which CTL signal STEREOSYNC goes on to", }, { col => 3, table => 1, text => " 0=TMDS CTL registers have normal functionality ", }, { col => 3, table => 1, text => " 1=Stereosync will use TMDS CTL1 register ", }, { col => 3, table => 1, text => " 2=Stereosync will use TMDS CTL2 register ", }, { col => 3, table => 1, text => " 3=Stereosync will use TMDS CTL3 register ", }, { col => "heading", table => 2, text => "TMDSA_SYNC_CHAR_PATTERN_SEL - RW - 32 bits - [GpuF0MMReg:0x78A4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_SYNC_CHAR_PATTERN_SEL" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Reserved" }, { col => undef, table => undef, text => "Not Currently Connected" }, { col => "heading", table => 3, text => "TMDSA_SYNC_CHAR_PATTERN_0_1 - RW - 32 bits - [GpuF0MMReg:0x78A8]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TMDSA_SYNC_CHAR_PATTERN0" }, { col => 1, table => 3, text => "9:0" }, { col => 2, table => 3, text => "0x0TMDSA SYNC character set 0" }, { col => 0, table => 3, text => "TMDSA_SYNC_CHAR_PATTERN1" }, { col => 1, table => 3, text => "25:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "TMDSA SYNC character set 1" }, { col => "heading", table => 4, text => "TMDSA_SYNC_CHAR_PATTERN_2_3 - RW - 32 bits - [GpuF0MMReg:0x78AC]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "TMDSA_SYNC_CHAR_PATTERN2" }, { col => 1, table => 4, text => "9:0" }, { col => 2, table => 4, text => "0x0TMDSA SYNC character set 2" }, { col => 0, table => 4, text => "TMDSA_SYNC_CHAR_PATTERN3" }, { col => 1, table => 4, text => "25:16" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "TMDSA SYNC character set 3" }, { col => undef, table => undef, text => "TMDSA_CRC_CNTL - RW - 32 bits - [GpuF0MMReg:0x78B0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, ], }, { num => 309, text => [ { col => 0, table => 0, text => "TMDSA_CRC_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable TMDSA primary CRC calculation" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_CRC_CONT_EN" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select continuous or one-shot mode for primary CRC", }, { col => 3, table => 0, text => " 0=CRC is calculated over 1 frame " }, { col => 3, table => 0, text => " 1=CRC is continuously calculated for every frame ", }, { col => 0, table => 0, text => "TMDSA_CRC_ONLY_BLANKb" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether primary CRC is calculated for the ", }, { col => 3, table => 0, text => "whole frame or only during non-blank period.", }, { col => 3, table => 0, text => " 0=CRC calculated over entire field " }, { col => 3, table => 0, text => " 1=CRC calculated only during BLANKb " }, { col => 0, table => 0, text => "TMDSA_CRC_FIELD" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls which field polarity starts the TMDSA CRC block ", }, { col => 3, table => 0, text => "after TMDSA_CRC_EN is set to 1. Used only for interlaced ", }, { col => 3, table => 0, text => "mode CRCs" }, { col => 3, table => 0, text => " 0=Even field begins CRC calculation " }, { col => 3, table => 0, text => " 1=Odd field begins CRC calculation " }, { col => 0, table => 0, text => "TMDSA_2ND_CRC_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable TMDSA 2nd CRC calculation" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_2ND_CRC_LINK_SEL" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select which TMDS link to perform CRC on.", }, { col => 3, table => 0, text => " 0=Perform CRC on link0 " }, { col => 3, table => 0, text => " 1=Perform CRC on link1 " }, { col => 0, table => 0, text => "TMDSA_2ND_CRC_DATA_SEL" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Select whether to perform CRC on all data or a subset of ", }, { col => 3, table => 0, text => "the video frame." }, { col => 3, table => 0, text => " 0=2ND CRC calculated over entire field ", }, { col => 3, table => 0, text => " 1=2ND CRC calculated only during video data enable ", }, { col => 3, table => 0, text => "(plus preamble and guard band in HDMI mode) ", }, { col => 3, table => 0, text => " 2=2ND CRC calculated over vertical blank region, ", }, { col => 3, table => 0, text => "including VBI preamble and guard band region, excluding ", }, { col => 3, table => 0, text => "horizontal blank " }, { col => undef, table => undef, text => " 3=2ND CRC calculated only during audio data enable ", }, { col => undef, table => undef, text => "Enable TMDSA CRC Calculation" }, { col => "heading", table => 1, text => "TMDSA_CRC_SIG_MASK - RW - 32 bits - [GpuF0MMReg:0x78B4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_CRC_SIG_BLUE_MASK" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "CRC mask bits for TMDSA blue component" }, { col => 0, table => 1, text => "TMDSA_CRC_SIG_GREEN_MASK" }, { col => 1, table => 1, text => "15:8" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "CRC mask bits for TMDSA green component" }, { col => 0, table => 1, text => "TMDSA_CRC_SIG_RED_MASK" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "CRC mask bits for TMDSA red component" }, { col => 0, table => 1, text => "TMDSA_CRC_SIG_CONTROL_MASK" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x7" }, { col => 3, table => 1, text => "CRC mask bits for TMDSA control signals 3-bit input value:", }, { col => 3, table => 1, text => "bit 2 = Vsync" }, { col => 3, table => 1, text => "bit 1 = Hsync" }, { col => undef, table => undef, text => "bit 0 =Data Enable" }, { col => undef, table => undef, text => "RGB and Control CRC Mask" }, { col => undef, table => undef, text => "TMDSA_CRC_SIG_RGB - RW - 32 bits - [GpuF0MMReg:0x78B8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_CRC_SIG_BLUE (R)" }, { col => undef, table => undef, text => "7:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for TMDSA blue component", }, { col => undef, table => undef, text => "TMDSA_CRC_SIG_GREEN (R)" }, { col => undef, table => undef, text => "15:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for TMDSA green component", }, { col => undef, table => undef, text => "TMDSA_CRC_SIG_RED (R)" }, { col => undef, table => undef, text => "23:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for TMDSA red component", }, { col => undef, table => undef, text => "TMDSA_CRC_SIG_CONTROL (R)" }, { col => undef, table => undef, text => "26:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for TMDSA control signals3-bit input ", }, { col => undef, table => undef, text => "value:" }, { col => undef, table => undef, text => "bit 2 = Vsync" }, { col => undef, table => undef, text => "bit 1 = Hsync" }, { col => undef, table => undef, text => "bit 0 =Data Enable" }, ], }, { num => 310, text => [ { col => undef, table => undef, text => "RGB and Control CRC Result" }, { col => "heading", table => 0, text => "TMDSA_2ND_CRC_RESULT - RW - 32 bits - [GpuF0MMReg:0x78BC]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TMDSA_2ND_CRC_RESULT (R)" }, { col => 1, table => 0, text => "29:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Secondary TMDS CRC Result" }, { col => "heading", table => 1, text => "TMDSA_TEST_PATTERN - RW - 32 bits - [GpuF0MMReg:0x78C0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_TEST_PATTERN_OUT_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls the TMDSA output test pattern" }, { col => 3, table => 1, text => " 0=Normal functionality determined by value of ", }, { col => 3, table => 1, text => "TMDSA_RANDOM_PATTERN_OUT_EN register " }, { col => 3, table => 1, text => " 1=Test pattern output mode. The value of ", }, { col => 3, table => 1, text => "TMDSA_HALF_CLOCK_PATTERN_SEL determines ", }, { col => 3, table => 1, text => "whether a static 10-bit test data pattern or an alternating ", }, { col => 3, table => 1, text => "half-clock pattern will be output. " }, { col => 0, table => 1, text => "TMDSA_HALF_CLOCK_PATTERN_SEL" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Controls between static pattern output and alternating static ", }, { col => 3, table => 1, text => "pattern output" }, { col => 3, table => 1, text => " 0=10 bit test pattern from " }, { col => 3, table => 1, text => "TMDSA_STATIC_TEST_PATTERN is sent for TMDS ", }, { col => 3, table => 1, text => "output during every pixel clock " }, { col => 3, table => 1, text => " 1=Alternating pattern of " }, { col => 3, table => 1, text => "TMDSA_STATIC_TEST_PATTERN and " }, { col => 3, table => 1, text => "!(TMDSA_STATIC_TEST_PATTERN) on each subsequent ", }, { col => 3, table => 1, text => "pixel clock cycle is sent during every pixel clock ", }, { col => 0, table => 1, text => "TMDSA_RANDOM_PATTERN_OUT_EN" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable for random pattern output" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=TMDS Random Pixel Data Generator circuit generates ", }, { col => 3, table => 1, text => "24-bit pixel data to be encoded and transmitted ", }, { col => 0, table => 1, text => "TMDSA_RANDOM_PATTERN_RESET" }, { col => 1, table => 1, text => 5 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Reset random pattern to pattern seed" }, { col => 3, table => 1, text => " 0=Enable Random Pixel Data Generator ", }, { col => 3, table => 1, text => " 1=Random Pixel Data Generator is Reset to the value in ", }, { col => 3, table => 1, text => "TMDSA_RANDOM_PATTERN_SEED " }, { col => 0, table => 1, text => "TMDSA_TEST_PATTERN_EXTERNAL_" }, { col => 0, table => 1, text => "RESET_EN" }, { col => 1, table => 1, text => "60x10: Normal" }, { col => 3, table => 1, text => "1: Hold non-static test pattern (random, half clock) in reset ", }, { col => 3, table => 1, text => "when external signal is asserted" }, { col => 3, table => 1, text => " 0=Normal " }, { col => 3, table => 1, text => " 1=External signal resets random and half clock patterns ", }, { col => 0, table => 1, text => "TMDSA_STATIC_TEST_PATTERN" }, { col => 1, table => 1, text => "25:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "TMDSA test pixel. Replace the pixel value when ", }, { col => 3, table => 1, text => "TMDSA_TEST_PATTERN_OUT_EN=1" }, { col => "heading", table => 2, text => "TMDSA_RANDOM_PATTERN_SEED - RW - 32 bits - [GpuF0MMReg:0x78C4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_RANDOM_PATTERN_SEED" }, { col => 1, table => 2, text => "23:0" }, { col => 2, table => 2, text => "0x22222" }, { col => 2, table => 2, text => 2 }, { col => 3, table => 2, text => "Initial pattern for eye pattern measurement", }, ], }, { num => 311, text => [ { col => 0, table => 0, text => "TMDSA_RAN_PAT_DURING_DE_ONLY" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls between random pattern out during entire field and ", }, { col => 3, table => 0, text => "DE" }, { col => 3, table => 0, text => " 0=TMDS Random Data Pattern is output for all pixels ", }, { col => 3, table => 0, text => " 1=TMDS Random Data Pattern is only output when DE is ", }, { col => 3, table => 0, text => "high " }, { col => "heading", table => 1, text => "TMDSA_DEBUG - RW - 32 bits - [GpuF0MMReg:0x78C8]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_DEBUG_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set to 1 to enable debug mode" }, { col => 0, table => 1, text => "TMDSA_DEBUG_HSYNC" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug mode HSYNC" }, { col => 0, table => 1, text => "TMDSA_DEBUG_HSYNC_EN" }, { col => 1, table => 1, text => 9 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set to 1 to enable debug mode HSYNC" }, { col => 0, table => 1, text => "TMDSA_DEBUG_VSYNC" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug mode VSYNC" }, { col => 0, table => 1, text => "TMDSA_DEBUG_VSYNC_EN" }, { col => 1, table => 1, text => 17 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set to 1 to enable debug mode VSYNC" }, { col => 0, table => 1, text => "TMDSA_DEBUG_DE" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Debug mode display enable" }, { col => 0, table => 1, text => "TMDSA_DEBUG_DE_EN" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Set to 1 to enable debug mode display enable", }, { col => "heading", table => 2, text => "TMDSA_CTL_BITS - RW - 32 bits - [GpuF0MMReg:0x78CC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_CTL0" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Control signal for TMDSA (encoded in Green channel).", }, { col => 0, table => 2, text => "TMDSA_CTL1" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Control signal for TMDSA (encoded in Green channel).", }, { col => 0, table => 2, text => "TMDSA_CTL2" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Control signal for TMDSA (encoded in Red channel).", }, { col => 0, table => 2, text => "TMDSA_CTL3" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Control signal for TMDSA (encoded in Red channel).", }, { col => "heading", table => 3, text => "TMDSA_DCBALANCER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x78D0]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TMDSA_DCBALANCER_EN" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x1" }, { col => 3, table => 3, text => "DC Balancer Enable" }, { col => 3, table => 3, text => " 0=Disable " }, { col => 3, table => 3, text => " 1=Enable " }, { col => 0, table => 3, text => "TMDSA_DCBALANCER_TEST_EN" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "DC Balancer Test Enable" }, { col => 0, table => 3, text => "TMDSA_DCBALANCER_TEST_IN" }, { col => 1, table => 3, text => "19:16" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "DC Balancer Test Input" }, { col => 0, table => 3, text => "TMDSA_DCBALANCER_FORCE" }, { col => 1, table => 3, text => 24 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "DC Balancer select value to use when " }, { col => 3, table => 3, text => "DCBALANCER_EN=0" }, { col => "heading", table => 4, text => "TMDSA_RED_BLUE_SWITCH - RW - 32 bits - [GpuF0MMReg:0x78D4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "TMDSA_RB_SWITCH_EN" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Switch Red and Blue encoding position." }, { col => 3, table => 4, text => " 0=Disable " }, { col => 3, table => 4, text => " 1=Enable " }, ], }, { num => 312, text => [ { col => "heading", table => 0, text => "TMDSA_DATA_SYNCHRONIZATION - RW - 32 bits - [GpuF0MMReg:0x78DC]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TMDSA_DSYNSEL" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Data synchronization circuit select enable", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_PFREQCHG (W)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write to 1 to restarts read and write address generation ", }, { col => 3, table => 0, text => "logic. Write of 0 has no effect. Read value is always 0. ", }, { col => 3, table => 0, text => "PFREQCHG must be written to 1 when the data ", }, { col => 3, table => 0, text => "synchronizer is started by setting DSYNSEL to 1, ", }, { col => 3, table => 0, text => "TMDSA_DUAL_LINK_ENABLE is reprogrammed, or either ", }, { col => 3, table => 0, text => "PCLK_TMDSA or PCLK_TMDSA_DIRECT (IDCLK) is ", }, { col => undef, table => undef, text => "reprogrammed or stopped and restarted.", }, { col => undef, table => undef, text => "TMDSA Data Sychronization Control", }, { col => undef, table => undef, text => "TMDSA_CTL0_1_GEN_CNTL - RW - 32 bits - [GpuF0MMReg:0x78E0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_CTL0_DATA_SEL" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select data to be used to generate CTL0 pattern (selected ", }, { col => undef, table => undef, text => "fields are ORed together)" }, { col => undef, table => undef, text => "[0]: Display Enable" }, { col => undef, table => undef, text => "[1]: VSYNC" }, { col => undef, table => undef, text => "[2]: HSYNC" }, { col => undef, table => undef, text => "[3] Random data" }, { col => undef, table => undef, text => "TMDSA_CTL0_DATA_DELAY" }, { col => undef, table => undef, text => "6:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Number of pixel clocks to delay CTL0 data", }, { col => undef, table => undef, text => " 0=CTL0 data is delayed 0 pixel clocks ", }, { col => undef, table => undef, text => " 1=CTL0 data is delayed 1 pixel clocks ", }, { col => undef, table => undef, text => " 2=CTL0 data is delayed 2 pixel clocks ", }, { col => undef, table => undef, text => " 3=CTL0 data is delayed 3 pixel clocks ", }, { col => undef, table => undef, text => " 4=CTL0 data is delayed 4 pixel clocks ", }, { col => undef, table => undef, text => " 5=CTL0 data is delayed 5 pixel clocks ", }, { col => undef, table => undef, text => " 6=CTL0 data is delayed 6 pixel clocks ", }, { col => undef, table => undef, text => " 7=CTL0 data is delayed 7 pixel clocks ", }, { col => undef, table => undef, text => "TMDSA_CTL0_DATA_INVERT" }, { col => undef, table => undef, text => 7 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to invert CTL0 data" }, { col => undef, table => undef, text => " 0=CTL0 data is normal " }, { col => undef, table => undef, text => " 1=CTL0 data is inverted " }, { col => undef, table => undef, text => "TMDSA_CTL0_DATA_MODULATION" }, { col => undef, table => undef, text => "9:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CTL0 data modulation control" }, { col => undef, table => undef, text => " 0=CTL0 data is not modulated ", }, { col => undef, table => undef, text => " 1=CTL0 data is modulated by bit 0 of 2 bit counter ", }, { col => undef, table => undef, text => " 2=CTL0 data is modulated by bit 1 of 2 bit counter ", }, { col => undef, table => undef, text => " 3=CTL0 data is modulated every time 2 bit counter ", }, { col => undef, table => undef, text => "overflows " }, { col => undef, table => undef, text => "TMDSA_CTL0_USE_FEEDBACK_PATH" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable CTL0 internal feedback path", }, { col => undef, table => undef, text => "TMDSA_CTL0_FB_SYNC_CONT" }, { col => undef, table => undef, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to force continunous toggle on CTL0 internal ", }, { col => undef, table => undef, text => "feedback path" }, { col => undef, table => undef, text => "TMDSA_CTL0_PATTERN_OUT_EN" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select CTL0 output data" }, { col => undef, table => undef, text => " 0=Register value " }, { col => undef, table => undef, text => " 1=Pattern generator output " }, { col => undef, table => undef, text => "TMDSA_CTL1_DATA_SEL" }, { col => undef, table => undef, text => "19:16" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select data to be used to generate CTL1 pattern (selected ", }, { col => undef, table => undef, text => "fields are ORed together)" }, { col => undef, table => undef, text => "[0]: Display Enable" }, { col => undef, table => undef, text => "[1]: VSYNC" }, { col => undef, table => undef, text => "[2]: HSYNC" }, { col => undef, table => undef, text => "[3] Always (blank time)" }, ], }, { num => 313, text => [ { col => 0, table => 0, text => "TMDSA_CTL1_DATA_DELAY" }, { col => 1, table => 0, text => "22:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of pixel clocks to delay CTL1 data", }, { col => 3, table => 0, text => " 0=CTL1 data is delayed 0 pixel clocks ", }, { col => 3, table => 0, text => " 1=CTL1 data is delayed 1 pixel clocks ", }, { col => 3, table => 0, text => " 2=CTL1 data is delayed 2 pixel clocks ", }, { col => 3, table => 0, text => " 3=CTL1 data is delayed 3 pixel clocks ", }, { col => 3, table => 0, text => " 4=CTL1 data is delayed 4 pixel clocks ", }, { col => 3, table => 0, text => " 5=CTL1 data is delayed 5 pixel clocks ", }, { col => 3, table => 0, text => " 6=CTL1 data is delayed 6 pixel clocks ", }, { col => 3, table => 0, text => " 7=CTL1 data is delayed 7 pixel clocks ", }, { col => 0, table => 0, text => "TMDSA_CTL1_DATA_INVERT" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to invert CTL1 data" }, { col => 3, table => 0, text => " 0=CTL1 data is normal " }, { col => 3, table => 0, text => " 1=CTL1 data is inverted " }, { col => 0, table => 0, text => "TMDSA_CTL1_DATA_MODULATION" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "CTL1 data modulation control" }, { col => 3, table => 0, text => " 0=CTL1 data is not modulated " }, { col => 3, table => 0, text => " 1=CTL1 data is modulated by bit 0 of 2 bit counter ", }, { col => 3, table => 0, text => " 2=CTL1 data is modulated by bit 1 of 2 bit counter ", }, { col => 3, table => 0, text => " 3=CTL1 data is modulated every time 2 bit counter ", }, { col => 3, table => 0, text => "overflows " }, { col => 0, table => 0, text => "TMDSA_CTL1_USE_FEEDBACK_PATH" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable CTL1 internal feedback path", }, { col => 0, table => 0, text => "TMDSA_CTL1_FB_SYNC_CONT" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to force continunous toggle on CTL1 internal ", }, { col => 3, table => 0, text => "feedback path" }, { col => 0, table => 0, text => "TMDSA_CTL1_PATTERN_OUT_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select CTL1 output data" }, { col => 3, table => 0, text => " 0=Register value " }, { col => 3, table => 0, text => " 1=Pattern generator output " }, { col => 0, table => 0, text => "TMDSA_2BIT_COUNTER_EN" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable 2-bit data modulation counter", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => undef, table => undef, text => "TMDSA_CTL2_3_GEN_CNTL - RW - 32 bits - [GpuF0MMReg:0x78E4]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_CTL2_DATA_SEL" }, { col => undef, table => undef, text => "3:0" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select data to be used to generate CTL2 pattern (selected ", }, { col => undef, table => undef, text => "fields are ORed together)" }, { col => undef, table => undef, text => "[0]: Display Enable" }, { col => undef, table => undef, text => "[1]: VSYNC" }, { col => undef, table => undef, text => "[2]: HSYNC" }, { col => undef, table => undef, text => "[3] Always (blank time)" }, { col => undef, table => undef, text => "TMDSA_CTL2_DATA_DELAY" }, { col => undef, table => undef, text => "6:4" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Number of pixel clocks to delay CTL2 data", }, { col => undef, table => undef, text => " 0=CTL2 data is delayed 0 pixel clocks ", }, { col => undef, table => undef, text => " 1=CTL2 data is delayed 1 pixel clocks ", }, { col => undef, table => undef, text => " 2=CTL2 data is delayed 2 pixel clocks ", }, { col => undef, table => undef, text => " 3=CTL2 data is delayed 3 pixel clocks ", }, { col => undef, table => undef, text => " 4=CTL2 data is delayed 4 pixel clocks ", }, { col => undef, table => undef, text => " 5=CTL2 data is delayed 5 pixel clocks ", }, { col => undef, table => undef, text => " 6=CTL2 data is delayed 6 pixel clocks ", }, { col => undef, table => undef, text => " 7=CTL2 data is delayed 7 pixel clocks ", }, { col => undef, table => undef, text => "TMDSA_CTL2_DATA_INVERT" }, { col => undef, table => undef, text => 7 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to invert CTL2 data" }, { col => undef, table => undef, text => " 0=CTL2 data is normal " }, { col => undef, table => undef, text => " 1=CTL2 data is inverted " }, { col => undef, table => undef, text => "TMDSA_CTL2_DATA_MODULATION" }, { col => undef, table => undef, text => "9:8" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "CTL2 data modulation control" }, { col => undef, table => undef, text => " 0=CTL2 data is not modulated ", }, { col => undef, table => undef, text => " 1=CTL2 data is modulated by bit 0 of 2 bit counter ", }, { col => undef, table => undef, text => " 2=CTL2 data is modulated by bit 1 of 2 bit counter ", }, { col => undef, table => undef, text => " 3=CTL2 data is modulated every time 2 bit counter ", }, { col => undef, table => undef, text => "overflows " }, { col => undef, table => undef, text => "TMDSA_CTL2_USE_FEEDBACK_PATH" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable CTL2 internal feedback path", }, ], }, { num => 314, text => [ { col => 0, table => 0, text => "TMDSA_CTL2_FB_SYNC_CONT" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to force continunous toggle on CTL2 internal ", }, { col => 3, table => 0, text => "feedback path" }, { col => 0, table => 0, text => "TMDSA_CTL2_PATTERN_OUT_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select CTL2 output data" }, { col => 3, table => 0, text => " 0=Register value " }, { col => 3, table => 0, text => " 1=Pattern generator output " }, { col => 0, table => 0, text => "TMDSA_CTL3_DATA_SEL" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select data to be used to generate CTL3 pattern (selected ", }, { col => 3, table => 0, text => "fields are ORed together)" }, { col => 3, table => 0, text => "[0]: Display Enable" }, { col => 3, table => 0, text => "[1]: VSYNC" }, { col => 3, table => 0, text => "[2]: HSYNC" }, { col => 3, table => 0, text => "[3] Always (blank time)" }, { col => 0, table => 0, text => "TMDSA_CTL3_DATA_DELAY" }, { col => 1, table => 0, text => "22:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Number of pixel clocks to delay CTL3 data", }, { col => 3, table => 0, text => " 0=CTL3 data is delayed 0 pixel clocks ", }, { col => 3, table => 0, text => " 1=CTL3 data is delayed 1 pixel clocks ", }, { col => 3, table => 0, text => " 2=CTL3 data is delayed 2 pixel clocks ", }, { col => 3, table => 0, text => " 3=CTL3 data is delayed 3 pixel clocks ", }, { col => 3, table => 0, text => " 4=CTL3 data is delayed 4 pixel clocks ", }, { col => 3, table => 0, text => " 5=CTL3 data is delayed 5 pixel clocks ", }, { col => 3, table => 0, text => " 6=CTL3 data is delayed 6 pixel clocks ", }, { col => 3, table => 0, text => " 7=CTL3 data is delayed 7 pixel clocks ", }, { col => 0, table => 0, text => "TMDSA_CTL3_DATA_INVERT" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to invert CTL3 data" }, { col => 3, table => 0, text => " 0=CTL3 data is normal " }, { col => 3, table => 0, text => " 1=CTL3 data is inverted " }, { col => 0, table => 0, text => "TMDSA_CTL3_DATA_MODULATION" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "CTL3 data modulation control" }, { col => 3, table => 0, text => " 0=CTL3 data is not modulated " }, { col => 3, table => 0, text => " 1=CTL3 data is modulated by bit 0 of 2 bit counter ", }, { col => 3, table => 0, text => " 2=CTL3 data is modulated by bit 1 of 2 bit counter ", }, { col => 3, table => 0, text => " 3=CTL3 data is modulated every time 2 bit counter ", }, { col => 3, table => 0, text => "overflows " }, { col => 0, table => 0, text => "TMDSA_CTL3_USE_FEEDBACK_PATH" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable CTL3 internal feedback path", }, { col => 0, table => 0, text => "TMDSA_CTL3_FB_SYNC_CONT" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to force continunous toggle on CTL3 internal ", }, { col => 3, table => 0, text => "feedback path" }, { col => 0, table => 0, text => "TMDSA_CTL3_PATTERN_OUT_EN" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select CTL3 output data" }, { col => 3, table => 0, text => " 0=Register value " }, { col => 3, table => 0, text => " 1=Pattern generator output " }, { col => undef, table => undef, text => "TMDSA_TRANSMITTER_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7904]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_TX0_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link0 enable (ILNK0EN)(set to 1 whenever TMDS ", }, { col => undef, table => undef, text => "is enabled)" }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "TMDSA_LNKC0EN" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA clock channel enable (ICHCEN)(set to 1 whenever ", }, { col => undef, table => undef, text => "TMDS is enabled)" }, { col => undef, table => undef, text => "TMDSA_LNKD00EN" }, { col => undef, table => undef, text => 2 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link0 data channel 0 enable (ICHD0EN)(set to 1 ", }, { col => undef, table => undef, text => "whenever TMDS is enabled)" }, { col => undef, table => undef, text => "TMDSA_LNKD01EN" }, { col => undef, table => undef, text => 3 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link0 data channel 1 enable (ICHD1EN)(set to 1 ", }, { col => undef, table => undef, text => "whenever TMDS is enabled)" }, { col => undef, table => undef, text => "TMDSA_LNKD02EN" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link0 data channel 2 enable (ICHD2EN)(set to 1 ", }, { col => undef, table => undef, text => "whenever TMDS is enabled)" }, { col => undef, table => undef, text => "TMDSA_TX1_ENABLE" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link1 enable (ILNKD1EN)(set to 1 whenever TMDS ", }, { col => undef, table => undef, text => "is enabled in dual-link mode)" }, { col => undef, table => undef, text => "TMDSA_LNKC1EN" }, { col => undef, table => undef, text => 9 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA_LNKD10EN" }, { col => undef, table => undef, text => 10 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link1 data channel 0 enable (ICHD3EN)(set to 1 ", }, { col => undef, table => undef, text => "whenever TMDS is enabled in dual-link mode)", }, { col => undef, table => undef, text => "TMDSA_LNKD11EN" }, { col => undef, table => undef, text => 11 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA link1 data channel 1 enable (ICHD4EN)(set to 1 ", }, { col => undef, table => undef, text => "whenever TMDS is enabled in dual-link mode)", }, ], }, { num => 315, text => [ { col => 0, table => 0, text => "TMDSA_LNKD12EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "TMDSA link1 data channel 2 enable (ICHD5EN)(set to 1 ", }, { col => 3, table => 0, text => "whenever TMDS is enabled in dual-link mode)", }, { col => 0, table => 0, text => "TMDSA_TX_ENABLE_HPD_MASK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0:Disallow" }, { col => 3, table => 0, text => "1:Allow override of TMDSA_TXX_ENABLE by HPD on ", }, { col => 3, table => 0, text => "disconnect" }, { col => 3, table => 0, text => " 0=Result from HPD circuit can not override ", }, { col => 3, table => 0, text => "TMDSA_TXX_ENABLE " }, { col => 3, table => 0, text => " 1=Result from HPD circuit can override ", }, { col => 3, table => 0, text => "TMDSA_TXX_ENABLE on disconnect " }, { col => 0, table => 0, text => "TMDSA_LNKCEN_HPD_MASK" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0:Disallow" }, { col => 3, table => 0, text => "1:Allow override of TMDSA_LNKCXEN by HPD on ", }, { col => 3, table => 0, text => "disconnect" }, { col => 3, table => 0, text => " 0=Result from HPD circuit can not override ", }, { col => 3, table => 0, text => "TMDSA_LNKC0EN " }, { col => 3, table => 0, text => " 1=Result from HPD circuit overrides TMDSA_LNKC0EN ", }, { col => 3, table => 0, text => "on disconnect " }, { col => 0, table => 0, text => "TMDSA_LNKDEN_HPD_MASK" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "0:Disallow" }, { col => 3, table => 0, text => "1:Allow override of TMDSA_LNKDXEN by HPD on ", }, { col => 3, table => 0, text => "disconnect" }, { col => 3, table => 0, text => " 0=Result from HPD circuit can not override ", }, { col => 3, table => 0, text => "TMDSA_LNKDXEN " }, { col => 3, table => 0, text => " 1=Result from HPD circuit overrides TMDSA_LNKDXEN ", }, { col => 3, table => 0, text => "on disconnect " }, { col => "heading", table => 1, text => "TMDSA_LOAD_DETECT - RW - 32 bits - [GpuF0MMReg:0x7908]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_LOAD_DETECT_ENABLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "0: Disable" }, { col => 3, table => 1, text => "1: Enable TMDSA macro load detect functionDrives IMSEN ", }, { col => 3, table => 1, text => "macro input" }, { col => 0, table => 1, text => "TMDSA_LOAD_DETECT (R)" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "From TMDSA macro OMSEN output" }, { col => 3, table => 1, text => "0: No load detected" }, { col => 3, table => 1, text => "1: Load detected" }, { col => "heading", table => 2, text => "TMDSA_PLL_ADJUST - RW - 32 bits - [GpuF0MMReg:0x790C]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_PLL_CP_GAIN" }, { col => 1, table => 2, text => "5:0" }, { col => 2, table => 2, text => "0xb" }, { col => 3, table => 2, text => "tmds macro channel A&B charge pump gain control", }, { col => 0, table => 2, text => "TMDSA_PLL_VCO_GAIN" }, { col => 1, table => 2, text => "13:8" }, { col => 2, table => 2, text => "0x7" }, { col => 3, table => 2, text => "tmds macro channel A&B vco control" }, { col => 0, table => 2, text => "TMDSA_PLL_DUTY_CYCLE" }, { col => 1, table => 2, text => "17:16" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "tmds macro channel A&B clock duty cycle control", }, { col => undef, table => undef, text => "TMDSA_TRANSMITTER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7910]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "TMDSA_PLL_ENABLE" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "TMDSA transmitter's PLL enable. This can power down the ", }, { col => undef, table => undef, text => "PLL." }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, ], }, { num => 317, text => [ { col => 0, table => 0, text => "TMDSA_BYPASS_PLLA" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Controls ICHCSELA pin on TMDSA macro" }, { col => 3, table => 0, text => "0: Coherent mode: transmitted A clock is PLL output", }, { col => 3, table => 0, text => "1: Incoherent mode: transmitted A clock is PLL input", }, { col => 3, table => 0, text => " 0=0: TMDS transmitter A is in coherent mode ", }, { col => 3, table => 0, text => " 1=1: Tmds transmitter A is in incoherent mode ", }, { col => 0, table => 0, text => "TMDSA_BYPASS_PLLB" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "Controls ICHCSELA pin on TMDSA macro" }, { col => 3, table => 0, text => "0: Coherent mode: transmitted B clock is PLL output", }, { col => 3, table => 0, text => "1: Incoherent mode: transmitted B clock is PLL input", }, { col => 3, table => 0, text => " 0=0: TMDS transmitter B is in coherent mode ", }, { col => 3, table => 0, text => " 1=1: Tmds transmitter B is in incoherent mode ", }, { col => 0, table => 0, text => "TMDSA_INPUT_TEST_CLK_SEL1" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls ITCLKSEL1 pin on TMDSA macro" }, { col => 0, table => 0, text => "TMDSA_INPUT_TEST_CLK_SEL2" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls ITCLKSEL2 pin on TMDSA macro" }, { col => "heading", table => 1, text => "TMDSA_REG_TEST_OUTPUTA - RW - 32 bits - [GpuF0MMReg:0x7914]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_REG_TEST_OUTPUTA (R)" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Outputs of the 10 shift registers (OTDATX[9:0]) from one of ", }, { col => 3, table => 1, text => "the channels during test mode." }, { col => 0, table => 1, text => "TMDSA_TEST_CNTLA" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selects which of 3 register test output channels from ", }, { col => 3, table => 1, text => "TMDSA macro is visible in " }, { col => 3, table => 1, text => "TMDSA_REG_TEST_OUTPUTA." }, { col => 3, table => 1, text => " 0=OTDATA0 " }, { col => 3, table => 1, text => " 1=OTDATA1 " }, { col => 3, table => 1, text => " 2=OTDATA2 " }, { col => 3, table => 1, text => " 3=N/A " }, { col => 0, table => 1, text => "TMDSA_TEST_OUTPUT_SELECT" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "ENABLE TEST_OUTPUTA & TEST_OUTPUTB" }, { col => "heading", table => 2, text => "TMDSA_TRANSMITTER_DEBUG - RW - 32 bits - [GpuF0MMReg:0x7918]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "TMDSA_PLL_DEBUG" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Drives ITPL pins on TMDSA macro" }, { col => 0, table => 2, text => "TMDSA_TX_DEBUG" }, { col => 1, table => 2, text => "15:8" }, { col => 2, table => 2, text => "0x0" }, { col => undef, table => undef, text => "Drives ITX pins on TMDSA macro" }, { col => undef, table => undef, text => "Reserved for debugging purposes" }, { col => "heading", table => 3, text => "TMDSA_DITHER_RAND_SEED - RW - 32 bits - [GpuF0MMReg:0x791C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "TMDSA_RAND_R_SEED" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Seed for random red, the random seed is 1'b1, ", }, { col => 3, table => 3, text => "TMDSA_RAND_R_SEED[2:0], 3TMDSA_RAND_R_SEED ", }, { col => 3, table => 3, text => "= 28 bits" }, { col => 0, table => 3, text => "TMDSA_RAND_G_SEED" }, { col => 1, table => 3, text => "15:8" }, { col => 2, table => 3, text => "0x99" }, { col => 3, table => 3, text => "Seed for random green, the random seed is 1'b1, ", }, { col => 3, table => 3, text => "TMDSA_RAND_G_SEED[2:0], 3TMDSA_RAND_G_SEED ", }, { col => 3, table => 3, text => "= 28 bits" }, { col => 0, table => 3, text => "TMDSA_RAND_B_SEED" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0xdd" }, { col => 3, table => 3, text => "Seed for random bleu, the random seed is 1'b1, ", }, { col => 3, table => 3, text => "TMDSA_RAND_B_SEED[2:0], 3TMDSA_RAND_B_SEED ", }, { col => undef, table => undef, text => "= 28 bits" }, { col => undef, table => undef, text => "programmable seed for random dithering", }, ], }, { num => 318, text => [ { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "Digital Video Output (DVO) Registers", }, { col => "heading", table => 0, text => "TMDSA_TRANSMITTER_ADJUST - RW - 32 bits - [GpuF0MMReg:0x7920]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "TMDSA_TX_VOLTAGE_SWING_A" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => "tmds macro transmitter A, voltage swing control", }, { col => 0, table => 0, text => "TMDSA_TX_VOLTAGE_SWING_B" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0xa" }, { col => 3, table => 0, text => "tmds macro transmitter B, voltage swing control", }, { col => 0, table => 0, text => "TMDSA_TXPCA" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter A, pulse current control", }, { col => 0, table => 0, text => "TMDSA_TXPCB" }, { col => 1, table => 0, text => "13:12" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter B, pulse current control", }, { col => 0, table => 0, text => "TMDSA_TXPWA" }, { col => 1, table => 0, text => "17:16" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter A, pulse width control", }, { col => 0, table => 0, text => "TMDSA_TXPWB" }, { col => 1, table => 0, text => "21:20" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter A, pulse width control", }, { col => 0, table => 0, text => "TMDSA_TX_VS_COMPA" }, { col => 1, table => 0, text => "25:24" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter A, voltage swing compensation ", }, { col => 3, table => 0, text => "control" }, { col => 0, table => 0, text => "TMDSA_TX_VS_COMPB" }, { col => 1, table => 0, text => "29:28" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "tmds macro transmitter B, voltage swing compensation ", }, { col => 3, table => 0, text => "control" }, { col => "heading", table => 1, text => "TMDSA_REG_TEST_OUTPUTB - RW - 32 bits - [GpuF0MMReg:0x7924]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "TMDSA_REG_TEST_OUTPUTB (R)" }, { col => 1, table => 1, text => "9:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Outputs of the 10 shift registers (OTDATX[9:0]) from one of ", }, { col => 3, table => 1, text => "the channels during test mode." }, { col => 0, table => 1, text => "TMDSA_TEST_CNTLB" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Selects which of 3 register test output channels from ", }, { col => 3, table => 1, text => "TMDSA macro is visible in " }, { col => 3, table => 1, text => "TMDSA_REG_TEST_OUTPUTB." }, { col => 3, table => 1, text => " 0=OTDATB0 " }, { col => 3, table => 1, text => " 1=OTDATB1 " }, { col => 3, table => 1, text => " 2=OTDATB2 " }, { col => 3, table => 1, text => " 3=N/A " }, { col => "heading", table => 2, text => "DVOA_ENABLE - RW - 32 bits - [GpuF0MMReg:0x7980]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DVOA_ENABLE" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable for DVO" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DVOA_PIXEL_ENCODING" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Selects pixel encoding format" }, { col => 3, table => 2, text => " 0=RGB 4:4:4 or YCBCR 4:4:4 " }, { col => 3, table => 2, text => " 1=YCbCr 4:2:2 " }, { col => "heading", table => 3, text => "DVOA_SOURCE_SELECT - RW - 32 bits - [GpuF0MMReg:0x7984]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DVOA_SOURCE_SELECT" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Select between 1st and 2nd display streams", }, { col => 3, table => 3, text => " 0=CRTC1 data is used " }, { col => 3, table => 3, text => " 1=CRTC2 data is used " }, ], }, { num => 319, text => [ { col => 0, table => 0, text => "DVOA_SYNC_SELECT" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select between SYNCA and SYNCB signals from CRTC", }, { col => 3, table => 0, text => " 0=HSYNC_A & VSYNC_A from the selected CRTC are ", }, { col => 3, table => 0, text => "used " }, { col => 3, table => 0, text => " 1=HSYNC_B & VSYNC_B from the selected CRTC are ", }, { col => 3, table => 0, text => "used " }, { col => 0, table => 0, text => "DVOA_STEREOSYNC_SELECT" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select between CRTC1 and CRTC2 stereosync signals", }, { col => 3, table => 0, text => " 0=DVOA Stereosync from CRTC1 used " }, { col => undef, table => undef, text => " 1=DVOA Stereosync from CRTC2 used ", }, { col => undef, table => undef, text => "Source Select control for Data, H/VSYNC & Stereosync", }, { col => "heading", table => 1, text => "DVOA_BIT_DEPTH_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7988]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DVOA_TRUNCATE_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable bit reduction by truncation" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DVOA_TRUNCATE_DEPTH" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select truncation depth" }, { col => 3, table => 1, text => " 0=18bpp " }, { col => 3, table => 1, text => " 1=24bpp " }, { col => 0, table => 1, text => "DVOA_SPATIAL_DITHER_EN" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable bit reduction by spatial (random) dither", }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DVOA_SPATIAL_DITHER_MODE" }, { col => 1, table => 1, text => "10:9" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "LFSR seed selection. 0: Seed pattern A(a,a), 1: seed ", }, { col => 3, table => 1, text => "pattern A(a, ~a), 2: seed pattern AABB(a, ~a, b, ~b), 3: ", }, { col => 3, table => 1, text => "seed pattern AABBCC(a, ~a, b, ~b, c, ~c)", }, { col => 0, table => 1, text => "DVOA_SPATIAL_DITHER_DEPTH" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0Select spatial dither depth" }, { col => 3, table => 1, text => " 0=18bpp " }, { col => 3, table => 1, text => " 1=24bpp " }, { col => 0, table => 1, text => "DVOA_FRAME_RANDOM_ENABLE" }, { col => 1, table => 1, text => 13 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Control the LFSR reset, every frame or once at startup", }, { col => 3, table => 1, text => " 0=0: RGB LFSR are reset every frame, 1: reset once at ", }, { col => 3, table => 1, text => "startup/no reset on every frame " }, { col => 0, table => 1, text => "DVOA_RGB_RANDOM_ENABLE" }, { col => 1, table => 1, text => 14 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Control the pseudo-random number to be dithered on RGB", }, { col => 3, table => 1, text => " 0=0: RGB use x^28+x^3+1 random number ", }, { col => 3, table => 1, text => " 1=1: R dithered with x^28+x^3+1, G dithered with ", }, { col => 3, table => 1, text => "x^28+x^9+1 and B dithered with x^28+x^13+1 ", }, { col => 0, table => 1, text => "DVOA_HIGHPASS_RANDOM_ENABLE" }, { col => 1, table => 1, text => 15 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Highpass filter on RGB dithered channels", }, { col => 3, table => 1, text => " 0=0: highpass filter is disable, 1: highpass filter is enable ", }, { col => 3, table => 1, text => "on RGB " }, { col => 0, table => 1, text => "DVOA_TEMPORAL_DITHER_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable bit reduction by temporal dither (frame mod.)", }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DVOA_TEMPORAL_DITHER_DEPTH" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select temporal dither depth" }, { col => 3, table => 1, text => " 0=18bpp " }, { col => 3, table => 1, text => " 1=24bpp " }, { col => 0, table => 1, text => "DVOA_TEMPORAL_DITHER_OFFSET" }, { col => 1, table => 1, text => "22:21" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Add offset to RGB channel before temporal dithering ", }, { col => 3, table => 1, text => "operation" }, { col => 3, table => 1, text => " 0=For 24bpp: add offset[1:0] to RGB channels ", }, { col => 3, table => 1, text => " 1=For 18bpp: Add offset[1:0]x4 to RGB channels ", }, { col => 0, table => 1, text => "DVOA_TEMPORAL_LEVEL" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Gray level select (2 or 4 levels)" }, { col => 3, table => 1, text => " 0=Gray level 2 " }, { col => 3, table => 1, text => " 1=Gray level 4 " }, { col => 0, table => 1, text => "DVOA_TEMPORAL_DITHER_RESET" }, { col => 1, table => 1, text => 25 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Reset temporal dither (frame modulation)", }, { col => 3, table => 1, text => " 0=Temporal Dither Ready " }, { col => undef, table => undef, text => " 1=Reset Temporal Dither Circuit ", }, { col => undef, table => undef, text => "Control the method in which the data input into the DVO block is reduced and the length it is reduced to.", }, ], }, { num => 320, text => [ { col => "heading", table => 0, text => "DVOA_OUTPUT - RW - 32 bits - [GpuF0MMReg:0x798C]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DVOA_OUTPUT_ENABLE_MODE" }, { col => 1, table => 0, text => "1:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Ouput mode for DVO" }, { col => 3, table => 0, text => " 0=disabled " }, { col => 3, table => 0, text => " 1=lower 12 output en " }, { col => 3, table => 0, text => " 2=upper 12 output en " }, { col => 3, table => 0, text => " 3=all 24 output enable " }, { col => 0, table => 0, text => "DVOA_CLOCK_MODE" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Reserved" }, { col => 3, table => 0, text => " 0=differential clocking enabled " }, { col => undef, table => undef, text => " 1=single ended clocking enabled ", }, { col => undef, table => undef, text => "Output enable control for DVO pads.", }, { col => undef, table => undef, text => "DVOA_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7990]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DVOA_RATE_SELECT" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select between DDR and SDR modes", }, { col => undef, table => undef, text => " 0=DDR Speed " }, { col => undef, table => undef, text => " 1=SDR Speed using NPL A pin " }, { col => undef, table => undef, text => "DVOA_SDRCLK_SEL" }, { col => undef, table => undef, text => 1 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Select SDR DVOCLK using clk from A pin or CLK0 pin in ", }, { col => undef, table => undef, text => "NPL" }, { col => undef, table => undef, text => " 0=use NPL A input clock " }, { col => undef, table => undef, text => " 1=use CLK0 input clock " }, { col => undef, table => undef, text => "DVOA_DUAL_CHANNEL_EN" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable Dual Channel DVO Mode" }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DVOA_RESET_FIFO (W)" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Write 1 to force reset of DVO mesochronous fifo", }, { col => undef, table => undef, text => "DVOA_SYNC_PHASE" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x1" }, { col => undef, table => undef, text => "Determine whether to reset phase signal on frame pulse", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DVOA_INVERT_DVOCLK" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to invert 'clock' going to d input of dvoclk pad", }, { col => undef, table => undef, text => " 0=Don't Invert " }, { col => undef, table => undef, text => " 1=Invert " }, { col => undef, table => undef, text => "DVOA_COLOR_FORMAT" }, { col => undef, table => undef, text => "25:24" }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => " 0=8-bit DVO display " }, { col => undef, table => undef, text => " 1=Twin Single Link 10-bit mode ", }, { col => undef, table => undef, text => " 2=Dual-Link 10-bit mode " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "DVOA_REORDER_BITS" }, { col => undef, table => undef, text => 28 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Reorder DVO bits output = input 1:0, input 7:2", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => "heading", table => 1, text => "DVOA_CRC_EN - RW - 32 bits - [GpuF0MMReg:0x7994]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DVOA_CRC_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable DVO CRC" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DVOA_CRC_CONT_EN" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select between one shot and continous mode", }, { col => 3, table => 1, text => " 0=CRC is calculated over 1 frame " }, { col => 3, table => 1, text => " 1=CRC is continuously calculated for every frame ", }, { col => 0, table => 1, text => "DVOA_CRC2_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable DVO output CRC2" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, ], }, { num => 321, text => [ { col => "heading", table => 0, text => "DVOA_CRC_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7998]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DVOA_CRC_FIELD" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Controls which field polarity starts the DVO CRC block after ", }, { col => 3, table => 0, text => "DAC_CRC_EN is set high" }, { col => 3, table => 0, text => " 0=Even field begins CRC calculation " }, { col => 3, table => 0, text => " 1=Odd field begins CRC calculation " }, { col => 0, table => 0, text => "DVOA_CRC_ONLY_BLANKb" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Determines whether CRC is calculated for the whole frame ", }, { col => 3, table => 0, text => "or only during non-blank period for DVO" }, { col => 3, table => 0, text => " 0=CRC calculated over entire field " }, { col => 3, table => 0, text => " 1=CRC calculated only during BLANKb " }, { col => "heading", table => 1, text => "DVOA_CRC_SIG_MASK1 - RW - 32 bits - [GpuF0MMReg:0x799C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DVOA_CRC_SIG_BLUE_MASK" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0xff" }, { col => 3, table => 1, text => "Mask bits for DVO B channel CRC." }, { col => 0, table => 1, text => "DVOA_CRC_SIG_GREEN_MASK" }, { col => 1, table => 1, text => "23:16" }, { col => 2, table => 1, text => "0xff" }, { col => undef, table => undef, text => "Mask bits for DVO G channel CRC.", }, { col => undef, table => undef, text => "Select which data the CRC calculation is performed on.", }, { col => "heading", table => 2, text => "DVOA_CRC_SIG_MASK2 - RW - 32 bits - [GpuF0MMReg:0x79A0]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DVOA_CRC_SIG_RED_MASK" }, { col => 1, table => 2, text => "7:0" }, { col => 2, table => 2, text => "0xff" }, { col => 3, table => 2, text => "Mask bits for DVO R channel CRC." }, { col => 0, table => 2, text => "DVOA_CRC_SIG_CONTROL_MASK" }, { col => 1, table => 2, text => "18:16" }, { col => 2, table => 2, text => "0x7" }, { col => 3, table => 2, text => "Mask bits for DVO control signal CRC" }, { col => 3, table => 2, text => "Bit 18: Vsync signal" }, { col => 3, table => 2, text => "Bit 17: Hsync Signal" }, { col => undef, table => undef, text => "Bit 16: Data Enable" }, { col => undef, table => undef, text => "Select which control signals the CRC calculation is performed on.", }, { col => "heading", table => 3, text => "DVOA_CRC_SIG_RESULT1 - RW - 32 bits - [GpuF0MMReg:0x79A4]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DVOA_CRC_SIG_BLUE (R)" }, { col => 1, table => 3, text => "7:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "CRC signature value for DVO B channel CRC.", }, { col => 0, table => 3, text => "DVOA_CRC_SIG_GREEN (R)" }, { col => 1, table => 3, text => "23:16" }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for DVO G channel CRC.", }, { col => undef, table => undef, text => "DVOA Data CRC Results" }, { col => "heading", table => 4, text => "DVOA_CRC_SIG_RESULT2 - RW - 32 bits - [GpuF0MMReg:0x79A8]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DVOA_CRC_SIG_RED (R)" }, { col => 1, table => 4, text => "7:0" }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "CRC signature value for DVO R channel CRC.", }, { col => 0, table => 4, text => "DVOA_CRC_SIG_CONTROL (R)" }, { col => 1, table => 4, text => "18:16" }, { col => 2, table => 4, text => "0x0" }, { col => undef, table => undef, text => "CRC signature value for DVO control CRC.", }, { col => undef, table => undef, text => "DVOA DATA and Control CRC Results", }, ], }, { num => 322, text => [ { col => "heading", table => 0, text => "DVOA_CRC2_SIG_MASK - RW - 32 bits - [GpuF0MMReg:0x79AC]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DVOA_CRC2_SIG_MASK" }, { col => 1, table => 0, text => "26:0" }, { col => 2, table => 0, text => "0x7ffffff" }, { col => 3, table => 0, text => "Mask bits for DVO output CRC2" }, { col => 3, table => 0, text => "Bit 26: Vsync signal" }, { col => 3, table => 0, text => "Bit 25: Hsync Signal" }, { col => 3, table => 0, text => "Bit 24: Data Enable" }, { col => undef, table => undef, text => "Bit 23-0:DVO Data" }, { col => undef, table => undef, text => "Control for secondary DVO CRC" }, { col => "heading", table => 1, text => "DVOA_CRC2_SIG_RESULT - RW - 32 bits - [GpuF0MMReg:0x79B0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DVOA_CRC2_SIG_RESULT (R)" }, { col => 1, table => 1, text => "26:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "CRC2 signature value for DVO output", }, { col => undef, table => undef, text => "CRC2 signature value for DVO output", }, { col => "heading", table => 2, text => "DVOA_STRENGTH_CONTROL - RW - 32 bits - [GpuF0MMReg:0x79B4]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DVOA_SP" }, { col => 1, table => 2, text => "3:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Strength of pull-up section of output buffer for DVO signals.", }, { col => 0, table => 2, text => "DVOA_SN" }, { col => 1, table => 2, text => "7:4" }, { col => 2, table => 2, text => "0x6" }, { col => 3, table => 2, text => "Strength of pull-down section of output buffer for DVO ", }, { col => 3, table => 2, text => "signals." }, { col => 0, table => 2, text => "DVOACLK_SP" }, { col => 1, table => 2, text => "11:8" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Strength of pull-up section of output buffer for DVO clock ", }, { col => 3, table => 2, text => "output." }, { col => 0, table => 2, text => "DVOACLK_SN" }, { col => 1, table => 2, text => "15:12" }, { col => 2, table => 2, text => "0x6" }, { col => 3, table => 2, text => "Strength of pull-down section of output buffer for DVO clock ", }, { col => 3, table => 2, text => "output." }, { col => 0, table => 2, text => "DVOA_SRP" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Increases slew rate to pull-up section of output buffer for ", }, { col => 3, table => 2, text => "DVO signals." }, { col => 0, table => 2, text => "DVOA_SRN" }, { col => 1, table => 2, text => 17 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Increases slew rate to pull-down section of output buffer for ", }, { col => 3, table => 2, text => "DVO signals." }, { col => 0, table => 2, text => "DVOACLK_SRP" }, { col => 1, table => 2, text => 24 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Increases slew rate to pull-up section of output buffer for ", }, { col => 3, table => 2, text => "DVO clock." }, { col => 0, table => 2, text => "DVOACLK_SRN" }, { col => 1, table => 2, text => 25 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "Increases slew rate to pull-down section of output buffer for ", }, { col => 3, table => 2, text => "DVO clock." }, { col => 0, table => 2, text => "DVOA_LSB_VMODE" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "This pin controls the DVO I/O pad's internal level shifter ", }, { col => 3, table => 2, text => "voltage" }, { col => 3, table => 2, text => "Should be set based on pad output voltage (determined by ", }, { col => 3, table => 2, text => "board voltage regulator)" }, { col => 3, table => 2, text => "This field controls DVODATA[11:0], DVOCNTL and ", }, { col => 3, table => 2, text => "DVOCLK" }, { col => 3, table => 2, text => "Sense is inverted for BIF debug" }, { col => 3, table => 2, text => "0: 1.8V" }, { col => 3, table => 2, text => "1: 3.3V" }, { col => 0, table => 2, text => "DVOA_MSB_VMODE" }, { col => 1, table => 2, text => 29 }, { col => 2, table => 2, text => "0x1" }, { col => 3, table => 2, text => "This pin controls the DVO I/O pad's internal level shifter ", }, { col => 3, table => 2, text => "voltage" }, { col => 3, table => 2, text => "Should be set based on pad output voltage (determined by ", }, { col => 3, table => 2, text => "board voltage regulator)" }, { col => 3, table => 2, text => "This field controls DVODATA[23:12], MVP_DVOCNTL[1:0]", }, { col => 3, table => 2, text => "Sense is inverted for BIF debug" }, { col => 3, table => 2, text => "0: 1.8V" }, { col => 3, table => 2, text => "1: 3.3V" }, ], }, { num => 323, text => [ { col => undef, table => undef, text => " " }, { col => undef, table => undef, text => "Hot Plug Detection Registers" }, { col => "heading", table => 0, text => "DVOA_FORCE_OUTPUT_CNTL - RW - 32 bits - [GpuF0MMReg:0x79B8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DVOA_FORCE_DATA_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable force option on DVOA" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DVOA_FORCE_DATA_SEL" }, { col => 1, table => 0, text => "10:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select which DVOA channels have data forced0=Don't ", }, { col => 3, table => 0, text => "Force, 1=Force" }, { col => 3, table => 0, text => "Bit 0: Blue channel" }, { col => 3, table => 0, text => "Bit 1: Green channel" }, { col => 3, table => 0, text => "Bit 2: Red channel" }, { col => 0, table => 0, text => "DVOA_FORCE_DATA_ON_BLANKb_ON" }, { col => 0, table => 0, text => "LY" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Data is forced only during active region.", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DVOA_HDCP_RGB_PASSTHRU_IN_NO" }, { col => 0, table => 0, text => "NEACTIVE" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable the DVO to let RGB data pass thru in non active ", }, { col => 3, table => 0, text => "data zone when encryption is enable, otherwise RGB data ", }, { col => 3, table => 0, text => "are zero in non active area" }, { col => 0, table => 0, text => "DVOA_HDCP_RANDOM_DATA_EN" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable random data generation (snow) when encryption is ", }, { col => undef, table => undef, text => "required and cipher is not valid.", }, { col => undef, table => undef, text => "DVOA Force Data control register", }, { col => "heading", table => 1, text => "DVOA_FORCE_DATA - RW - 32 bits - [GpuF0MMReg:0x79BC]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DVOA_FORCE_DATA" }, { col => 1, table => 1, text => "7:0" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Data to be forced on R, G & B channels", }, { col => undef, table => undef, text => "Data to be forced on R, G & B channels", }, { col => "heading", table => 2, text => "DC_HOT_PLUG_DETECT1_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D00]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_HOT_PLUG_DETECT1_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable 1st HPD circuit" }, { col => 3, table => 2, text => "When disabled, HPD interrupts will not happen and ", }, { col => 3, table => 2, text => "DC_HOT_PLUG_DETECT1_SENSE will not change", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => undef, table => undef, text => "DC_HOT_PLUG_DETECT1_INT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D04]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DC_HOT_PLUG_DETECT1_INT_STATU" }, { col => undef, table => undef, text => "S (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Interrupt generated by 1st HPD circuit - connect or ", }, { col => undef, table => undef, text => "disconnect has taken place" }, ], }, { num => 324, text => [ { col => 0, table => 0, text => "DC_HOT_PLUG_DETECT1_SENSE (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Connection status of panel being monitored by the 1st HPD ", }, { col => 3, table => 0, text => "circuit" }, { col => 3, table => 0, text => " 0=nothing connected to HPD1 " }, { col => 3, table => 0, text => " 1=panel connected to HPD1 " }, { col => "heading", table => 1, text => "DC_HOT_PLUG_DETECT1_INT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D08]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_HOT_PLUG_DETECT1_INT_ACK " }, { col => 0, table => 1, text => "(W)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Interrupt acknowledge for the 1st HPD circuit", }, { col => 0, table => 1, text => "DC_HOT_PLUG_DETECT1_INT_POLAR" }, { col => 0, table => 1, text => "ITY" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Polarity of 1st HPD circuit" }, { col => 3, table => 1, text => " 0=generate interrupt on disconnect " }, { col => 3, table => 1, text => " 1=generate interrupt on connect " }, { col => 0, table => 1, text => "DC_HOT_PLUG_DETECT1_INT_EN" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable Interrupts on the 1st HPD circuit", }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => "heading", table => 2, text => "DC_HOT_PLUG_DETECT2_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D10]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_HOT_PLUG_DETECT2_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable 2nd HPD circuit" }, { col => 3, table => 2, text => "When disabled, HPD interrupts will not happen and ", }, { col => 3, table => 2, text => "DC_HOT_PLUG_DETECT2_SENSE will not change", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => "heading", table => 3, text => "DC_HOT_PLUG_DETECT2_INT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D14]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_HOT_PLUG_DETECT2_INT_STATU" }, { col => 0, table => 3, text => "S (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Interrupt generated by 2nd HPD circuit - connect or ", }, { col => 3, table => 3, text => "disconnect has taken place" }, { col => 0, table => 3, text => "DC_HOT_PLUG_DETECT2_SENSE (R)" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Connection status of panel being monitored by the 2nd ", }, { col => 3, table => 3, text => "HPD circuit" }, { col => 3, table => 3, text => " 0=nothing connected to HPD2 " }, { col => 3, table => 3, text => " 1=panel connected to HPD2 " }, { col => "heading", table => 4, text => "DC_HOT_PLUG_DETECT2_INT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D18]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DC_HOT_PLUG_DETECT2_INT_ACK " }, { col => 0, table => 4, text => "(W)" }, { col => 1, table => 4, text => 0 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Interrupt acknowledge for the 2nd HPD circuit", }, { col => 0, table => 4, text => "DC_HOT_PLUG_DETECT2_INT_POLAR" }, { col => 0, table => 4, text => "ITY" }, { col => 1, table => 4, text => 8 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => "Polarity of 2nd HPD circuit." }, { col => 3, table => 4, text => " 0=generate interrupt on disconnect " }, { col => 3, table => 4, text => " 1=generate interrupt on connect " }, ], }, { num => 325, text => [ { col => 0, table => 0, text => "DC_HOT_PLUG_DETECT2_INT_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable Interrupts on the 2nd HPD circuit", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => "heading", table => 1, text => "DC_HOT_PLUG_DETECT_CLOCK_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D20]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_HOT_PLUG_DETECT_CLOCK_ENA" }, { col => 0, table => 1, text => "BLE" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Enable HPD clock" }, { col => 3, table => 1, text => " 0=Disable " }, { col => 3, table => 1, text => " 1=Enable " }, { col => 0, table => 1, text => "DC_HOT_PLUG_DETECT_CLOCK_SEL" }, { col => 1, table => 1, text => "17:16" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select HPD reference frequency" }, { col => 3, table => 1, text => " 0=Period = 8192 us " }, { col => 3, table => 1, text => " 1=512 us " }, { col => 3, table => 1, text => " 2=32 us " }, { col => 3, table => 1, text => " 3=2 us " }, { col => "heading", table => 2, text => "DC_HOT_PLUG_DETECT3_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D24]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_HOT_PLUG_DETECT3_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => "heading", table => 3, text => "DC_HOT_PLUG_DETECT3_INT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7D28]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_HOT_PLUG_DETECT3_INT_STATU" }, { col => 0, table => 3, text => "S (R)" }, { col => 1, table => 3, text => "00x0" }, { col => 0, table => 3, text => "DC_HOT_PLUG_DETECT3_SENSE (R)" }, { col => 1, table => 3, text => 1 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => " 0=nothing connected to HPD3 " }, { col => 3, table => 3, text => " 1=panel connected to HPD3 " }, { col => "heading", table => 4, text => "DC_HOT_PLUG_DETECT3_INT_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7D2C]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "DC_HOT_PLUG_DETECT3_INT_ACK " }, { col => 0, table => 4, text => "(W)" }, { col => 1, table => 4, text => "00x0" }, { col => 0, table => 4, text => "DC_HOT_PLUG_DETECT3_INT_POLAR" }, { col => 0, table => 4, text => "ITY" }, { col => 1, table => 4, text => 8 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=generate interrupt on disconnect " }, { col => 3, table => 4, text => " 1=generate interrupt on connect " }, { col => 0, table => 4, text => "DC_HOT_PLUG_DETECT3_INT_EN" }, { col => 1, table => 4, text => 16 }, { col => 2, table => 4, text => "0x0" }, { col => 3, table => 4, text => " 0=Disable " }, { col => 3, table => 4, text => " 1=Enable " }, ], }, { num => 326, text => [ { col => undef, table => undef, text => "2.9.2" }, { col => undef, table => undef, text => "Display Output Control Registers", }, { col => "heading", table => 0, text => "DC_GENERICA - RW - 32 bits - [GpuF0MMReg:0x7DC0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "GENERICA_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable signal for GENERICA pad" }, { col => 0, table => 0, text => "GENERICA_SEL" }, { col => 1, table => 0, text => "11:8" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select signals for GENERICA pad" }, { col => 3, table => 0, text => " 0=DACA Stereosync " }, { col => 3, table => 0, text => " 1=DACB Stereosync " }, { col => 3, table => 0, text => " 2=DACA Pixclk " }, { col => 3, table => 0, text => " 3=DACB Pixclk " }, { col => 3, table => 0, text => " 4=DVOA CTL3 " }, { col => 3, table => 0, text => " 5=P1 PLLCLK " }, { col => 3, table => 0, text => " 6=P2 PLLCLK " }, { col => 3, table => 0, text => " 7=DVOA Stereosync " }, { col => 3, table => 0, text => " 8=DACA Field Number " }, { col => 3, table => 0, text => " 9=DACB Field Number " }, { col => 3, table => 0, text => " 10=GENERICA test debug clock from DCCG ", }, { col => 3, table => 0, text => " 11=SYNCEN " }, { col => 3, table => 0, text => " 12=GENERICA test debug clock from SCG ", }, { col => 3, table => 0, text => " 13=Reserved " }, { col => 3, table => 0, text => " 14=Reserved " }, { col => 3, table => 0, text => " 15=Reserved " }, { col => "heading", table => 1, text => "DC_GENERICB - RW - 32 bits - [GpuF0MMReg:0x7DC4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "GENERICB_EN" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable signals for GENERICB pad" }, { col => 0, table => 1, text => "GENERICB_SEL" }, { col => 1, table => 1, text => "11:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Select signal for GENERICB pad" }, { col => 3, table => 1, text => " 0=DACA Stereosync " }, { col => 3, table => 1, text => " 1=DACB Stereosync " }, { col => 3, table => 1, text => " 2=DACA PIXCLK " }, { col => 3, table => 1, text => " 3=DACB PIXCLK " }, { col => 3, table => 1, text => " 4=DVOA CTL3 " }, { col => 3, table => 1, text => " 5=P1 PLLCLK " }, { col => 3, table => 1, text => " 6=P2 PLLCLK " }, { col => 3, table => 1, text => " 7=DVOA Stereosync " }, { col => 3, table => 1, text => " 8=DACA Field Number " }, { col => 3, table => 1, text => " 9=DACB Field Number " }, { col => 3, table => 1, text => " 10=GENERICB test debug clock from DCCG ", }, { col => 3, table => 1, text => " 11=SYNCEN " }, { col => 3, table => 1, text => " 12=GENERICA test debug clock from SCG ", }, { col => 3, table => 1, text => " 13=Reserved " }, { col => 3, table => 1, text => " 14=Reserved " }, { col => 3, table => 1, text => " 15=Reserved " }, { col => "heading", table => 2, text => "DC_PAD_EXTERN_SIG - RW - 32 bits - [GpuF0MMReg:0x7DCC]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, ], }, { num => 327, text => [ { col => 0, table => 0, text => "DC_PAD_EXTERN_SIG_SEL" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Select pin PAD_EXTERN_SIGNAL is connected to", }, { col => 3, table => 0, text => " 0=PAD_EXTERN_SIGNAL is connected to HSYNCA pin ", }, { col => 3, table => 0, text => " 1=PAD_EXTERN_SIGNAL is connected to VSYNCA pin ", }, { col => 3, table => 0, text => " 2=PAD_EXTERN_SIGNAL is connected to HSYNCB pin ", }, { col => 3, table => 0, text => " 3=PAD_EXTERN_SIGNAL is connected to VSYNCB pin ", }, { col => 3, table => 0, text => " 4=PAD_EXTERN_SIGNAL is connected to GENERICA ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 5=PAD_EXTERN_SIGNAL is connected to GENERICB ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 6=PAD_EXTERN_SIGNAL is connected to GENERICC ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 7=PAD_EXTERN_SIGNAL is connected to HPD1 pin ", }, { col => 3, table => 0, text => " 8=PAD_EXTERN_SIGNAL is connected to HPD2 pin ", }, { col => 3, table => 0, text => " 9=PAD_EXTERN_SIGNAL is connected to DDC1CLK pin ", }, { col => 3, table => 0, text => " 10=PAD_EXTERN_SIGNAL is connected to DDC1DATA ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 11=PAD_EXTERN_SIGNAL is connected to DDC2CLK ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 12=PAD_EXTERN_SIGNAL is connected to DDC2DATA ", }, { col => 3, table => 0, text => "pin " }, { col => 3, table => 0, text => " 13=PAD_EXTERN_SIGNAL is connected to VHAD(1) pin ", }, { col => 3, table => 0, text => " 14=PAD_EXTERN_SIGNAL is connected to VHAD(0) pin ", }, { col => undef, table => undef, text => " 15=PAD_EXTERN_SIGNAL is connected to VPHCTL pin ", }, { col => undef, table => undef, text => "Select for PAD_EXTERN_SIGNAL" }, { col => "heading", table => 1, text => "DC_REF_CLK_CNTL - RW - 32 bits - [GpuF0MMReg:0x7DD4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "HSYNCA_OUTPUT_SEL" }, { col => 1, table => 1, text => "1:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Reference Clock Output disabled " }, { col => 3, table => 1, text => " 1=PPLL1 Reference Clock Output " }, { col => 3, table => 1, text => " 2=PPLL2 Reference Clock Output " }, { col => 3, table => 1, text => " 3=Reserved " }, { col => 0, table => 1, text => "HSYNCB_OUTPUT_SEL" }, { col => 1, table => 1, text => "9:8" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=Reference Clock Output disabled " }, { col => 3, table => 1, text => " 1=PPLL1 Reference Clock Output " }, { col => 3, table => 1, text => " 2=PPLL2 Reference Clock Output " }, { col => undef, table => undef, text => " 3=Reserved " }, { col => undef, table => undef, text => "Control output of external reference clocks", }, { col => undef, table => undef, text => "DISP_INTERRUPT_STATUS - RW - 32 bits - [GpuF0MMReg:0x7EDC]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "SCL_DISP1_MODE_CHANGE_INTERRU" }, { col => undef, table => undef, text => "PT (R)" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Interrupt that can be generated by the primary display ", }, { col => undef, table => undef, text => "controller's scaler when it detects any change in the scale ", }, { col => undef, table => undef, text => "ratio or number of taps the scaling filter is using. In ", }, { col => undef, table => undef, text => "automatic mode, the scale ratio can change whenever the ", }, { col => undef, table => undef, text => "source size (i.e. viewport) changes or the destination size ", }, { col => undef, table => undef, text => "(i.e. active display of the CRTC output timing).", }, ], }, { num => 328, text => [ { col => 0, table => 0, text => "SCL_DISP2_MODE_CHANGE_INTERRU" }, { col => 0, table => 0, text => "PT (R)" }, { col => 1, table => 0, text => 1 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the secondary display ", }, { col => 3, table => 0, text => "controller's scaler when it detects any change in the scale ", }, { col => 3, table => 0, text => "ratio or number of taps the scaling filter is using. In ", }, { col => 3, table => 0, text => "automatic mode, the scale ratio can change whenever the ", }, { col => 3, table => 0, text => "source size (i.e. viewport) changes or the destination size ", }, { col => 3, table => 0, text => "(i.e. active display of the CRTC output timing).", }, { col => 0, table => 0, text => "LB_D1_VLINE_INTERRUPT (R)" }, { col => 1, table => 0, text => 2 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the primary display ", }, { col => 3, table => 0, text => "controller's line buffer logic when the source image line ", }, { col => 3, table => 0, text => "counter falls within a programmed range of line numbers.", }, { col => 0, table => 0, text => "LB_D2_VLINE_INTERRUPT (R)" }, { col => 1, table => 0, text => 3 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the secondary display ", }, { col => 3, table => 0, text => "controller's line buffer logic when the source image line ", }, { col => 3, table => 0, text => "counter falls within a programmed range of line numbers.", }, { col => 0, table => 0, text => "LB_D1_VBLANK_INTERRUPT (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "primary display controller's line buffer logic either when the ", }, { col => 3, table => 0, text => "source image line counter is not requesting any active ", }, { col => 3, table => 0, text => "display data (i.e. in the vertical blank) or the output CRTC ", }, { col => 3, table => 0, text => "timing generator is within the vertical blanking region.", }, { col => 0, table => 0, text => "LB_D2_VBLANK_INTERRUPT (R)" }, { col => 1, table => 0, text => 5 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "secondary display controller's line buffer logic either when ", }, { col => 3, table => 0, text => "the source image line counter is not requesting any active ", }, { col => 3, table => 0, text => "display data (i.e. in the vertical blank) or the output CRTC ", }, { col => 3, table => 0, text => "timing generator is within the vertical blanking region.", }, { col => 0, table => 0, text => "CRTC1_SNAPSHOT_INTERRUPT (R)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "primary display controller's snapshot logic when either ", }, { col => 3, table => 0, text => "manually forced to trigger by writing a register, or by either a ", }, { col => 3, table => 0, text => "primary CRTC TRIG_A or TRIG_B event occurring.", }, { col => 0, table => 0, text => "CRTC1_FORCE_VSYNC_NEXT_LINE_I" }, { col => 0, table => 0, text => "NTERRUPT (R)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "primary display controller's force VSYNC next line logic ", }, { col => 3, table => 0, text => "when a force VSYNC next line event occurs, caused by ", }, { col => 3, table => 0, text => "either manually writing a register, or by either a primary ", }, { col => 3, table => 0, text => "CRTC TRIG_A or TRIG_B event occurring." }, { col => 0, table => 0, text => "CRTC1_FORCE_COUNT_NOW_INTERR" }, { col => 0, table => 0, text => "UPT (R)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "primary display controller's force count now logic when ", }, { col => 3, table => 0, text => "either a primary CRTC TRIG_A or TRIG_B event occur and ", }, { col => 3, table => 0, text => "the horizontal and/or vertical primary CRTC output timing ", }, { col => 3, table => 0, text => "counters reach the H_TOTAL and/or V_TOTAL position ", }, { col => 3, table => 0, text => "selected by the D1CRTC_FORCE_COUNT_NOW_MODE.", }, { col => 0, table => 0, text => "CRTC1_TRIGA_INTERRUPT (R)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the primary display ", }, { col => 3, table => 0, text => "controller when it detects a primary TRIGA event has ", }, { col => 3, table => 0, text => "occurred." }, { col => 0, table => 0, text => "CRTC1_TRIGB_INTERRUPT (R)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the primary display ", }, { col => 3, table => 0, text => "controller when it detects a primary TRIGB event has ", }, { col => 3, table => 0, text => "occurred." }, { col => 0, table => 0, text => "CRTC2_SNAPSHOT_INTERRUPT (R)" }, { col => 1, table => 0, text => 11 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "secondary display controller's snapshot logic when either ", }, { col => 3, table => 0, text => "manually forced to trigger by writing a register, or by either a ", }, { col => 3, table => 0, text => "CRTC TRIG_A or TRIG_B event from the secondary ", }, { col => 3, table => 0, text => "display controller occurring." }, { col => 0, table => 0, text => "CRTC2_FORCE_VSYNC_NEXT_LINE_I" }, { col => 0, table => 0, text => "NTERRUPT (R)" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "secondary display controller's force VSYNC next line logic ", }, { col => 3, table => 0, text => "when a force VSYNC next line event occurs, caused by ", }, { col => 3, table => 0, text => "either manually writing a register, or by either a secondary ", }, { col => 3, table => 0, text => "CRTC TRIG_A or TRIG_B event occurring." }, { col => 0, table => 0, text => "CRTC2_FORCE_COUNT_NOW_INTERR" }, { col => 0, table => 0, text => "UPT (R)" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated by the ", }, { col => 3, table => 0, text => "secondary display controller's force count now logic when ", }, { col => 3, table => 0, text => "either a primary CRTC TRIG_A or TRIG_B event occur and ", }, { col => 3, table => 0, text => "the horizontal and/or vertical secondary CRTC output timing ", }, { col => 3, table => 0, text => "counters reach the H_TOTAL and/or V_TOTAL position ", }, { col => 3, table => 0, text => "selected by the D2CRTC_FORCE_COUNT_NOW_MODE.", }, { col => 0, table => 0, text => "CRTC2_TRIGA_INTERRUPT (R)" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the secondary display ", }, { col => 3, table => 0, text => "controller when it detects a secondary TRIGA event has ", }, { col => 3, table => 0, text => "occurred." }, ], }, { num => 329, text => [ { col => 0, table => 0, text => "CRTC2_TRIGB_INTERRUPT (R)" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated by the secondary display ", }, { col => 3, table => 0, text => "controller when it detects a secondary TRIGB event has ", }, { col => 3, table => 0, text => "occurred." }, { col => 0, table => 0, text => "DACA_AUTODETECT_INTERRUPT (R)" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated when the ", }, { col => 3, table => 0, text => "Autodetect device connected to DACA output detects either ", }, { col => 3, table => 0, text => "a display being first connected or, once connected, first ", }, { col => 3, table => 0, text => "detects the display being disconnected." }, { col => 0, table => 0, text => "DACB_AUTODETECT_INTERRUPT (R)" }, { col => 1, table => 0, text => 17 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated when the ", }, { col => 3, table => 0, text => "Autodetect device connected to DACA output detects either ", }, { col => 3, table => 0, text => "a display being first connected or, once connected, first ", }, { col => 3, table => 0, text => "detects the display being disconnected." }, { col => 0, table => 0, text => "DC_HOT_PLUG_DETECT1_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 18 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated when a ", }, { col => 3, table => 0, text => "Flat Panel (supporting the hot plug feature) is detected to ", }, { col => 3, table => 0, text => "be first connected to the HPD1 pin or, once connected, is ", }, { col => 3, table => 0, text => "detected to have disconnected from the HPD1 pin.", }, { col => 0, table => 0, text => "DC_HOT_PLUG_DETECT2_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 19 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be programmed to be generated when a ", }, { col => 3, table => 0, text => "Flat Panel (supporting the hot plug feature) is detected to ", }, { col => 3, table => 0, text => "be first connected to the HPD2 pin or, once connected, is ", }, { col => 3, table => 0, text => "detected to have disconnected from the HPD2 pin.", }, { col => 0, table => 0, text => "DC_I2C_SW_DONE_INTERRUPT (R)" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated when the current I2C read ", }, { col => 3, table => 0, text => "or write operation done by the DISPOUT hardware assisted ", }, { col => 3, table => 0, text => "I2C finished execution." }, { col => 0, table => 0, text => "DC_I2C_HW_DONE_INTERRUPT (R)" }, { col => 1, table => 0, text => 21 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated when the current I2C read ", }, { col => 3, table => 0, text => "or write operation done by the DISPOUT hardware assisted ", }, { col => 3, table => 0, text => "I2C finishes execution." }, { col => 0, table => 0, text => "DISP_TIMER_INTERRUPT (R)" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated when the display Timer ", }, { col => 3, table => 0, text => "Control logic has generated a hardware interrupt.", }, { col => 0, table => 0, text => "DACA_CAPTURE_START_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated each time a start of frame ", }, { col => 3, table => 0, text => "pulse arrives at the DACA output." }, { col => 0, table => 0, text => "DACB_CAPTURE_START_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated each time a start of frame ", }, { col => 3, table => 0, text => "pulse arrives at the DACB output." }, { col => 0, table => 0, text => "TMDSA_CAPTURE_START_INTERRUP" }, { col => 0, table => 0, text => "T (R)" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated each time a start of frame ", }, { col => 3, table => 0, text => "pulse arrives at the integrated TMDS transmitter output.", }, { col => 0, table => 0, text => "TMDS2A_CAPTURE_START_INTERRU" }, { col => 0, table => 0, text => "PT (R)" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated each time a start of frame ", }, { col => 3, table => 0, text => "pulse arrives at the integrated TMDS2 transmitter output.", }, { col => 0, table => 0, text => "DVOA_CAPTURE_START_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Interrupt that can be generated each time a start of frame ", }, { col => 3, table => 0, text => "pulse arrives at the DVOA port." }, { col => 0, table => 0, text => "DISP_INTERRUPT_STATUS_CONTINU" }, { col => 0, table => 0, text => "E (R)" }, { col => 1, table => 0, text => 31 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "when this bit is set, continue reading " }, { col => undef, table => undef, text => "DISP_INTERRUPT_STATUS_CONTINUE" }, { col => undef, table => undef, text => "Status of all display block interrupts", }, { col => undef, table => undef, text => "DISP_INTERRUPT_STATUS_CONTINUE - RW - 32 bits - [GpuF0MMReg:0x7EE8]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "D1MODE_DATA_UNDERFLOW_INTERR" }, { col => undef, table => undef, text => "UPT (R)" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 1 Line Buffer data underflow", }, { col => undef, table => undef, text => "D1MODE_REQUEST_UNDERFLOW_IN" }, { col => undef, table => undef, text => "TERRUPT (R)" }, { col => undef, table => undef, text => 17 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 1 Line Buffer request underflow", }, { col => undef, table => undef, text => "D1SCL_DATA_UNDERFLOW_INTERRU" }, { col => undef, table => undef, text => "PT (R)" }, { col => undef, table => undef, text => 18 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 1 Scaler data underflow", }, { col => undef, table => undef, text => "D1SCL_HOST_CONFLICT_INTERRUPT " }, { col => undef, table => undef, text => "(R)" }, { col => undef, table => undef, text => 19 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 1 Scaler host conflict", }, { col => undef, table => undef, text => "D2MODE_DATA_UNDERFLOW_INTERR" }, { col => undef, table => undef, text => "UPT (R)" }, { col => undef, table => undef, text => 20 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 2 Line Buffer data underflow", }, { col => undef, table => undef, text => "D2MODE_REQUEST_UNDERFLOW_IN" }, { col => undef, table => undef, text => "TERRUPT (R)" }, { col => undef, table => undef, text => 21 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 2 Line Buffer request underflow", }, { col => undef, table => undef, text => "D2SCL_DATA_UNDERFLOW_INTERRU" }, { col => undef, table => undef, text => "PT (R)" }, { col => undef, table => undef, text => 22 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Debug interrupt for Display 2 Scaler data underflow", }, ], }, { num => 330, text => [ { col => 0, table => 0, text => "D2SCL_HOST_CONFLICT_INTERRUPT " }, { col => 0, table => 0, text => "(R)" }, { col => 1, table => 0, text => 23 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug interrupt for Display 2 Scaler host conflict", }, { col => 0, table => 0, text => "MVP_FIFO_ERROR_INTERRUPT (R)" }, { col => 1, table => 0, text => 24 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug interrupt for multi-vpu fifo error (underflow or ", }, { col => 3, table => 0, text => "overflow)" }, { col => 0, table => 0, text => "HDMI0_ERROR_INTERRUPT (R)" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug interrupt for HDMI0 error (audio fifo overflow, acr tx ", }, { col => 3, table => 0, text => "overflow, audio packet error or vbi packet error)", }, { col => 0, table => 0, text => "HDMI1_ERROR_INTERRUPT (R)" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Debug interrupt for HDMI1 error (audio fifo overflow, acr tx ", }, { col => undef, table => undef, text => "overflow, audio packet error or vbi packet error)", }, { col => undef, table => undef, text => "Status of all display block interrupts", }, { col => "heading", table => 1, text => "DOUT_POWER_MANAGEMENT_CNTL - RW - 32 bits - [GpuF0MMReg:0x7EE0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "PWRDN_WAIT_BUSY_OFF" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Control whether power management waits for signal ", }, { col => 3, table => 1, text => "indicating all block busy signals =0 from DCCG during ", }, { col => 3, table => 1, text => "powerdown" }, { col => 3, table => 1, text => " 0=When in WAIT_BUSY_OFF, don't wait for all busy=0 ", }, { col => 3, table => 1, text => " 1=When in WAIT_BUSY_OFF, wait for all busy=0 ", }, { col => 0, table => 1, text => "PWRDN_WAIT_PWRSEQ_OFF" }, { col => 1, table => 1, text => 4 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Control whether power management waits for signal ", }, { col => 3, table => 1, text => "indicating power sequencer is off during powerdown", }, { col => 3, table => 1, text => " 0=When in WAIT_BUSY_OFF, don't wait for pwrseq off ", }, { col => 3, table => 1, text => " 1=When in WAIT_BUSY_OFF, wait pwrseq off ", }, { col => 0, table => 1, text => "PWRDN_WAIT_PPLL_OFF" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Control whether power management waits for DCCG to ", }, { col => 3, table => 1, text => "report pixel PLLs are off during powerdown", }, { col => 3, table => 1, text => " 0=When in WAIT_PPLL_OFF, proceed to next state ", }, { col => 3, table => 1, text => " 1=When in WAIT_PPLL_OFF, wait for pixel pll off ", }, { col => 3, table => 1, text => "indicator " }, { col => 0, table => 1, text => "PWRUP_WAIT_PPLL_ON" }, { col => 1, table => 1, text => 12 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Control whether power management waits for 1 ms to allow ", }, { col => 3, table => 1, text => "pixel PLLs to lock during powerup" }, { col => 3, table => 1, text => " 0=When in WAIT_PPLL_ON, proceed to next state ", }, { col => 3, table => 1, text => " 1=When in WAIT_PPLL_ON, wait for 1 ms proceeding to ", }, { col => 3, table => 1, text => "next state " }, { col => 0, table => 1, text => "PWRUP_WAIT_MEM_INIT_DONE" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Control whether power management mem_init_done ", }, { col => 3, table => 1, text => "indicator" }, { col => 3, table => 1, text => " 0=When in WAIT_MEM_INIT_DONE, proceed to next ", }, { col => 3, table => 1, text => "state " }, { col => 3, table => 1, text => " 1=When in WAIT_MEM_INIT_DONE, wait for ", }, { col => 3, table => 1, text => "mem_init_done indicator " }, { col => 0, table => 1, text => "PM_ASSERT_RESET" }, { col => 1, table => 1, text => 20 }, { col => 2, table => 1, text => "0x1" }, { col => 3, table => 1, text => "Control whether power management asserts ", }, { col => 3, table => 1, text => "DOUT_CRTC_pwr_down_reset on powerdown" }, { col => 3, table => 1, text => " 0=Don't assert pm_reset when in 'OFF' state ", }, { col => 3, table => 1, text => " 1=Assert pm_reset when in 'OFF' state ", }, { col => 0, table => 1, text => "PM_PWRDN_PPLL" }, { col => 1, table => 1, text => 24 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Control whether power management asserts pixel PLL ", }, { col => 3, table => 1, text => "reset on powerdown" }, { col => 3, table => 1, text => " 0=Don't reset pixel PLLs when in 'OFF' state ", }, { col => 3, table => 1, text => " 1=Reset pixel PLLs when in 'OFF' state ", }, { col => 0, table => 1, text => "PM_CURRENT_STATE (R)" }, { col => 1, table => 1, text => "30:28" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Current power management state" }, { col => 3, table => 1, text => " 0=PM_OFF " }, { col => 3, table => 1, text => " 1=PM_WAIT_PPLL_ON " }, { col => 3, table => 1, text => " 2=PM_WAIT_MEM_INIT_DONE " }, { col => 3, table => 1, text => " 3=PM_ON " }, { col => 3, table => 1, text => " 4=PM_WAIT_BUSY_OFF " }, { col => 3, table => 1, text => " 5=PM_WAIT_PPLL_OFF " }, { col => 3, table => 1, text => " 6=Reserved " }, { col => 3, table => 1, text => " 7=Reserved " }, ], }, { num => 331, text => [ { col => "heading", table => 0, text => "DISP_TIMER_CONTROL - RW - 32 bits - [GpuF0MMReg:0x7EF0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DISP_TIMER_INT_COUNT" }, { col => 1, table => 0, text => "24:0" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Desired value for Display Timer Counter to count to before ", }, { col => 3, table => 0, text => "generating event that can cause a hardware interrupt to ", }, { col => 3, table => 0, text => "occur. The counter value is decremented each clock pulse ", }, { col => 3, table => 0, text => "of the CG_xtal_ref_sclk signal. CG_xtal_ref_sclk = a one ", }, { col => 3, table => 0, text => "clock wide pulse on core clock (SCLK) that occurs (Crystal ", }, { col => 3, table => 0, text => "Oscillator Frequency (i.e. 27 MHz)) / (CG_RT_CNTL2_DIV) ", }, { col => 3, table => 0, text => "times per second." }, { col => 0, table => 0, text => "DISP_TIMER_INT_ENABLE (W)" }, { col => 1, table => 0, text => 25 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Start timer interrupt if TIMER_INT_CNT > 0. ", }, { col => 0, table => 0, text => "DISP_TIMER_INT_RUNNING (R)" }, { col => 1, table => 0, text => 26 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Timer interrupt counter not running ", }, { col => 3, table => 0, text => " 1=Timer interrupt counter running " }, { col => 0, table => 0, text => "DISP_TIMER_INT_MSK" }, { col => 1, table => 0, text => 27 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Display Countdown Timer cannot generate hardware ", }, { col => 3, table => 0, text => "interrupt. " }, { col => 3, table => 0, text => " 1=Display Countdown Timer can generate hardware ", }, { col => 3, table => 0, text => "interrupt when count reached. " }, { col => 0, table => 0, text => "DISP_TIMER_INT_STAT (R)" }, { col => 1, table => 0, text => 28 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Status of the Display Timer Counter logic. When this bit is ", }, { col => 3, table => 0, text => "high, it does not indicate that a hardware interrupt has ", }, { col => 3, table => 0, text => "occurred." }, { col => 0, table => 0, text => "DISP_TIMER_INT_STAT_AK (W)" }, { col => 1, table => 0, text => 29 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Write 1 to acknowledge and clear interrupt", }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Interrupt Acknowledged and will be cleared. ", }, { col => 0, table => 0, text => "DISP_TIMER_INT (R)" }, { col => 1, table => 0, text => 30 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "When this bit is high, it indicates that the Display Timer ", }, { col => 3, table => 0, text => "Control logic has generated a hardware interrupt. This bit ", }, { col => 3, table => 0, text => "equals the display timer status (DISP_TIMER_INT_STAT) ", }, { col => 3, table => 0, text => "logically 'AND'ed with the display timer interrupt mask ", }, { col => undef, table => undef, text => "(DISP_TIMER_INT_MSK)." }, { col => undef, table => undef, text => "Display Countdown Timer capable of generating a hardware interrupt", }, { col => "heading", table => 1, text => "CAPTURE_START_STATUS - RW - 32 bits - [GpuF0MMReg:0x7ED0]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DACA_CAPTURE_START (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Extended DACA Capture Start that is used for test & debug ", }, { col => 3, table => 1, text => "purposes. This Capture Start is de-asserted by ", }, { col => 3, table => 1, text => "DACA_CAPTURE_START_AK." }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Capture_start has occurred " }, { col => 0, table => 1, text => "DACB_CAPTURE_START (R)" }, { col => 1, table => 1, text => 1 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Extended DACB Capture Start that is used for test & debug ", }, { col => 3, table => 1, text => "purposes. This Capture Start is de-asserted by ", }, { col => 3, table => 1, text => "DACB_CAPTURE_START_AK." }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Capture_start has occurred " }, { col => 0, table => 1, text => "TMDSA_CAPTURE_START (R)" }, { col => 1, table => 1, text => 2 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Extended TMDSA Capture Start that is used for test & ", }, { col => 3, table => 1, text => "debug purposes. This Capture Start is de-asserted by ", }, { col => 3, table => 1, text => "TMDSA_CAPTURE_START_AK." }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Capture_start has occurred " }, { col => 0, table => 1, text => "TMDS2A_CAPTURE_START (R)" }, { col => 1, table => 1, text => 3 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => " 0=No event " }, { col => 3, table => 1, text => " 1=Capture_start has occurred " }, ], }, { num => 332, text => [ { col => 0, table => 0, text => "DVOA_CAPTURE_START (R)" }, { col => 1, table => 0, text => 4 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Extended DVOA Capture Start that is used for test & debug ", }, { col => 3, table => 0, text => "purposes. This Capture Start is de-asserted by ", }, { col => 3, table => 0, text => "DVOA_CAPTURE_START_AK." }, { col => 3, table => 0, text => " 0=No event " }, { col => 3, table => 0, text => " 1=Capture_start has occurred " }, { col => 0, table => 0, text => "DACA_CAPTURE_START_AK (W)" }, { col => 1, table => 0, text => 6 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Acknowledge bit for DACA Capture Start. This bit will clear ", }, { col => 3, table => 0, text => "DACA_CAPTURE_START and " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DACA_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear Capture_start " }, { col => 0, table => 0, text => "DACB_CAPTURE_START_AK (W)" }, { col => 1, table => 0, text => 7 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Acknowledge bit for DACB Capture Start. This bit will clear ", }, { col => 3, table => 0, text => "DACB_CAPTURE_START and " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DACB_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear Capture_start " }, { col => 0, table => 0, text => "TMDSA_CAPTURE_START_AK (W)" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Acknowledge bit for TMDSA Capture Start. This bit will ", }, { col => 3, table => 0, text => "clear TMDSA_CAPTURE_START and " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.TMDSA_CAPTURE_STA", }, { col => 3, table => 0, text => "RT_INTERRUPT." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear Capture_start " }, { col => 0, table => 0, text => "TMDS2A_CAPTURE_START_AK (W)" }, { col => 1, table => 0, text => 9 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear Capture_start " }, { col => 0, table => 0, text => "DVOA_CAPTURE_START_AK (W)" }, { col => 1, table => 0, text => 10 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Acknowledge bit for DVOA Capture Start. This bit will clear ", }, { col => 3, table => 0, text => "DVOA_CAPTURE_START and " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DVOA_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=No effect " }, { col => 3, table => 0, text => " 1=Clear Capture_start " }, { col => 0, table => 0, text => "DACA_CAPTURE_START_INT_EN" }, { col => 1, table => 0, text => 12 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable interrupts on DACA Capture Start. Interrupt can be ", }, { col => 3, table => 0, text => "monitored by polling " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DACA_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DACB_CAPTURE_START_INT_EN" }, { col => 1, table => 0, text => 13 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable interrupts on DACB Capture Start. Interrupt can be ", }, { col => 3, table => 0, text => "monitored by polling " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DACB_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDSA_CAPTURE_START_INT_EN" }, { col => 1, table => 0, text => 14 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable interrupts on TMDSA Capture Start. Interrupt can ", }, { col => 3, table => 0, text => "be monitored by polling " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.TMDSA_CAPTURE_STA", }, { col => 3, table => 0, text => "RT_INTERRUPT." }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "TMDS2A_CAPTURE_START_INT_EN" }, { col => 1, table => 0, text => 15 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DVOA_CAPTURE_START_INT_EN" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable interrupts on DVOA Capture Start. Interrupt can be ", }, { col => 3, table => 0, text => "monitored by polling " }, { col => 3, table => 0, text => "DISP_INTERRUPT_STATUS_x.DVOA_CAPTURE_STAR", }, { col => 3, table => 0, text => "T_INTERRUPT." }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Capture Start Control" }, ], }, { num => 333, text => [ { col => undef, table => undef, text => " General Purpose I/O Registers" }, { col => "heading", table => 0, text => "DC_GPIO_GENERIC_MASK - RW - 32 bits - [GpuF0MMReg:0x7DE0]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_GENERICA_MASK" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 0, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 0, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 0, text => "overridden. " }, { col => 0, table => 0, text => "DC_GPIO_GENERICB_MASK" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 0, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 0, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 0, text => "overridden. " }, { col => 0, table => 0, text => "DC_GPIO_GENERICC_MASK" }, { col => 1, table => 0, text => 16 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 0, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 0, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "Control GPIO functionality of GENERIC pads - active high.", }, { col => "heading", table => 1, text => "DC_GPIO_GENERIC_A - RW - 32 bits - [GpuF0MMReg:0x7DE4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_GENERICA_A" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for GENERICA pad when ", }, { col => 3, table => 1, text => "DC_GPIO_GENERICA_MASK = 1." }, { col => 0, table => 1, text => "DC_GPIO_GENERICB_A" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for GENERICB pad when ", }, { col => 3, table => 1, text => "DC_GPIO_GENERICB_MASK = 1." }, { col => 0, table => 1, text => "DC_GPIO_GENERICC_A" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for GENERICC pad when ", }, { col => undef, table => undef, text => "DC_GPIO_GENERICC_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for GENERIC pads when GPIO functionality enabled by DC_GPIO_GENERIC_MASK register.", }, { col => "heading", table => 2, text => "DC_GPIO_GENERIC_EN - RW - 32 bits - [GpuF0MMReg:0x7DE8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_GENERICA_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable used for GENERICA when " }, { col => 3, table => 2, text => "DC_GPIO_GENERICA_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_GENERICB_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable used for GENERICB when " }, { col => 3, table => 2, text => "DC_GPIO_GENERICB_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_GENERICC_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable used for GENERICC when " }, { col => undef, table => undef, text => "DC_GPIO_GENERICC_MASK = 1." }, { col => undef, table => undef, text => "Ouput enable for GENERIC pads when GPIO functionality enabled by DC_GPIO_GENERIC_MASK register.", }, { col => "heading", table => 3, text => "DC_GPIO_GENERIC_Y - RW - 32 bits - [GpuF0MMReg:0x7DEC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_GENERICA_Y (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on GENERICA pad." }, { col => 0, table => 3, text => "DC_GPIO_GENERICB_Y (R)" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on GENERICB pad." }, { col => 0, table => 3, text => "DC_GPIO_GENERICC_Y (R)" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on GENERICC pad." }, ], }, { num => 334, text => [ { col => undef, table => undef, text => "Output values of GENERIC pads." }, { col => "heading", table => 0, text => "DC_GPIO_DDC4_MASK - RW - 32 bits - [GpuF0MMReg:0x7E00]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_DDC4CLK_MASK" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable/Disable GPIO functionality on DDC4CLK pad", }, { col => 3, table => 0, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 0, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 0, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 0, text => "overridden. " }, { col => 0, table => 0, text => "DC_GPIO_DDC4DATA_MASK" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Enable/Disable GPIO functionality on DDC4DATA pad", }, { col => 3, table => 0, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 0, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 0, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "Control GPIO functionality of the DDC4 pads - all fields are active high.", }, { col => "heading", table => 1, text => "DC_GPIO_DDC4_A - RW - 32 bits - [GpuF0MMReg:0x7E04]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DDC4CLK_A" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for DDC4CLK when " }, { col => 3, table => 1, text => "DC_GPIO_DDC4CLK_MASK = 1." }, { col => 0, table => 1, text => "DC_GPIO_DDC4DATA_A" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for DDC4DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC4DATA_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the DDC4 pads when the GPIO functionality is enabled by the DC_GPIO_DDC4_MASK register.", }, { col => "heading", table => 2, text => "DC_GPIO_DDC4_EN - RW - 32 bits - [GpuF0MMReg:0x7E08]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_DDC4CLK_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable for DDC4CLK when " }, { col => 3, table => 2, text => "DC_GPIO_DDC4CLK_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_DDC4DATA_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable for DDC4DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC4DATA_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the DDC4 pads when the GPIO functionality is enabled by the DC_GPIO_DDC4_MASK register.", }, { col => "heading", table => 3, text => "DC_GPIO_DDC4_Y - RW - 32 bits - [GpuF0MMReg:0x7E0C]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_DDC4CLK_Y (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on DDC4CLK pad." }, { col => 0, table => 3, text => "DC_GPIO_DDC4DATA_Y (R)" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Value on DDC4DATA pad." }, { col => undef, table => undef, text => "Output values for the DDC4 pads.", }, { col => undef, table => undef, text => "DC_GPIO_DEBUG - RW - 32 bits - [GpuF0MMReg:0x7E2C]", }, ], }, { num => 335, text => [ { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_VIPGPIO_DEBUG" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "0. Normal Mode" }, { col => 3, table => 0, text => "1. CG/BIF Debug on GPIO[34:18]" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=CG/BIF Debug on GPIO[34:18] " }, { col => 0, table => 0, text => "DC_GPIO_MACRO_DEBUG" }, { col => 1, table => 0, text => "9:8" }, { col => 2, table => 0, text => "0x1" }, { col => 3, table => 0, text => "0. Normal Mode" }, { col => 3, table => 0, text => "1. Mux Chip/BIF debug bus on DVODATA[23:0] and ", }, { col => 3, table => 0, text => "DVOCNTL[0]" }, { col => 3, table => 0, text => "2.Mux TMDS on DVODATA[15:6]" }, { col => 3, table => 0, text => "3. Mux TMDS2 on DVODATA[15:6]" }, { col => 3, table => 0, text => " 0=Normal " }, { col => 3, table => 0, text => " 1=Chip/BIF Debug on dvo[23:0] and dvoctrl[0] ", }, { col => 3, table => 0, text => " 2=TMDSA debug output on dvo[15:6] " }, { col => undef, table => undef, text => " 3=TMDS2A debug output on dvo[15:6] ", }, { col => undef, table => undef, text => "Mux control to allow VIP and DCO Debug to share DVO Pads.", }, { col => "heading", table => 1, text => "DC_GPIO_DVODATA_MASK - RW - 32 bits - [GpuF0MMReg:0x7E30]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DVODATA_MASK" }, { col => 1, table => 1, text => "23:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable/Disable GPIO functionality on DVODATA pads. Bits ", }, { col => 3, table => 1, text => "can be set individually." }, { col => 0, table => 1, text => "DC_GPIO_DVOCNTL_MASK" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable/Disable GPIO functionality on DVOCNTL pads. Bits ", }, { col => 3, table => 1, text => "can be set individually." }, { col => 0, table => 1, text => "DC_GPIO_DVOCLK_MASK" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable/Disable GPIO functionality on DVOCLK pads. Bits ", }, { col => 3, table => 1, text => "can be set individually." }, { col => 0, table => 1, text => "DC_GPIO_MVP_DVOCNTL_MASK" }, { col => 1, table => 1, text => "31:30" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Enable/Disable GPIO functionality on DVO_MVP_CNTL ", }, { col => undef, table => undef, text => "pads. Bits can be set individually.", }, { col => undef, table => undef, text => "Control GPIO functionality of the DVO pads - all fields are active high.", }, { col => "heading", table => 2, text => "DC_GPIO_DVODATA_A - RW - 32 bits - [GpuF0MMReg:0x7E34]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_DVODATA_A" }, { col => 1, table => 2, text => "23:0" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Asynchronous inputs for DVODATA pads when associated ", }, { col => 3, table => 2, text => "DC_GPIO_DVODATA_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_DVOCNTL_A" }, { col => 1, table => 2, text => "26:24" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Asynchronous inputs for DVOCNTL pads when associated ", }, { col => 3, table => 2, text => "DC_GPIO_DVOCNTL_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_DVOCLK_A" }, { col => 1, table => 2, text => 28 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Asynchronous inputs for DVOCLK pads when associated ", }, { col => 3, table => 2, text => "DC_GPIO_DVOCLK_MASK = 1." }, { col => 0, table => 2, text => "DC_GPIO_MVP_DVOCNTL_A" }, { col => 1, table => 2, text => "31:30" }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Asynchronous inputs for DVO_MVP_CNTL pads when ", }, { col => undef, table => undef, text => "associated DC_GPIO_MVP_DVOCNTL_MASK = 1.", }, { col => undef, table => undef, text => "Asynchronous inputs for the DVO pads when the GPIO functionality is enabled by the DC_GPIO_DVODATA_MASK register.", }, { col => "heading", table => 3, text => "DC_GPIO_DVODATA_EN - RW - 32 bits - [GpuF0MMReg:0x7E38]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_DVODATA_EN" }, { col => 1, table => 3, text => "23:0" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Output enables for DVODATA pads when associated ", }, { col => 3, table => 3, text => "DC_GPIO_DVODATA_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_DVOCNTL_EN" }, { col => 1, table => 3, text => "26:24" }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Output enables for DVOCNTL pads when associated ", }, { col => 3, table => 3, text => "DC_GPIO_DVOCNTL_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_DVOCLK_EN" }, { col => 1, table => 3, text => 28 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Output enables for DVOCLK pads when associated ", }, { col => 3, table => 3, text => "DC_GPIO_DVOCLK_MASK = 1." }, ], }, { num => 336, text => [ { col => 0, table => 0, text => "DC_GPIO_MVP_DVOCNTL_EN" }, { col => 1, table => 0, text => "31:30" }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enables for DVO_MVP_CNTL pads when ", }, { col => undef, table => undef, text => "associated DC_GPIO_MVP_DVOCNTL_MASK = 1.", }, { col => undef, table => undef, text => "Output enable values for the DVO pads when the GPIO functionality is enabled by the DC_GPIO_DVODATA_MASK register.", }, { col => "heading", table => 1, text => "DC_GPIO_DVODATA_Y - RW - 32 bits - [GpuF0MMReg:0x7E3C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DVODATA_Y (R)" }, { col => 1, table => 1, text => "23:0" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Values on DVODATA pads." }, { col => 0, table => 1, text => "DC_GPIO_DVOCNTL_Y (R)" }, { col => 1, table => 1, text => "26:24" }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Values on DVOCNTL pads." }, { col => 0, table => 1, text => "DC_GPIO_DVOCLK_Y (R)" }, { col => 1, table => 1, text => 28 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Values on DVOCLK pads." }, { col => 0, table => 1, text => "DC_GPIO_MVP_DVOCNTL_Y (R)" }, { col => 1, table => 1, text => "31:30" }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Values on DVO_MVP_CNTL pads." }, { col => undef, table => undef, text => "Output values of the DVO pads." }, { col => "heading", table => 2, text => "DC_GPIO_DDC1_MASK - RW - 32 bits - [GpuF0MMReg:0x7E40]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_DDC1CLK_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC1CLK pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC1CLK_PD_EN" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on DDC1CLK pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_DDC1CLK_PU_EN" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on DDC1CLK pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_DDC1DATA_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC1DATA pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC1DATA_PD_EN" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on DDC1DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_DDC1DATA_PU_EN" }, { col => 1, table => 2, text => 14 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on DDC1DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Control GPIO functionality of the DDC1 pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_DDC1_A - RW - 32 bits - [GpuF0MMReg:0x7E44]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_DDC1CLK_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC1CLK when " }, { col => 3, table => 3, text => "DC_GPIO_DDC1CLK_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_DDC1DATA_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC1DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC1DATA_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the DDC1 pads when the GPIO functionality is enabled by the DC_GPIO_DDC1_MASK register.", }, ], }, { num => 337, text => [ { col => "heading", table => 0, text => "DC_GPIO_DDC1_EN - RW - 32 bits - [GpuF0MMReg:0x7E48]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_DDC1CLK_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC1CLK when " }, { col => 3, table => 0, text => "DC_GPIO_DDC1CLK_MASK = 1." }, { col => 0, table => 0, text => "DC_GPIO_DDC1DATA_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC1DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC1DATA_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the DDC1 pads when the GPIO functionality is enabled by the DC_GPIO_DDC1_MASK register.", }, { col => "heading", table => 1, text => "DC_GPIO_DDC1_Y - RW - 32 bits - [GpuF0MMReg:0x7E4C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DDC1CLK_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on DDC1CLK pad." }, { col => 0, table => 1, text => "DC_GPIO_DDC1DATA_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Value on DDC1DATA pad." }, { col => undef, table => undef, text => "Output values of the DDC1 pads." }, { col => "heading", table => 2, text => "DC_GPIO_DDC2_MASK - RW - 32 bits - [GpuF0MMReg:0x7E50]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_DDC2CLK_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC2CLK pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC2DATA_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC2DATA pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC2DATA_PD_EN" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on DDC2DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_DDC2DATA_PU_EN" }, { col => 1, table => 2, text => 14 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on DDC2DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Control GPIO functionality of the DDC2 pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_DDC2_A - RW - 32 bits - [GpuF0MMReg:0x7E54]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_DDC2CLK_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC2CLK when " }, { col => 3, table => 3, text => "DC_GPIO_DDC2CLK_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_DDC2DATA_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC2DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC2DATA_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the DDC2 pads when the GPIO functionality is enabled by the DC_GPIO_DDC2_MASK register.", }, ], }, { num => 338, text => [ { col => "heading", table => 0, text => "DC_GPIO_DDC2_EN - RW - 32 bits - [GpuF0MMReg:0x7E58]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_DDC2CLK_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC2CLK when " }, { col => 3, table => 0, text => "DC_GPIO_DDC2CLK_MASK = 1." }, { col => 0, table => 0, text => "DC_GPIO_DDC2DATA_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC2DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC2DATA_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the DDC2 pads when the GPIO functionality is enabled by the DC_GPIO_DDC2_MASK register.", }, { col => "heading", table => 1, text => "DC_GPIO_DDC2_Y - RW - 32 bits - [GpuF0MMReg:0x7E5C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DDC2CLK_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on DDC2CLK pad." }, { col => 0, table => 1, text => "DC_GPIO_DDC2DATA_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Value on DDC2DATA pad." }, { col => undef, table => undef, text => "Output values of the DDC2 pads." }, { col => "heading", table => 2, text => "DC_GPIO_DDC3_MASK - RW - 32 bits - [GpuF0MMReg:0x7E60]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_DDC3CLK_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC3CLK pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC3DATA_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on DDC3DATA pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_DDC3DATA_PD_EN" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on DDC3DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_DDC3DATA_PU_EN" }, { col => 1, table => 2, text => 14 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on DDC3DATA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Control GPIO functionality of the DDC3 pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_DDC3_A - RW - 32 bits - [GpuF0MMReg:0x7E64]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_DDC3CLK_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC3CLK when " }, { col => 3, table => 3, text => "DC_GPIO_DDC3CLK_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_DDC3DATA_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for DDC3DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC3DATA_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the DDC3 pads when the GPIO functionality is enabled by the DC_GPIO_DDC3_MASK register.", }, ], }, { num => 339, text => [ { col => "heading", table => 0, text => "DC_GPIO_DDC3_EN - RW - 32 bits - [GpuF0MMReg:0x7E68]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_DDC3CLK_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC3CLK when " }, { col => 3, table => 0, text => "DC_GPIO_DDC3CLK_MASK = 1." }, { col => 0, table => 0, text => "DC_GPIO_DDC3DATA_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for DDC3DATA when " }, { col => undef, table => undef, text => "DC_GPIO_DDC3DATA_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the DDC3 pads when the GPIO functionality is enabled by the DC_GPIO_DDC3_MASK register.", }, { col => "heading", table => 1, text => "DC_GPIO_DDC3_Y - RW - 32 bits - [GpuF0MMReg:0x7E6C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_DDC3CLK_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on DDC3CLK pad." }, { col => 0, table => 1, text => "DC_GPIO_DDC3DATA_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Value on DDC3DATA pad." }, { col => undef, table => undef, text => "Output values for the DDC3 pads.", }, { col => "heading", table => 2, text => "DC_GPIO_SYNCA_MASK - RW - 32 bits - [GpuF0MMReg:0x7E70]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_HSYNCA_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on HSYNCA pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_HSYNCA_PD_EN" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on HSYNCA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_HSYNCA_PU_EN" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on HSYNCA pad" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_VSYNCA_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on VSYNCA pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_VSYNCA_PD_EN" }, { col => 1, table => 2, text => 12 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on VSYNCA pad", }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_VSYNCA_PU_EN" }, { col => 1, table => 2, text => 14 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on VSYNCA pad" }, { col => 3, table => 2, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Control GPIO functionality of the HSYNCA & VSYNCA pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_SYNCA_A - RW - 32 bits - [GpuF0MMReg:0x7E74]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_HSYNCA_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for HSYNCA when " }, { col => 3, table => 3, text => "DC_GPIO_HSYNCA_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_VSYNCA_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for VSYNCA when " }, { col => 3, table => 3, text => "DC_GPIO_VSYNCA_MASK = 1." }, ], }, { num => 340, text => [ { col => undef, table => undef, text => "Asynchronous inputs for the HSYNCA & VSYNCA pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_SYNCA_MASK register." }, { col => "heading", table => 0, text => "DC_GPIO_SYNCA_EN - RW - 32 bits - [GpuF0MMReg:0x7E78]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_HSYNCA_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for HSYNCA when " }, { col => 3, table => 0, text => "DC_GPIO_HSYNCA_MASK = 1." }, { col => 0, table => 0, text => "DC_GPIO_VSYNCA_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for VSYNCA when " }, { col => undef, table => undef, text => "DC_GPIO_VSYNCA_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the HSYNCA & VSYNCA pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_SYNCA_MASK register." }, { col => "heading", table => 1, text => "DC_GPIO_SYNCA_Y - RW - 32 bits - [GpuF0MMReg:0x7E7C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_HSYNCA_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on HSYNCA pad." }, { col => 0, table => 1, text => "DC_GPIO_VSYNCA_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Value on VSYNCA pad." }, { col => undef, table => undef, text => "Output values of the HSYNCA & VSYNCA pads.", }, { col => "heading", table => 2, text => "DC_GPIO_SYNCB_MASK - RW - 32 bits - [GpuF0MMReg:0x7E80]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_HSYNCB_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on HSYNCB pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_VSYNCB_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on VSYNCB pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "Control GPIO functionality of the HSYNCB & VSYNCB pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_SYNCB_A - RW - 32 bits - [GpuF0MMReg:0x7E84]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_HSYNCB_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for HSYNCB when " }, { col => 3, table => 3, text => "DC_GPIO_HSYNCB_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_VSYNCB_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for VSYNCB when " }, { col => undef, table => undef, text => "DC_GPIO_VSYNCB_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the HSYNCB & VSYNCB pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_SYNCB_MASK register." }, ], }, { num => 341, text => [ { col => "heading", table => 0, text => "DC_GPIO_SYNCB_EN - RW - 32 bits - [GpuF0MMReg:0x7E88]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_HSYNCB_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for HSYNCB when " }, { col => 3, table => 0, text => "DC_GPIO_HSYNCB_MASK = 1." }, { col => 0, table => 0, text => "DC_GPIO_VSYNCB_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for VSYNCB when " }, { col => undef, table => undef, text => "DC_GPIO_VSYNCB_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the HSYNCB & VSYNCB pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_SYNCB_MASK register." }, { col => "heading", table => 1, text => "DC_GPIO_SYNCB_Y - RW - 32 bits - [GpuF0MMReg:0x7E8C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_HSYNCB_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on HSYNCB pad." }, { col => 0, table => 1, text => "DC_GPIO_VSYNCB_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => undef, table => undef, text => "Value on VSYNCB pad." }, { col => undef, table => undef, text => "Output values of the HSYNCB & VSYNCB pads.", }, { col => "heading", table => 2, text => "DC_GPIO_HPD_MASK - RW - 32 bits - [GpuF0MMReg:0x7E90]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_HPD1_MASK" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on HPD1 pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_HPD1_PD_EN" }, { col => 1, table => 2, text => 4 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pulldown on HPD1 pad" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_HPD1_PU_EN" }, { col => 1, table => 2, text => 6 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Set to 1 to enable pullup on HPD1 pad" }, { col => 3, table => 2, text => " 0=Disable " }, { col => 3, table => 2, text => " 1=Enable " }, { col => 0, table => 2, text => "DC_GPIO_HPD2_MASK" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Enable/Disable GPIO functionality on HPD2 pad", }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => 3, table => 2, text => "overridden. " }, { col => 0, table => 2, text => "DC_GPIO_HPD3_MASK" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => 3, table => 2, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => 3, table => 2, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "Control GPIO functionality of the Hot Plug Detect pads - all fields are active high.", }, { col => "heading", table => 3, text => "DC_GPIO_HPD_A - RW - 32 bits - [GpuF0MMReg:0x7E94]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_HPD1_A" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for HPD1 when " }, { col => 3, table => 3, text => "DC_GPIO_HPD1_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_HPD2_A" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Asynchronous input for HPD2 when " }, { col => 3, table => 3, text => "DC_GPIO_HPD2_MASK = 1." }, { col => 0, table => 3, text => "DC_GPIO_HPD3_A" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, ], }, { num => 342, text => [ { col => undef, table => undef, text => "Asynchronous inputs for the HPD pads when the GPIO functionality is enabled by the DC_GPIO_HPD_MASK register.", }, { col => "heading", table => 0, text => "DC_GPIO_HPD_EN - RW - 32 bits - [GpuF0MMReg:0x7E98]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "DC_GPIO_HPD1_EN" }, { col => 1, table => 0, text => 0 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for HPD1 when DC_GPIO_HPD1_MASK = ", }, { col => 3, table => 0, text => "1." }, { col => 0, table => 0, text => "DC_GPIO_HPD2_EN" }, { col => 1, table => 0, text => 8 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Output enable for HPD2 when DC_GPIO_HPD2_MASK = ", }, { col => 3, table => 0, text => "1." }, { col => 0, table => 0, text => "DC_GPIO_HPD3_EN" }, { col => 1, table => 0, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Output enable values for the HPD pads when the GPIO functionality is enabled by the DC_GPIO_HPD_MASK register.", }, { col => "heading", table => 1, text => "DC_GPIO_HPD_Y - RW - 32 bits - [GpuF0MMReg:0x7E9C]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_HPD1_Y (R)" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on HPD1 pad." }, { col => 0, table => 1, text => "DC_GPIO_HPD2_Y (R)" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Value on HPD2 pad." }, { col => 0, table => 1, text => "DC_GPIO_HPD3_Y (R)" }, { col => 1, table => 1, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Output values of the HPD pads." }, { col => undef, table => undef, text => "DC_GPIO_PWRSEQ_MASK - RW - 32 bits - [GpuF0MMReg:0x7EA0]", }, { col => undef, table => undef, text => "Field Name" }, { col => undef, table => undef, text => "Bits" }, { col => undef, table => undef, text => "Default" }, { col => undef, table => undef, text => "Description" }, { col => undef, table => undef, text => "DC_GPIO_BLON_MASK" }, { col => undef, table => undef, text => 0 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable/Disable GPIO functionality on BLON pad", }, { col => undef, table => undef, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => undef, table => undef, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => undef, table => undef, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "DC_GPIO_BLON_PD_EN" }, { col => undef, table => undef, text => 4 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable pulldown on BLON pad", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DC_GPIO_BLON_PU_EN" }, { col => undef, table => undef, text => 6 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable pullup on BLON pad", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DC_GPIO_DIGON_MASK" }, { col => undef, table => undef, text => 8 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable/Disable GPIO functionality on DIGON pad", }, { col => undef, table => undef, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => undef, table => undef, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => undef, table => undef, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, { col => undef, table => undef, text => "DC_GPIO_DIGON_PD_EN" }, { col => undef, table => undef, text => 12 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable pulldown on DIGON pad", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DC_GPIO_DIGON_PU_EN" }, { col => undef, table => undef, text => 14 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Set to 1 to enable pullup on DIGON pad", }, { col => undef, table => undef, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "DC_GPIO_ENA_BL_MASK" }, { col => undef, table => undef, text => 16 }, { col => undef, table => undef, text => "0x0" }, { col => undef, table => undef, text => "Enable/Disable GPIO functionality on ENA_BL pad", }, { col => undef, table => undef, text => " 0=Pad Driven by Hardware - Normal Operation ", }, { col => undef, table => undef, text => " 1=Pad Controlled by Software through associated GPIO ", }, { col => undef, table => undef, text => "registers. Pad values generated by hardware are ", }, { col => undef, table => undef, text => "overridden. " }, ], }, { num => 343, text => [ { col => 0, table => 0, text => "DC_GPIO_ENA_BL_PD_EN" }, { col => 1, table => 0, text => 20 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable pulldown on ENA_BL pad", }, { col => 3, table => 0, text => " 0=Disable " }, { col => 3, table => 0, text => " 1=Enable " }, { col => 0, table => 0, text => "DC_GPIO_ENA_BL_PU_EN" }, { col => 1, table => 0, text => 22 }, { col => 2, table => 0, text => "0x0" }, { col => 3, table => 0, text => "Set to 1 to enable pullup on ENA_BL pad" }, { col => 3, table => 0, text => " 0=Disable " }, { col => undef, table => undef, text => " 1=Enable " }, { col => undef, table => undef, text => "Control GPIO functionality of the BLON, DIGON & ENA_BL pads - all fields are active high.", }, { col => "heading", table => 1, text => "DC_GPIO_PWRSEQ_A - RW - 32 bits - [GpuF0MMReg:0x7EA4]", }, { col => 0, table => 1, text => "Field Name" }, { col => 1, table => 1, text => "Bits" }, { col => 2, table => 1, text => "Default" }, { col => 3, table => 1, text => "Description" }, { col => 0, table => 1, text => "DC_GPIO_BLON_A" }, { col => 1, table => 1, text => 0 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for BLON when " }, { col => 3, table => 1, text => "DC_GPIO_BLON_MASK = 1." }, { col => 0, table => 1, text => "DC_GPIO_DIGON_A" }, { col => 1, table => 1, text => 8 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for BIGON when " }, { col => 3, table => 1, text => "DC_GPIO_DIGON_MASK = 1." }, { col => 0, table => 1, text => "DC_GPIO_ENA_BL_A" }, { col => 1, table => 1, text => 16 }, { col => 2, table => 1, text => "0x0" }, { col => 3, table => 1, text => "Asynchronous input for BIGON when " }, { col => undef, table => undef, text => "DC_GPIO_ENA_BL_MASK = 1." }, { col => undef, table => undef, text => "Asynchronous inputs for the BLON, DIGON & ENA_BL pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_PWRSEQ_MASK register." }, { col => "heading", table => 2, text => "DC_GPIO_PWRSEQ_EN - RW - 32 bits - [GpuF0MMReg:0x7EA8]", }, { col => 0, table => 2, text => "Field Name" }, { col => 1, table => 2, text => "Bits" }, { col => 2, table => 2, text => "Default" }, { col => 3, table => 2, text => "Description" }, { col => 0, table => 2, text => "DC_GPIO_BLON_EN" }, { col => 1, table => 2, text => 0 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable for BLON when DC_GPIO_BLON_MASK = ", }, { col => 3, table => 2, text => "1." }, { col => 0, table => 2, text => "DC_GPIO_DIGON_EN" }, { col => 1, table => 2, text => 8 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable for DIGON when DC_GPIO_DIGON_MASK ", }, { col => 3, table => 2, text => "= 1." }, { col => 0, table => 2, text => "DC_GPIO_ENA_BL_EN" }, { col => 1, table => 2, text => 16 }, { col => 2, table => 2, text => "0x0" }, { col => 3, table => 2, text => "Output enable for ENA_BL when " }, { col => undef, table => undef, text => "DC_GPIO_ENA_BL_MASK = 1." }, { col => undef, table => undef, text => "Output enable values for the BLON, DIGON & ENA_BL pads when the GPIO functionality is enabled by the ", }, { col => undef, table => undef, text => "DC_GPIO_PWRSEQ_MASK register." }, { col => "heading", table => 3, text => "DC_GPIO_PWRSEQ_Y - RW - 32 bits - [GpuF0MMReg:0x7EAC]", }, { col => 0, table => 3, text => "Field Name" }, { col => 1, table => 3, text => "Bits" }, { col => 2, table => 3, text => "Default" }, { col => 3, table => 3, text => "Description" }, { col => 0, table => 3, text => "DC_GPIO_BLON_Y (R)" }, { col => 1, table => 3, text => 0 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on BLON pad." }, { col => 0, table => 3, text => "DC_GPIO_DIGON_Y (R)" }, { col => 1, table => 3, text => 8 }, { col => 2, table => 3, text => "0x0" }, { col => 3, table => 3, text => "Value on DIGON pad." }, { col => 0, table => 3, text => "DC_GPIO_ENA_BL_Y (R)" }, { col => 1, table => 3, text => 16 }, { col => 2, table => 3, text => "0x0" }, { col => undef, table => undef, text => "Value on ENA_BL pad." }, { col => undef, table => undef, text => "Output values of the BLON, DIGON & ENA_BL pads.", }, { col => "heading", table => 4, text => "DC_GPIO_PAD_STRENGTH_1 - RW - 32 bits - [GpuF0MMReg:0x7ED4]", }, { col => 0, table => 4, text => "Field Name" }, { col => 1, table => 4, text => "Bits" }, { col => 2, table => 4, text => "Default" }, { col => 3, table => 4, text => "Description" }, { col => 0, table => 4, text => "SYNC_STRENGTH_SN" }, { col => 1, table => 4, text => "27:24" }, { col => 2, table => 4, text => "0x7" }, { col => 3, table => 4, text => "Control SN strengths for HSYNCA, HSYNCB, VSYNCA & ", }, { col => 3, table => 4, text => "VSYNCB" }, { col => 0, table => 4, text => "SYNC_STRENGTH_SP" }, { col => 1, table => 4, text => "31:28" }, { col => 2, table => 4, text => "0x4" }, { col => 3, table => 4, text => "Control SP strengths for HSYNCA, HSYNCB, VSYNCA & ", }, { col => 3, table => 4, text => "VSYNCB" }, ], }, { num => 344, text => [ { col => "heading", table => 0, text => "DC_GPIO_PAD_STRENGTH_2 - RW - 32 bits - [GpuF0MMReg:0x7ED8]", }, { col => 0, table => 0, text => "Field Name" }, { col => 1, table => 0, text => "Bits" }, { col => 2, table => 0, text => "Default" }, { col => 3, table => 0, text => "Description" }, { col => 0, table => 0, text => "STRENGTH_SN" }, { col => 1, table => 0, text => "3:0" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Control SN strengths for DDC1, DDC2, DDC3, GENERICA, ", }, { col => 3, table => 0, text => "GENERICB, GENERICC, HPD1 & HPD2 pads" }, { col => 0, table => 0, text => "STRENGTH_SP" }, { col => 1, table => 0, text => "7:4" }, { col => 2, table => 0, text => "0x4" }, { col => 3, table => 0, text => "Control SP strengths for DDC1, DDC2, DDC3, GENERICA, ", }, { col => 3, table => 0, text => "GENERICB, GENERICC, HPD1 & HPD2 pads" }, { col => 0, table => 0, text => "PWRSEQ_STRENGTH_SN" }, { col => 1, table => 0, text => "19:16" }, { col => 2, table => 0, text => "0x7" }, { col => 3, table => 0, text => "Control SN strengths for BLON & DIGON pads", }, { col => 0, table => 0, text => "PWRSEQ_STRENGTH_SP" }, { col => 1, table => 0, text => "23:20" }, { col => 2, table => 0, text => "0x4" }, { col => 3, table => 0, text => "Control SP strengths for BLON & DIGON pads", }, ], }, ]